872S480BKLF

Differential-to-HSTL Zero Delay Clock Generator ICS872S480 DATA SHEET General Description The ICS872S480 is a Zero Delay Clock Generator with hitless input clock switching capability. The ICS872S480 is ideal for use in redundant, fault tolerant clock trees where low jitter frequency synthesis are critical. The device receives two differential clock signals from which it generates two outputs with “zero” delay. The output and feedback dividers are configured to allow for a 1:1 frequency generation ratio. The ICS872S480 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of an invalid clock input (stuck LOW or HIGH for at least one complete clock period of the VCO feedback frequency), the loss of reference monitor will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. Once the primary clock is restored to a good state, the DCS will automatically switch back to the primary clock input. The low jitter characteristics with input clock monitoring and DCS capability make the ICS872S480 an ideal choice for DDR3 applications requiring fault tolerant reference clocks. Features • • • • • • • • • • • • • • Three differential HSTL output pairs Selectable differential CLKx, nCLKx input pairs CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL Output frequency range: 350MHz to 950MHz Input frequency range: 350MHz to 950MHz VCO range: 970MHz to 2250MHz External feedback for “zero delay” clock regeneration with configurable frequencies Static phase offset: ±100ps (maximum) Cycle-to-cycle jitter: 25ps (maximum) Output skew: 20ps (maximum) 3.3V operating voltage supply Selectable DDR3 or DDR3 low voltage output 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Function Table Input FREQ_SEL 0 1 (default) Output Divider 2 4 Input & Output Frequency (MHz) Pin Assignment AUTO_SEL GND VDD 485 350 950 562.5 CLK0 nCLK0 GND 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 9 nQFB 10 11 12 13 14 15 16 nQ1 Q1 Q0 QFB nQ0 VDD VDD 17 VDD LOR0 LOR1 CLK_IND GND FREQ_SEL OE VDDA Output Voltage Table Input VOUT_SEL 0 (default) 1 HSTL Output Style 1.5V 1.35V CLK1 nCLK1 PLL_BYPASS FB_IN nFB_IN ICS872S480 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS872S480BK REVISION A APRIL 19, 2011 1 ©2011 Integrated Device Technology, Inc. VDD Minimum Maximum VOUT_SEL REF_SEL nc nc ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Block Diagram VOUT_SEL OE PLL_Bypass Pulldown Pullup Pulldown Q0, nQ0 CLK0 nCLK0 Pullup Pulldown Activity Detector 0 1 Activity Detector 1 PD + CP + LF Output Divider LOR0 CLK1 nCLK1 Pullup Pulldown Q1, nQ1 VCO 0 LOR1 QFB, nQFB CLK_IND REF_SEL Pulldown Dynamic Switch Logic 1 0 AUTO_SEL Pullup FB_IN nFB_IN Pullup Pulldown FREQ_SEL Pullup ICS872S480BK REVISION A APRIL 19, 2011 2 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number 1 2 3, 20, 28 4 5 6 7 8 9, 10 11, 16, 24, 25, 32 12, 13 14, 15 17 18 19 21 22 23 26 27, 29 30 Name CLK0 nCLK0 GND CLK1 nCLK1 PLL_BYPASS FB_IN nFB_IN nQFB, QFB VDD nQ1, Q1 nQ0, Q0 VDDA OE FREQ_SEL CLK_IND LOR1 LOR0 Input Input Power Input Input Input Input Input Output Power Output Output Power Input Input Output Output Output Input Unused Input Pullup Pulldown Pullup Pullup Pulldown Pullup Pulldown Pulldown Pullup Type Pulldown Pullup Description Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Non-inverting differential clock input. Inverting differential clock input. PLL bypass pin. When HIGH, the PLL is bypassed and the reference clock is passed directly to the output dividers. LVCMOS/LVTTL interface levels. Non-inverting differential external feedback input. Inverting differential external feedback input. Differential feedback output pair. HSTL interface levels. See Table 4D. Core supply pins. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Analog supply pin. Output enable pin. LVCMOS/LVTTL interface levels. Frequency select pin. LVCMOS/LVTTL interface levels. Clock indicator pin. When LOW, CLK0, nCLK0 is selected. When HIGH, CLK1, nCLK1 is selected. Loss of Reference Indicator for CLK1, nCLK1. LVCMOS/LVTTL interface levels. Loss of Reference Indicator for CLK0, nCLK0. LVCMOS/LVTTL interface levels. Output voltage select pin. LVCMOS/LVTTL interface levels. No connect. Dynamic Clock switch enable pin. When LOW, disables internal Dynamic Clock Switch circuitry and CLK_INDICATOR will track REF_SEL. When HIGH, Dynamic Clock Switch is enabled. LVCMOS/LVTTL interface levels. Reference clock select pin. When LOW selects CLK0, nCLK0, when HIGH selects CLK1, nCLK1. LVCMOS/LVTTL interface levels. VOUT_SEL nc AUTO_SEL 31 REF_SEL Input Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 2 51 51 Maximum Units pF kΩ kΩ ICS872S480BK REVISION A APRIL 19, 2011 3 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 42.7°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Outputs terminated 50Ω to GND Test Conditions Minimum 3.135 VDD –0.25 Typical 3.3 3.3 Maximum 3.465 VDD 275 25 Units V V mA mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage PLL_BYPASS, REF_SEL, VOUT_SEL OE, FREQ_SEL, AUTO_SEL PLL_BYPASS, REF_SEL, VOUT_SEL OE, FREQ_SEL, AUTO_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 Test Conditions Minimum 2.2 -0.3 Typical Maximum VDD + 0.3 0.8 150 10 Units V V µA µA µA µA IIH Input High Current IIL Input Low Current ICS872S480BK REVISION A APRIL 19, 2011 4 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol IIH Parameter Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.15 0.3 1.75 VDD – 0.85 Minimum Typical Maximum 150 10 Units µA µA µA µA V V IIL VPP VCMR Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. HSTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol VOX Parameter Output Crosspoint Voltage, NOTE 1 Differential Output Voltage; NOTE 1 Test Conditions VOUT_SEL = 0 VOUT_SEL = 1 VOUT_SEL = 0 VOUT_SEL = 1 Minimum 0.7 0.6 0.8 0.8 Typical 0.8 0.7 0.9 0.9 Maximum 0.9 0.8 1.0 1.0 Units V V V V VOD NOTE 1: Outputs terminated with 50Ω to ground. Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol FIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions FSEL = 1 FSEL = 0 Minimum 485 350 Typical Maximum 950 562.5 Units MHz MHz ICS872S480BK REVISION A APRIL 19, 2011 5 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol fOUT Parameter Output Frequency fOUT = 400MHz t(Ø) Static Phase Offset; NOTE 1, 2 fOUT = 533.3MHz fOUT = 666.6MHz fOUT = 800MHz fOUT = 400MHz tdyn(Ø) Dynamic Phase Offset; NOTE 7 fOUT = 533.3MHz fOUT = 666.6MHz fOUT = 800MHz pdev tsk(o) tjit(cc) tL tLdcs Output Period Deviation; NOTE 3, 7 Output Skew; NOTE 2, 4 Cycle-to-Cycle Jitter; NOTE 3, 7 PLL Lock Time; NOTE 7 DCS PLL Lock Time; NOTE 6, 7 fOUT = 400MHz 2.00 2.00 2.00 2.50 2.00 2.00 2.50 3.00 47 fOUT = 533.3MHz fOUT = 666.6MHz fOUT = 800MHz fOUT = 400MHz fOUT = 533.3MHz fOUT = 666.6MHz fOUT = 800MHz odc Output Duty Cycle 1.7 3.50 4.25 4.25 5.25 3.85 4.50 4.65 5.65 5.75 6.50 6.75 8.65 6.35 6.85 7.25 8.25 53 Test Conditions Minimum 350 -25 -50 -50 -50 Typical Maximum 950 75 50 50 50 ±20 ±25 ±20 ±20 100 20 25 3 Units MHz ps ps ps ps ps ps ps ps ps ps ps ms µs V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns % VOUT_SEL = 0 tSLEW Output Slew Rate; NOTE 5 VOUT_SEL = 1 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. Characterized using HSTL input level of 900mV, swing centered around 0.6V. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: This parameter is defined as the maximum output period deviation during a dynamic switch event with reference inputs 180° out of phase. This does not factor in any cycle-to-cycle jitter seen on the input or output. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: Output slew rate is measured at VOX ± 150mV for VOUT_SEL = 0 and VOX ±135mV for VOUT_SEL = 1. NOTE 6: This parameter is defined as PLL lock time after a dynamic switch event with reference inputs 180° out of phase. NOTE 7: This parameter is guaranteed by characterization. Not tested in production. ICS872S480BK REVISION A APRIL 19, 2011 6 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V ± 5% 3.3V ± 5% VDD VDD VDDA Qx SCOPE nCLK0, nCLK1 V PP Cross Points V CMR HSTL nQx CLK0, CLK1 GND GND 0V 3.3V Output Load AC Test Circuit Differential Input Level nQ[0:1] nQx Q[0:1] Qx t cycle n ➤ t jit(cc) = |t cycle n – t cycle n+1| 1000 Cycles Cycle-to-Cycle Jitter nCLK[0:1] CLK[0:1] nFB_IN FB_IN nQ[0:1] Q[0:1] ➤ t (Ø) t(Ø)mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on controlled edges) Static Phase Offset ICS872S480BK REVISION A APRIL 19, 2011 ➤ ➤ ➤ t cycle n+1 ➤ nQy Qy t sk(o) Output Skew t PW t PERIOD odc = t PW t PERIOD x 100% Output Duty Cycle/Pulse Width/Period 7 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued nCLK[0:1] nCLK[0:1] ∆t +VAC VOX VOD ∆t nFB_IN -VAC FB_IN Histogram Dynamic Phase Offset ➤ t (Ø) Dynamic Phase Offset =  t(Ø) – t(Ø)mean tdyn(Ø) = Peak-to-Peak value of Dynamic Phase Offset Histogram Where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on the controlled edges Dynamic Phase Offset PLL Lock Time ICS872S480BK REVISION A APRIL 19, 2011 ➤ ➤ t (Ø)mean VAC = 150mV for VOUT_SEL = 0 VAC = 135mV for VOUT_SEL = 1 tSLEW = 2 * VAC ∆t Slew Rate 8 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Applications Information Clock Redundancy and Reference Selection The ICS872S480 accepts two differential input clocks, CLK0, nCLK0 and CLK1, nCLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. CLK0, nCLK0 is defined as the initial, or primary clock, while the remaining clock is the redundant or secondary clock. The output signal CLK_IND indicates which clock input is being used as the reference (LOW = CLK0, nCLK0, HIGH = CLK1, nCLK1). Output Transitioning After a successful DCS initiated clock switch, the internal PLL of the ICS872S480 will begin slewing to phase/frequency alignment of the newly selected clock input. The PLL will achieve lock to the new input with minimal phase disturbance at the outputs. Recommended Power-up Sequence 1.Before startup, set AUTO_SEL low so the PLL will operate in manual switch mode, plus set REF_SEL low to ensure that the primary reference clock, CLK0, nCLK0, is selected. This will ensure that during startup, the PLL will acquire lock using the primary reference clock input. 2.Once powered-up, and assuming a stable clock is present at the primary clock input, the PLL will begin to phase/frequency slew as it attempts to achieve lock with the input reference clock. 3.Drive AUTO_SEL HIGH to enable DCS mode. Failure Detection and Alarm Signaling Within the ICS872S480 device, CLK0, nCLK0 and CLK1, nCLK1 are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period of the feedback. Upon detection of a failure, the corresponding loss-of-reference signal, LOR0 or LOR1, will be set HIGH. The input clocks are continuously monitored and the loss-of-reference signals will continue to reflect the real-time status of each input clock. Manual Clock Switching When input signal AUTO_SEL is driven LOW, the clock specified by REF_SEL will always be used as the reference, even when a clock failure is detected at the reference. In order to switch between CLK0, nCLK0 and CLK1, nCLK1 as the reference clock, the level on REF_SEL must be driven to the appropriate level. When the level on REF_SEL is changed, the selection of the new clock will take place, and CLK_IND will be updated to indicate which clock is now supplying the reference to the PLL. Alternate Power-up Sequence If both input clocks are valid before power up, the part may be powered-up in DCS mode. However, it cannot be guaranteed that the PLL will achieve lock with one specific input clock. 1.Before startup, leave AUTO_SEL floating and the internal pullup will enable DCS mode. 2.Once powered up, the PLL will begin to phase/frequency slew as it attempts to achieve lock with one of the input reference clocks. Dynamic Clock Switching The Dynamic Clock Switching (DCS) process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. When input signal AUTO_SEL is not driven HIGH, an internal pullup pulls it HIGH so that DCS is enabled. If DCS is enabled and a failure occurs on the initial clock, the ICS872S480 device will check the status of the secondary clock. If the secondary clock is detected as a good input clock, the ICS872S480 will automatically de-select the initial clock as the reference and multiplex in the secondary clock. When a successful switch from the initial to secondary clock has been accomplished, CLK_IND will be updated to indicate the new reference. If and when the fault on the initial clock is corrected, the corresponding loss-of-reference flag will be updated to represent this clock as good again. Once updated, the DCS will undergo an automatic clock switch. See the Dynamic Clock Switch State Diagram and for additional details on the functionality of the Dynamic Clock Switching circuit. ICS872S480BK REVISION A APRIL 19, 2011 9 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR ICS872S480BK REVISION A APRIL 19, 2011 State Diagram 10 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS872S480BK REVISION A APRIL 19, 2011 11 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK 3.3V 3.3V Zo = 50Ω CLK Zo = 50Ω nCLK LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω Differential Input R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter HSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω CLK Zo = 50Ω nCLK R1 100Ω CLK R3 125Ω R4 125Ω 3.3V Zo = 50Ω 3.3V LVPECL R1 84Ω R2 84Ω Differential Input Zo = 50Ω nCLK LVDS Receiver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 3.3V *R3 33Ω Zo = 50Ω CLK Zo = 50Ω nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS872S480BK REVISION A APRIL 19, 2011 12 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: HSTL Outputs All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. HSTL Output Termination VDDO VDD Zo = 50 + Zo = 50 HSTL R1 50 R2 50 HSTL ICS HiPerClockS HSTL Driv er Figure 4. Output Termination ICS872S480BK REVISION A APRIL 19, 2011 13 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS872S480BK REVISION A APRIL 19, 2011 14 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Schematic Example Figure 6 shows an example of ICS872S480 application schematic. In this example, the device is operated at VDD = 3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS872S480 provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. R1 3.3V R2 125 R3 125 AUTO_SEL REF_SEL Zo = 50 CLK0 nCLK0 Zo = 50 R6 84 R7 84 1 2 3 4 5 6 7 8 U1 VDD VOUT_SEL VDD VDD 32 31 30 29 28 27 26 25 CLK_IND 2.2K LD3 R5 LOR0 2.2K R4 LOR1 2.2K LD2 LD1 LVPECL Driv er VD D R EF _SE L A U T O _S EL nc GN D nc V O U T _S EL VD D 3.3V R8 125 R9 125 PLL_BYPASS CLK0 nCLK0 GND CLK1 nCLK1 PLL_BYPASS FB_IN nFB_IN VDD LOR0 LOR1 CLK_IND GND FREQ_SEL OE VDDA 24 23 22 21 20 19 18 17 Q0 FREQ_SEL OE nQ0 Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 CLK1 nCLK1 nF B _IN F B _IN nQ F B QFB VD D nQ 1 Q1 nQ 0 Q0 VD D R10 50 VDDA R12 10 R11 50 Zo = 50 R13 84 R14 84 R15 50 R16 50 VDD VDD nQ1 Q1 nQ0 Q0 C1 0.1u LVPECL Driv er 9 10 11 12 13 14 15 16 C2 10u VDD=3.3V BLM18BB221SN1 1 2 Ferrite Bead C4 VDD1 C5 10uF 0.1uF nQ1 Zo = 50 Ohm Q1 Zo = 50 Ohm + 3.3V Logic Control Input Examples VDD Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install 3.3V 1 C6 0.1uF C3 0.1uF To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins BLM18BB221SN1 2 Ferrite Bead C7 10uF (U1, 11) C8 0.1u (U1, 16) C9 0.1u (U1, 24) C10 0.1u (U1, 25) (U1, 32) C11 0.1u VDD C12 0.1u R17 50 R18 50 Figure 6. ICS872S480 Schematic Layout ICS872S480BK REVISION A APRIL 19, 2011 15 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS872S480. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for theICS872S480 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (275mA + 25mA) = 1039.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.040W * 42.7°C/W = 114.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 42.7°C/W 1 37.3°C/W 2.5 33.5°C/W ICS872S480BK REVISION A APRIL 19, 2011 16 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 32-lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 42.7°C/W 1 37.3°C/W 2.5 33.5°C/W Transistor Count The transistor count for ICS872S480 is: 2110 ICS872S480BK REVISION A APRIL 19, 2011 17 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e E2 2 (Re f.) (Ref.) (N -1)x e (R ef.) N &N Even e (Ty p.) 2 If N & N Anvil Anvil Singulation Singula tion are Even OR To p View b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 N &N Odd Th er mal Ba se Bottom View w/Type A ID Bottom View w/Type C ID 2 1 CHAMFER 2 1 RADIUS 4 N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS872S480BK REVISION A APRIL 19, 2011 18 ©2011 Integrated Device Technology, Inc. NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 872S480BKLF 872S480BKLFT Marking ICS72S480BL ICS72S480BL Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS872S480BK REVISION A APRIL 19, 2011 19 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.