9173B-15CS08LF

PRELIMINARY DATASHEET VIDEO GENLOCK PLL Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The IDT9173B contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The ICS674-01 can be used as the external feedback divider. A common application of the IDT9173B is the implementation of a video genlock circuit. Because of this, the IDT9173B inputs operate on the negative-going clock edge. The IDT9173B is pin and function compatible to the AV9173-01/15. IDT9173B Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • • • • On-chip loop filter Single 5 V power supply Low power CMOS technology 8-pin SOIC package Block Diagram IDT™ VIDEO GENLOCK PLL 1 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Pin Assignment FBIN IN GND FS0 1 2 3 4 8 pin SOIC 8 7 6 5 CLK2 VDD CLK1 OE Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name FBIN IN GND FS0 OE CLK1 VDD CLK2 Pin Type Input Input Power Input Input Output Power Output Feedback input. Pin Description Input for reference sync pulse. Ground. Frequency select 0 input. Output enable. Clock output 1. Power supply (+5 V). Clock output 2 (divided-by-2 from Clock 1). Allowable Input Frequency to Output Frequency for IDT9173B-01 (in MHz) (IDT9173B-15 outputs run at exactly half of the IDT9173B-01 frequencies) fOUT for FS = 0 fIN (kHz) 12 < fIN < 14 kHz 14 < fIN < 17 kHz 17 < fIN < 30 kHz 30 < fIN < 35 kHz 35 < fIN < 1000 kHz CLK1 Output 44.0 to 75 30.0 to 75 25.0 to 75 15.0 to 75 10.0 to 75 CLK2 Output 22.0 to 37.5 15.0 to 37.5 12.5 to 37.5 7.5 to 37.5 5.0 to 37.5 fOUT for FS = 1 CLK1 Output 11.0 to 18.75 7.5 to 18.75 6.25 to 18.75 3.75 to 18.75 2.5 to 18.75 CLK2 Output 5.5 to 9.375 3.75 to 9.375 3.125 to 9.375 1.875 to 9.375 1.25 to 9.375 IDT™ VIDEO GENLOCK PLL 2 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Using the IDT9173B in Genlock Applications Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video “genlock” (generator lock) circuit is required. The IDT9173B integrates the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the IDT9173B is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (H-SYNC) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. The clock feedback divider shown in Figure 1 is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: fOUT = fIN x N where N is external divide ratio Both input pins IN and FBIN respond only to negative-going clock edges of the input signal. The H-SYNC signal must be constant frequency in the 12 kHz to 1 MHz range and stable (low clock jitter) for creation of a stable output clock. The output hook-ups of the IDT9173B are dictated by the desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration. FS0 State 0 0 1 1 Output Used CLK1 CLK2 CLK1 CLK2 Frequency/Range IDT9173B-01 10 to 75 MHz 5 to 37.5 MHz 2.5 to 18.75 MHz 1.25 to 9.375 MHz Frequency/Range IDT9173B-15 5 to 37.5 MHz 2.5 to 18.75 MHz 1.25 to 9.375 MHz 0.625 to 4.6875 MHz Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). Figure 1: Typical Application of IDT9173B in a Video Genlock System IDT™ VIDEO GENLOCK PLL 3 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT9173B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD Storage Temperature Voltage on I/O Pins referenced to GND Junction Temperature Soldering Temperature Power Dissipation 7V -65 to +150° C Rating GND - 0.5 V to VDD + 0.5 V 125° C 260° C 0.5 Watts Recommended Operation Conditions Parameter Operating Temperature under Bias Power Supply Voltage (measured with respect to GND) Min. -0 +4.75 Typ. +5 V Max. +70 +5.25 Units °C V IDT™ VIDEO GENLOCK PLL 4 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70° C Parameter Operating Supply Current Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Output High Voltage Output High Voltage 1 1 1 Symbol IDD VIH VIL IIL IIH VOL VOH1 VOH2 VOH3 Conditions No load,50 MHz VDD = 5 V VDD = 5 V VIN = 0V VIN = VDD IOL = 8 mA IOH = -1 mA IOH = -4 mA IOH = -8 mA Min. Typ. 20 Max. 50 0.8 Units mA V V µA 2.0 -5 -5 VDD-0.4 VDD-0.8 2.4 5 0.4 µA V V V V Notes: 1. Duty cycle measured at 1.4 V. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. AC Electrical Characteristics Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70° C Parameter Output Clock Rise Time Output Clock Fall Time Output Rise Time Output Rise Time Output Fall Time Output Fall Time One-Sigma Jitter Jitter, Absolute Jitter, Absolute One-Sigma Jitter 1 1 1 1 Symbol ICLKr ICLKf tr1 tr2 tf1 tf2 Conditions Min. Typ. Max. Units 10 10 ns ns ns ns ns ns % ps ps % % ns 1000 kHz 15 pF load, 20% to 80% 15 pF load, 20% to 80% 15 pF load, 80% to 20% 15 pF load, 80% to 20% 15 pF load 40 3 3 0.6 1.4 0.8 0.8 47 120 -400 ±250 1.5 3.0 2.0 2.0 55 250 400 1 2 1 1 1 Output Duty Cycle 1, 5 1, 5 T1S1 TABS1 T1S2 TABS2 2 CLK1 frequency , 25 MHz CLK1 frequency , 25 MHz CLK1 frequency < 25 MHz CLK1 frequency < 25 MHz 1, 5 1, 5 1 Line-to-Line Jitter , Absolute Input Frequency 1, TLABS fIN see allowable fi below 12 ±4 IN or FBIN IDT™ VIDEO GENLOCK PLL 5 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Parameter CLK1 Frequency, -01 1, 3, 4 Symbol fCLK1 Conditions 12 < fIN < 14 kHz 14 < fIN < 17 kHz 17 < fIN < 30 kHz 30 < fIN < 35 kHz 35 < fIN < 1000 kHz Min. 44 30 25 15 10 22 15 12.5 7.5 5 Typ. Max. Units 75 75 75 75 75 37.5 37.5 37.5 37.5 37.5 MHz MHz CLK1 Frequency, -15 1, 3, 4 fCLK1 12 < fIN < 14 kHz 14 < fIN < 17 kHz 17 < fIN < 30 kHz 30 < fIN < 35 kHz 35 < fIN < 1000 kHz Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following these guidelines, the IDT9173B will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot variation. 5. Jitter values are measured at frequencies > 25 MHz for IDT9173B-01, for IDT9173B-15, jitter is measured at frequency > 12.5 MHz. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol θJA θJA θJA θJC ΨJT Conditions Still air 1 m/s air flow 3 m/s air flow Still air Min. Typ. 150 140 120 40 20 Max. Units ° C/W ° C/W ° C/W ° C/W ° C/W Thermal Resistance Junction to Case Thermal Resistance Junction to Top of Case IDT™ VIDEO GENLOCK PLL 6 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol Min Max Inches Min Max E INDEX AREA H 12 D A A1 B C D E e H h L α h x 45 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° A A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number 9173B-01CS08LF 9173B-01CS08LFT 9173B-15CS08LF 9173B-15CS08LFT Marking TBD Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Temperature 0 to +70° 0 to +70° 0 to +70° 0 to +70° C C C C Parts ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ VIDEO GENLOCK PLL 7 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Revision History Rev. A Originator R.Willner Date 09/23/08 Description of Change New datasheet. IDT™ VIDEO GENLOCK PLL 8 IDT9173B REV A 092308 IDT9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA