92HD92

DATASHEET SINGLE CHIP PC AUDIO SYSTEM CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO+I2S 92HD92 Features • 4 Channels (2 stereo DACs and 2 stereo ADCs) with 24-bit resolution • • • Supports full-duplex stereo audio and simultaneous VoIP Provides a mono output 2.1 audio crossover support Description The 92HD92 single-chip audio system is a low power optimized, high fidelity, 4-channel audio codec with integrated speaker amplifier, capless headphone amplifier, and low drop out voltage regulator. Dual High Definition Audio and I2S Interfaces allow for docking and secondary audio support with a single codec. The integrated combo jack allows for dual-function headphone and headset detection. The integrated high-pass and band-pass filters allow for Hardware EQ and speaker protection. The high integration of the 92HD92 enables the smallest PCB footprint with the lowest system audio BOM count and cost. The 92HD92 provides high quality HD Audio capability to notebook and business desktop PC applications. • 2W/channel Class-D stereo BTL speaker amplifier @ 4 ohms and 5V • • 10 band hardware parametric equalizer Hardware compressor limiter • • • • • Capless headphone amplifier with charge pump/LDO I2S support (2 input, 1 output) Aux Audio Mode with I2C Combo Jack Support allowing for dual-function headphone and headset detection Speaker Protection • • Dedicated BTL high pass filter Mono bandpass filter • • • • • • • • • • • Full HDA015-B low power support Internal digital core LDO voltage regulator Microsoft WLP desktop premium logo compliant Dual SPDIF for WLP compliant support of simultaneous HDMI and SPDIF output Support for 1.5V and 3.3V HDA signaling Two digital microphone inputs (mono, stereo, or quad microphones) High performance analog mixer 2 adjustable VREF Out pins for analog microphone bias 3 analog ports with port presence detect (2 single ended, 1 BTL) Digital PC Beep support 48-pad QFN RoHS package IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 1 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Full HDA015-B low power support • • • • • • Audio inactivity transitions codec from D0 to D3 low power mode Resume from D3 to D0 with audio activity in < 10 msec D3 to D0 transition with < -65dB pop/click Port presence detect in D3 with or without bit clock PC beep wake up in D3 Additional vendor specific modes for even lower power Software Support • • Intuitive IDT HD Sound graphical user interface that allows configurability and preference settings 12 band fully parametric equalizer • Constant, system-level effects tuned to optimize a particular platform can be combined with user-mode “presets” tailored for specific acoustical environments and applications • System-level effects automatically disabled when external audio connections made Dynamics Processing • Enables improved voice articulation • Compressor/limiter allows higher average volume level without resonances or damage to speakers. IDT Vista APO wrapper • Enables multiple APOs to be used with the IDT Driver Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression Dynamic Stream Switching • Improved multi-streaming user experience with less support calls Broad 3rd party branded software including Creative, Dolby, DTS, and SRS • • • • • IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 2 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO TABLE OF CONTENTS 1. DESCRIPTION ........................................................................................................................ 11 1.1. Overview ..........................................................................................................................................11 1.2. Orderable Part Numbers ..................................................................................................................11 2. DETAILED DESCRIPTION ..................................................................................................... 12 2.1. Port Functionality .............................................................................................................................12 2.1.1. Port Characteristics ............................................................................................................12 2.1.2. Vref_Out .............................................................................................................................14 2.1.3. Jack Detect ........................................................................................................................14 2.1.4. SPDIF Output .....................................................................................................................14 2.2. Mono Output ....................................................................................................................................16 2.3. Mono output Band-Pass Filter .........................................................................................................17 2.3.1. Filter Description ................................................................................................................17 2.4. Mixer ................................................................................................................................................17 2.5. ADC Multiplexers .............................................................................................................................17 2.6. Power Management .........................................................................................................................17 2.7. AFG D0 ............................................................................................................................................18 2.8. AFG D1 ............................................................................................................................................19 2.9. AFG D2 ............................................................................................................................................19 2.10. AFG D3 ..........................................................................................................................................19 2.10.1. AFG D3cold .....................................................................................................................19 2.11. Vendor Specific Function Group Power States D4/D5 ..................................................................19 2.12. Low-voltage HDA Signaling ...........................................................................................................20 2.13. Multi-channel capture ....................................................................................................................20 2.14. EAPD .............................................................................................................................................22 2.15. Digital Microphone Support ...........................................................................................................25 2.16. Analog PC-Beep ............................................................................................................................29 2.17. Digital PC-Beep .............................................................................................................................31 2.18. Headphone Drivers ........................................................................................................................32 2.19. BTL Amplifier .................................................................................................................................32 2.20. BTL Amplifier High-Pass Filter .......................................................................................................32 2.20.1. Filter Description ..............................................................................................................33 2.21. EQ ..................................................................................................................................................33 2.22. Combo Jack Detection ...................................................................................................................33 2.23. GPIO ..............................................................................................................................................34 2.23.1. GPIO Pin mapping and shared functions .........................................................................34 2.23.2. SPDIF/Digital Microphone/GPIO Selection ......................................................................34 2.23.3. Digital Microphone/GPIO Selection .................................................................................34 2.24. HD Audio HDA015-B support ........................................................................................................34 2.25. Digital Core Voltage Regulator ......................................................................................................35 2.26. Digital Audio Port (I2S) ..................................................................................................................36 2.26.1. Characteristics .................................................................................................................36 2.26.2. Left Justified Audio Interface ............................................................................................38 2.26.3. Right Justified Audio Interface (assuming n-bit word length) ...........................................38 2.26.4. I2S Format Audio Interface ..............................................................................................38 2.27. Microphone Mute Input ..................................................................................................................38 2.28. Aux Audio Support .........................................................................................................................40 2.28.1. General conditions in Aux Audio Mode: ...........................................................................40 2.28.2. Entering Aux Audio Mode ................................................................................................41 2.28.3. Firmware/Software Requirements: ...................................................................................41 2.28.4. Part Options Supporting I2S I/O ......................................................................................42 2.28.5. “Playback Path” Port Behavior (Digital I/O) ......................................................................42 2.28.6. When Port E presence detect = 0 ....................................................................................42 2.28.7. When Port E presence detect = 1 ....................................................................................42 2.28.8. “Record Path” Port Behavior (Digital I/O) .........................................................................43 2.28.9. EAPD ...............................................................................................................................44 2.28.10. Class-D BTL Issues .......................................................................................................44 2.28.11. Firmware/Software Requirements: .................................................................................44 2.28.12. SYSTEM DIAGRAMS ....................................................................................................45 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 3 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.28.13. I2C control interface .......................................................................................................47 2.28.14. Register Write Cycle ......................................................................................................47 2.28.15. Multiple Write Cycle .......................................................................................................47 2.29. Register Read Cycle ......................................................................................................................48 2.29.1. Multiple Read Cycle .........................................................................................................48 2.29.2. I2C Registers ...................................................................................................................49 3. CHARACTERISTICS ............................................................................................................... 72 3.1. Electrical Specifications ...................................................................................................................72 3.1.1. Absolute Maximum Ratings ...............................................................................................72 3.1.2. Recommended Operating Conditions ................................................................................72 3.2. 92HD92 Analog Performance Characteristics (PRELIMINARY) ......................................................................73 3.3. Class-D BTL Amplifier Performance ................................................................................................76 3.4. Capless Headphone Supply Characteristics ....................................................................................77 3.5. AC Timing Specs .............................................................................................................................77 3.5.1. HD Audio Bus Timing .........................................................................................................77 3.5.2. SPDIF Timing .....................................................................................................................78 3.5.3. Digital Microphone Timing .................................................................................................78 3.5.4. GPIO Characteristics .........................................................................................................78 3.5.5. I2S Interface Timing ...........................................................................................................79 4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 80 5. WIDGET DIAGRAM ................................................................................................................ 81 6. PORT AND PIN CONFIGURATIONS ..................................................................................... 82 6.1. Port Configurations ..........................................................................................................................82 6.2. Pin Configuration Default Register Settings .....................................................................................83 7. WIDGET INFORMATION ........................................................................................................ 84 7.1. Widget List .......................................................................................................................................85 7.2. Reset Key ........................................................................................................................................86 7.3. Root (NID = 00h): VendorID ............................................................................................................86 7.3.1. Root (NID = 00h): RevID ....................................................................................................87 7.3.2. Root (NID = 00h): NodeInfo ...............................................................................................87 7.4. AFG (NID = 01h): NodeInfo .............................................................................................................88 7.4.1. AFG (NID = 01h): FGType .................................................................................................88 7.4.2. AFG (NID = 01h): AFGCap ................................................................................................89 7.4.3. AFG (NID = 01h): PCMCap ...............................................................................................90 7.4.4. AFG (NID = 01h): StreamCap ............................................................................................91 7.4.5. AFG (NID = 01h): InAmpCap .............................................................................................92 7.4.6. AFG (NID = 01h): PwrStateCap .........................................................................................93 7.4.7. AFG (NID = 01h): GPIOCnt ...............................................................................................94 7.4.8. AFG (NID = 01h): OutAmpCap ..........................................................................................94 7.4.9. AFG (NID = 01h): PwrState ...............................................................................................95 7.4.10. AFG (NID = 01h): UnsolResp ..........................................................................................96 7.4.11. AFG (NID = 01h): GPIO ...................................................................................................96 7.4.12. AFG (NID = 01h): GPIOEn ...............................................................................................97 7.4.13. AFG (NID = 01h): GPIODir ..............................................................................................98 7.4.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................99 7.4.15. AFG (NID = 01h): GPIOUnsol ........................................................................................100 7.4.16. AFG (NID = 01h): GPIOSticky .......................................................................................101 7.4.17. AFG (NID = 01h): SubID ................................................................................................101 7.4.18. AFG (NID = 01h): GPIOPlrty ..........................................................................................102 7.4.19. AFG (NID = 01h): GPIODrive .........................................................................................103 7.4.20. AFG (NID = 01h): DMic ..................................................................................................104 7.4.21. AFG (NID = 01h): DACMode .........................................................................................105 7.4.22. AFG (NID = 01h): ADCMode .........................................................................................106 7.4.23. AFG (NID = 01h): PortUse .............................................................................................107 7.4.24. AFG (NID = 01h): ComJack ...........................................................................................108 7.4.25. AFG (NID = 01h): VSPwrState .......................................................................................109 7.4.26. AFG (NID = 01h): AnaPort .............................................................................................110 7.4.27. AFG (NID = 01h): AnaBTL .............................................................................................111 7.4.28. AFG (NID = 01h): AnaBTLStatus ...................................................................................113 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 4 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 7.4.29. AFG (NID = 01h): AnaCapless .......................................................................................113 7.4.30. AFG (NID = 01h): Reset .................................................................................................116 7.4.31. AFG (NID = 01h): DAC3OutAmp (Mono Out Volume) ...................................................117 7.4.32. AFG (NID = 01h): DAC5OutAmpLeft (AuxMode) ...........................................................118 7.4.33. AFG (NID = 01h): DAC5OutAmpRight (AuxMode) ........................................................118 7.4.34. AFG (NID = 01h): ADC4OutAmpLeft (AuxMode) ...........................................................118 7.4.35. AFG (NID = 01h): ADC4OutAmpRight (AuxMode) ........................................................119 7.4.36. AFG (NID = 01h): I2SCtrl ...............................................................................................120 7.4.37. AFG (NID = 01h): EAPD ................................................................................................121 7.5. PortA (NID = 0Ah): WCap ..............................................................................................................123 7.5.1. PortA (NID = 0Ah): PinCap ..............................................................................................124 7.5.2. PortA (NID = 0Ah): ConLst ...............................................................................................125 7.5.3. PortA (NID = 0Ah): ConLstEntry0 ....................................................................................126 7.5.4. PortA (NID = 0Ah): InAmpLeft ..........................................................................................126 7.5.5. PortA (NID = 0Ah): InAmpRight .......................................................................................127 7.5.6. PortA (NID = 0Ah): ConSelectCtrl ....................................................................................127 7.5.7. PortA (NID = 0Ah): PwrState ...........................................................................................128 7.5.8. PortA (NID = 0Ah): PinWCntrl ..........................................................................................128 7.5.9. PortA (NID = 0Ah): UnsolResp ........................................................................................129 7.5.10. PortA (NID = 0Ah): ChSense .........................................................................................130 7.5.11. PortA (NID = 0Ah): EAPDBTLLR ...................................................................................130 7.5.12. PortA (NID = 0Ah): ConfigDefault ..................................................................................131 7.6. PortB (NID = 0Bh): WCap ..............................................................................................................133 7.6.1. PortB (NID = 0Bh): PinCap ..............................................................................................135 7.6.2. PortB (NID = 0Bh): ConLst ...............................................................................................136 7.6.3. PortB (NID = 0Bh): ConLstEntry0 ....................................................................................137 7.6.4. PortB (NID = 0Bh): ConSelectCtrl ....................................................................................137 7.6.5. PortB (NID = 0Bh): PwrState ...........................................................................................137 7.6.6. PortB (NID = 0Bh): PinWCntrl ..........................................................................................138 7.6.7. PortB (NID = 0Bh): UnsolResp ........................................................................................139 7.6.8. PortB (NID = 0Bh): ChSense ...........................................................................................139 7.6.9. PortB (NID = 0Bh): EAPDBTLLR .....................................................................................140 7.6.10. PortB (NID = 0Bh): ConfigDefault ..................................................................................140 7.7. (NID = 0Ch): Vendor Reserved ......................................................................................................143 7.8. PortD (NID = 0Dh): WCap .............................................................................................................144 7.8.1. PortD (NID = 0Dh): PinCap ..............................................................................................145 7.8.2. PortD (NID = 0Dh): ConLst ..............................................................................................146 7.8.3. PortD (NID = 0Dh): ConLstEntry0 ....................................................................................147 7.8.4. PortD (NID = 0Dh): ConSelectCtrl ...................................................................................147 7.8.5. PortD (NID = 0Dh): PwrState ...........................................................................................148 7.8.6. PortD (NID = 0Dh): PinWCntrl .........................................................................................149 7.8.7. PortD (NID = 0Dh): EAPDBTLLR .....................................................................................149 7.8.8. PortD (NID = 0Dh): ConfigDefault ....................................................................................149 7.9. PortE (NID = 0Eh): WCap (I2S Output) .........................................................................................153 7.9.1. PortE (NID = 0Eh): PinCap ..............................................................................................154 7.9.2. PortE (NID = 0Eh): ConLst ...............................................................................................155 7.9.3. PortE (NID = 0Eh): ConLstEntry0 ....................................................................................156 7.9.4. PortE (NID = 0Eh): OutAmpLeft .......................................................................................156 7.9.5. PortE (NID = 0Eh): OutAmpRight ....................................................................................157 7.9.6. PortE (NID = 0Eh): ConSelectCtrl ....................................................................................157 7.9.7. PortE (NID = 0Eh): PwrState ...........................................................................................158 7.9.8. PortE (NID = 0Eh): PinWCntrl ..........................................................................................159 7.9.9. PortE (NID = 0Eh): UnsolResp ........................................................................................159 7.9.10. PortE (NID = 0Eh): ChSense .........................................................................................160 7.9.11. PortE (NID = 0Eh): EAPDBTLLR ...................................................................................160 7.9.12. PortE (NID = 0Eh): ConfigDefault ..................................................................................161 7.10. PortF (NID = 0Fh): WCap (I2S Input) ..........................................................................................164 7.10.1. PortF (NID = 0Fh): PinCap .............................................................................................165 7.10.2. PortF (NID = 0Fh): ConLst .............................................................................................166 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 5 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 7.10.3. PortF (NID = 0Fh): ConLstEntry0 ...................................................................................167 7.10.4. PortF (NID = 0Fh): InAmpLeft ........................................................................................167 7.10.5. PortF (NID = 0Fh): InAmpRight ......................................................................................168 7.10.6. PortF (NID = 0Fh): ConSelectCtrl ..................................................................................168 7.10.7. PortF (NID = 0Fh): PwrState ..........................................................................................169 7.10.8. PortF (NID = 0Fh): PinWCntrl ........................................................................................169 7.10.9. PortF (NID = 0Fh): UnsolResp .......................................................................................170 7.10.10. PortF (NID = 0Fh): ChSense ........................................................................................171 7.10.11. PortF (NID = 0Fh): EAPDBTLLR .................................................................................171 7.10.12. PortF (NID = 0Fh): InVolLeft ........................................................................................172 7.10.13. PortF (NID = 0Fh): InVolRight ......................................................................................172 7.10.14. PortF (NID = 0Fh): ConfigDefault .................................................................................173 7.11. MonoOut (NID = 10h): WCap ......................................................................................................176 7.11.1. MonoOut (NID = 10h): PinCap .......................................................................................177 7.11.2. MonoOut (NID = 10h): ConLst .......................................................................................178 7.11.3. MonoOut (NID = 10h): ConLstEntry0 .............................................................................179 7.11.4. MonoOut (NID = 10h): PwrState ....................................................................................179 7.11.5. MonoOut (NID = 10h): PinWCntrl ..................................................................................180 7.11.6. MonoOut (NID = 10h): ConfigDefault .............................................................................181 7.12. DMic0 (NID = 11h): WCap ...........................................................................................................184 7.12.1. DMic0 (NID = 11h): PinCap ...........................................................................................185 7.12.2. DMic0 (NID = 11h): InAmpLeft .......................................................................................186 7.12.3. DMic0 (NID = 11h): InAmpRight ....................................................................................187 7.12.4. DMic0 (NID = 11h): PwrState .........................................................................................187 7.12.5. DMic0 (NID = 11h): PinWCntrl .......................................................................................188 7.12.6. DMic0 (NID = 11h): UnsolResp ......................................................................................189 7.12.7. DMic0 (NID = 11h): ChSense ........................................................................................189 7.12.8. DMic0 (NID = 11h): ConfigDefault .................................................................................190 7.13. DMic1Vol (NID = 12h): WCap ......................................................................................................193 7.13.1. DMic1Vol (NID = 12h): ConLst .......................................................................................194 7.13.2. DMic1Vol (NID = 12h): ConLstEntry0 ............................................................................195 7.13.3. DMic1Vol (NID = 12h): InAmpLeft ..................................................................................195 7.13.4. DMic1Vol (NID = 12h): InAmpRight ...............................................................................195 7.13.5. DMic1Vol (NID = 12h): PwrState ...................................................................................196 7.14. DAC0 (NID = 13h): WCap ............................................................................................................197 7.14.1. DAC0 (NID = 13h): Cnvtr ...............................................................................................198 7.14.2. DAC0 (NID = 13h): OutAmpLeft .....................................................................................199 7.14.3. DAC0 (NID = 13h): OutAmpRight ..................................................................................200 7.14.4. DAC0 (NID = 13h): PwrState .........................................................................................200 7.14.5. DAC0 (NID = 13h): CnvtrID ............................................................................................201 7.14.6. DAC0 (NID = 13h): EAPDBTLLR ...................................................................................202 7.15. DAC1 (NID = 14h): WCap ............................................................................................................202 7.15.1. DAC1 (NID = 14h): Cnvtr ...............................................................................................204 7.15.2. DAC1 (NID = 14h): OutAmpLeft .....................................................................................205 7.15.3. DAC1 (NID = 14h): OutAmpRight ..................................................................................205 7.15.4. DAC1 (NID = 14h): PwrState .........................................................................................206 7.15.5. DAC1 (NID = 14h): CnvtrID ............................................................................................207 7.15.6. DAC1 (NID = 14h): EAPDBTLLR ...................................................................................207 7.16. ADC0 (NID = 15h): WCap ............................................................................................................208 7.16.1. ADC0 (NID = 15h): ConLst ............................................................................................209 7.16.2. ADC0 (NID = 15h): ConLstEntry0 ..................................................................................210 7.16.3. ADC0 (NID = 15h): Cnvtr ...............................................................................................210 7.16.4. ADC0 (NID = 15h): ProcState ........................................................................................211 7.16.5. ADC0 (NID = 15h): PwrState .........................................................................................212 7.16.6. ADC0 (NID = 15h): CnvtrID ............................................................................................213 7.17. ADC1 (NID = 1Bh): WCap ...........................................................................................................213 7.17.1. ADC1 (NID = 1Bh): ConLst ............................................................................................215 7.17.2. ADC1 (NID = 1Bh): ConLstEntry0 ..................................................................................215 7.17.3. ADC1 (NID = 1Bh): Cnvtr ...............................................................................................216 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 6 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 7.17.4. ADC1 (NID = 1Bh): ProcState ........................................................................................217 7.17.5. ADC1 (NID = 1Bh): PwrState .........................................................................................218 7.17.6. ADC1 (NID = 1Bh): CnvtrID ...........................................................................................219 7.18. ADC0Mux (NID = 17h): WCap .....................................................................................................220 7.18.1. ADC0Mux (NID = 17h): ConLst ......................................................................................221 7.18.2. ADC0Mux (NID = 17h): ConLstEntry4 ...........................................................................222 7.18.3. ADC0Mux (NID = 17h): ConLstEntry0 ...........................................................................222 7.18.4. ADC0Mux (NID = 17h): OutAmpCap .............................................................................223 7.18.5. ADC0Mux (NID = 17h): OutAmpLeft ..............................................................................223 7.18.6. ADC0Mux (NID = 17h): OutAmpRight ...........................................................................224 7.18.7. ADC0Mux (NID = 17h): ConSelectCtrl ...........................................................................224 7.18.8. ADC0Mux (NID = 17h): PwrState ..................................................................................225 7.18.9. ADC0Mux (NID = 17h): EAPDBTLLR ............................................................................226 7.19. ADC1Mux (NID = 18h): WCap .....................................................................................................226 7.19.1. ADC1Mux (NID = 18h): ConLst ......................................................................................228 7.19.2. ADC1Mux (NID = 18h): ConLstEntry4 ...........................................................................228 7.19.3. ADC1Mux (NID = 18h): ConLstEntry0 ...........................................................................229 7.19.4. ADC1Mux (NID = 18h): OutAmpCap .............................................................................229 7.19.5. ADC1Mux (NID = 18h): OutAmpLeft ..............................................................................230 7.19.6. ADC1Mux (NID = 18h): OutAmpRight ...........................................................................230 7.19.7. ADC1Mux (NID = 18h): ConSelectCtrl ...........................................................................231 7.19.8. ADC1Mux (NID = 18h): PwrState ..................................................................................231 7.19.9. ADC1Mux (NID = 18h): EAPDBTLLR ............................................................................232 7.20. MonoMux (NID = 19h): WCap .....................................................................................................233 7.20.1. MonoMux (NID = 19h): ConLst ......................................................................................234 7.20.2. MonoMux (NID = 19h): ConLstEntry0 ............................................................................235 7.20.3. MonoMux (NID = 19h): ConSelectCtrl ...........................................................................235 7.20.4. MonoMux (NID = 19h): PwrState ...................................................................................235 7.21. MonoMix (NID = 1Ah): WCap ......................................................................................................236 7.21.1. MonoMix (NID = 1Ah): ConLst .......................................................................................238 7.21.2. MonoMix (NID = 1Ah): ConLstEntry0 .............................................................................238 7.21.3. MonoMix (NID = 1Ah): PwrState ....................................................................................239 7.22. Mixer (NID = 1Bh): WCap ............................................................................................................241 7.22.1. Mixer (NID = 1Bh): InAmpCap .......................................................................................242 7.22.2. Mixer (NID = 1Bh): ConLst .............................................................................................243 7.22.3. Mixer (NID = 1Bh): ConLstEntry4 ..................................................................................243 7.22.4. Mixer (NID = 1Bh): ConLstEntry0 ..................................................................................244 7.22.5. Mixer (NID = 1Bh): InAmpLeft0 ......................................................................................244 7.22.6. Mixer (NID = 1Bh): InAmpRight0 ...................................................................................245 7.22.7. Mixer (NID = 1Bh): InAmpLeft1 ......................................................................................245 7.22.8. Mixer (NID = 1Bh): InAmpRight1 ...................................................................................246 7.22.9. Mixer (NID = 1Bh): InAmpLeft2 ......................................................................................246 7.22.10. Mixer (NID = 1Bh): InAmpRight2 .................................................................................247 7.22.11. Mixer (NID = 1Bh): InAmpLeft3 ....................................................................................247 7.22.12. Mixer (NID = 1Bh): InAmpRight3 .................................................................................248 7.22.13. Mixer (NID = 1Bh): InAmpLeft4 ....................................................................................248 7.22.14. Mixer (NID = 1Bh): InAmpRight4 .................................................................................249 7.22.15. Mixer (NID = 1Bh): InAmpLeft5 ....................................................................................249 7.22.16. Mixer (NID = 1Bh): InAmpRight5 .................................................................................250 7.22.17. Mixer (NID = 1Bh): PwrState ........................................................................................250 7.23. MixerOutVol (NID = 1Ch): WCap .................................................................................................251 7.23.1. MixerOutVol (NID = 1Ch): ConLst ..................................................................................253 7.23.2. MixerOutVol (NID = 1Ch): ConLstEntry0 .......................................................................253 7.23.3. MixerOutVol (NID = 1Ch): OutAmpCap .........................................................................254 7.23.4. MixerOutVol (NID = 1Ch): OutAmpLeft ..........................................................................255 7.23.5. MixerOutVol (NID = 1Ch): OutAmpRight .......................................................................255 7.23.6. MixerOutVol (NID = 1Ch): PwrState ..............................................................................256 7.24. SPDIFOut0 (NID = 1Dh): WCap ..................................................................................................257 7.24.1. SPDIFOut0 (NID = 1Dh): PCMCap ................................................................................258 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 7 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 7.24.2. SPDIFOut0 (NID = 1Dh): StreamCap ............................................................................260 7.24.3. SPDIFOut0 (NID = 1Dh): OutAmpCap ...........................................................................260 7.24.4. SPDIFOut0 (NID = 1Dh): Cnvtr ......................................................................................261 7.24.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft ...........................................................................262 7.24.6. SPDIFOut0 (NID = 1Dh): OutAmpRight .........................................................................263 7.24.7. SPDIFOut0 (NID = 1Dh): PwrState ................................................................................263 7.24.8. SPDIFOut0 (NID = 1Dh): CnvtrID ..................................................................................264 7.24.9. SPDIFOut0 (NID = 1Dh): DigCnvtr ................................................................................265 7.25. SPDIFOut1 (NID = 1Eh): WCap ..................................................................................................266 7.25.1. SPDIFOut1 (NID = 1Eh): PCMCap ................................................................................267 7.25.2. SPDIFOut1 (NID = 1Eh): StreamCap ............................................................................269 7.25.3. SPDIFOut1 (NID = 1Eh): OutAmpCap ...........................................................................269 7.25.4. SPDIFOut1 (NID = 1Eh): Cnvtr ......................................................................................270 7.25.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft ...........................................................................271 7.25.6. SPDIFOut1 (NID = 1Eh): OutAmpRight .........................................................................272 7.25.7. SPDIFOut1 (NID = 1Eh): PwrState ................................................................................272 7.25.8. SPDIFOut1 (NID = 1Eh): CnvtrID ..................................................................................273 7.25.9. SPDIFOut1 (NID = 1Eh): DigCnvtr .................................................................................274 7.26. Dig0Pin (NID = 1Fh): WCap ........................................................................................................275 7.26.1. Dig0Pin (NID = 1Fh): PinCap .........................................................................................276 7.26.2. Dig0Pin (NID = 1Fh): ConLst .........................................................................................277 7.26.3. Dig0Pin (NID = 1Fh): ConLstEntry0 ...............................................................................278 7.26.4. Dig0Pin (NID = 1Fh): PwrState ......................................................................................278 7.26.5. Dig0Pin (NID = 1Fh): PinWCntrl ....................................................................................279 7.26.6. Dig0Pin (NID = 1Fh): UnsolResp ..................................................................................280 7.26.7. Dig0Pin (NID = 1Fh): ChSense ......................................................................................280 7.26.8. Dig0Pin (NID = 1Fh): ConfigDefault ...............................................................................281 7.27. Dig1Pin (NID = 20h): WCap .........................................................................................................283 7.27.1. Dig1Pin (NID = 20h): PinCap .........................................................................................285 7.27.2. Dig1Pin (NID = 20h): ConLst .........................................................................................286 7.27.3. Dig1Pin (NID = 20h): ConLstEntry0 ...............................................................................287 7.27.4. Dig1Pin (NID = 20h): PwrState ......................................................................................287 7.27.5. Dig1Pin (NID = 20h): PinWCntrl .....................................................................................288 7.27.6. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................289 7.28. DigBeep (NID = 21h): WCap .......................................................................................................292 7.28.1. DigBeep (NID = 21h): OutAmpCap ................................................................................293 7.28.2. DigBeep (NID = 21h): OutAmpLeft ................................................................................293 7.28.3. DigBeep (NID = 21h): PwrState .....................................................................................294 7.28.4. DigBeep (NID = 21h): Gen .............................................................................................295 7.28.5. DigBeep (NID = 21h): Gain ............................................................................................295 7.29. I2C (NID = 22h): WCap ................................................................................................................296 7.29.1. I2C (NID = 22h): Cntrl0 ..................................................................................................297 8. PINOUT AND PACKAGING .................................................................................................. 299 8.0.1. 48QFN Pin Table .............................................................................................................300 8.0.2. 48QFN Package Outline and Package Dimensions ........................................................302 8.1. Standard Reflow Profile Data ........................................................................................................303 9. DISCLAIMER ......................................................................................................................... 304 10. DOCUMENT REVISION HISTORY ..................................................................................... 305 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 8 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO LIST OF TABLES Table 1. Port Functionality .............................................................................................................................12 Table 2. Analog Output Port Behavior ...........................................................................................................13 Table 3. 48pin Jack Detect ............................................................................................................................14 Table 4. SPDIF OUT 0 Behavior ....................................................................................................................15 Table 5. SPDIF OUT 1 Behavior ....................................................................................................................15 Table 6. Power Management .........................................................................................................................18 Table 7. Example channel mapping ...............................................................................................................20 Table 9. EAPD Pin Mode Select ....................................................................................................................23 Table 10. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations ...........23 Table 11. BTL Amp Enable Configuration ......................................................................................................23 Table 12. Headphone Amp Enable Configuration ..........................................................................................23 Table 14. EAPD Analog PC_Beep behavior ..................................................................................................24 Table 15. EAPD Behavior ..............................................................................................................................24 Table 13. Port E Headphone Amp Enable Configuration support by part and mode .....................................24 Table 16. Valid Digital Mic Configurations .....................................................................................................26 Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States ..........................................................26 Table 18. SCLK Frequency Selection ............................................................................................................36 Table 19. MCLK Frequency Selection ...........................................................................................................37 Table 20. I2C Registers .................................................................................................................................49 Table 21. Electrical Specification: Maximum Ratings ...................................................................................72 Table 22. Recommended Operating Conditions ............................................................................................72 Table 23. 92HD92 Analog Performance Characteristics ...............................................................................73 Table 24. Class-D BTL Amplifier Performance ..............................................................................................76 Table 25. Capless Headphone Supply ..........................................................................................................77 Table 26. HD Audio Bus Timing .....................................................................................................................77 Table 27. SPDIF Timing .................................................................................................................................78 Table 28. Digital Mic timing ............................................................................................................................78 Table 29. GPIO Characteristics .....................................................................................................................78 Table 30. I2S Interface Timing .......................................................................................................................79 Table 31. Pin Configuration Default Settings .................................................................................................83 Table 32. Command Format for Verb with 4-bit Identifier ..............................................................................84 Table 33. Command Format for Verb with 12-bit Identifier ............................................................................84 Table 34. Solicited Response Format ............................................................................................................84 Table 35. Unsolicited Response Format ........................................................................................................84 Table 36. Widget List .....................................................................................................................................85 Table 37. Pin Table ......................................................................................................................................300 Table 38. Standard Reflow Profile ...............................................................................................................303 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 9 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO LIST OF FIGURES Figure 1. Multi-channel capture ......................................................................................................................21 Figure 2. Multi-channel timing diagram ..........................................................................................................21 Figure 3. HP EAPD Example to be replaced by single pin for internal amp ..................................................25 Figure 4. EAPD implementation .....................................................................................................................25 Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................27 Figure 6. Stereo Digital Microphone Configuration ........................................................................................28 Figure 7. Quad Digital Microphone Configuration ..........................................................................................29 Figure 8. Analog PC Beep Active ..................................................................................................................30 Figure 9. Analog PC Beep Flow chart ............................................................................................................31 Figure 10. Combo Jack ..................................................................................................................................33 Figure 11. Left Justified Audio Interface (assuming 24-bit word length) ........................................................38 Figure 12. Right Justified Audio Interface (assuming 24-bit word length) ......................................................38 Figure 13. I2S Justified Audio Interface (assuming 24-bit word length) .........................................................38 Figure 14. Switching between Normal and Aux Audio Modes .......................................................................41 Figure 15. Playback Path on Parts Supporting Digital I/O .............................................................................45 Figure 16. Record Path on Parts Supporting Digital I/O ................................................................................46 Figure 17. 2-Wire Serial Control Interface ......................................................................................................47 Figure 18. Multiple Write Cycle ......................................................................................................................48 Figure 19. Read Cycle ...................................................................................................................................48 Figure 20. Multiple Read Cycle ......................................................................................................................49 Figure 21. HD Audio Bus Timing ....................................................................................................................77 Figure 22. Functional Block Diagram .............................................................................................................80 Figure 23. Widget Diagram ............................................................................................................................81 Figure 24. Port Configurations .......................................................................................................................82 Figure 25. ......................................................................................................................................................83 Figure 26. 48QFN Pin Assignment ..............................................................................................................299 Figure 27. 48QFN Package Diagram ...........................................................................................................302 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 10 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 1. DESCRIPTION 1.1. Overview The 92HD92 audio CODEC provides stereo 24- bit, full duplex resolution supporting sample rates up to 192kHz by the DAC and ADC. SPDIF outputs support sample rates of 192kHz, 96kHz, 88.2kHz, 48kHz, and 44.1kHz. Additional sample rates are supported by the driver software. An integrated BTL stereo amplifier is ideal for driving 4ohm or 8ohm integrated speakers in mobile and ultra-mobile computers. For desktop computers or mobile computers using only one speaker, the BTL output stage may be configured to support a single mono speaker. The 92HD92 audio CODEC supports a wide range of desktop and laptop configurations. The 2 independent SPDIF output interfaces provide connectivity to consumer electronic equipment or to a home entertainment system. Simultaneous HDMI and SPDIF output is possible. All inputs can be programmed with 0-30 dB gain in 10 dB steps allowing for line or microphone use of any input. Port presence detect capabilities allow the CODEC to detect when audio devices are connected to the CODEC. The fully parametric Internal EQ can be initiated upon headphone jack insertion and removal for protection of notebook speakers. The 92HD92 audio CODEC operates with a 3.3V digital supply and a 5V (4.75V allowed when using external voltage regulator) analog supply. It allows for 1.5V and 3.3V HDA signaling; the correct signalling level is selected dynamically based on the power supply voltage on the DVDD-IO pin. The 92HD92 audio CODEC is offered in a 48-pin QFN Environmental (ROHS) package. 1.2. Orderable Part Numbers 92HD92B1X5NLGXyyX 92HD92B2X5NLGXyyX Aux mode No Aux mode yy = silicon stepping/revision, contact sales for current data. Add an “8” to the end for tape and reel delivery. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 11 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2. DETAILED DESCRIPTION 2.1. Port Functionality Multi-function (Input/Output) ports allow for the highest possible flexibility and supporting a wide variety of consumer desktop and mobile system use models. • Port A supports • Headphone Out • Line Out • Line Input • Mic with 0/10/20/30 dB Boost Port B supports • Capless Headphone Out • Capless Line Out Port D supports • BTL stereo output • BTL (L+/L-) mono out Port E supports • Headpone Out • Line Out (I2S) Port F supports • Line In (I2S) • Mic with 0/10/20/30 dB boost and Vref_Out Mono Out supports • Line Out Mic Bias (Vref pin) Yes Yes Yes Yes Yes Yes Yes Yes Yes Table 1. Port Functionality Note: Pins 15/16/18 are shared for I2S clocking. Port C is vendor reserved for this device Yes Yes Yes Input boost amp Yes • • • • • Pins 48-QFN 28/29 31/32 40/41/43/44 17 24 25 48 46 4 (CLK=2) Port A B D E F Mono Out SPDIF_OUT0 DMIC1/SPDIFOUT1/ Aux_In DMIC0 Input Yes Output Yes Yes Yes Yes I2S Headphone Yes Yes BTL Yes I2S 2.1.1. Port Characteristics Universal (Bi-directional) jacks are supported on ports A, E, and F for all family members. Ports A and B are designed to drive 32 ohm (nominal) headphones or a 10K (nominal) load. Line Level outputs are intended to drive an external 10K load (nominal) and an on board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 5K ohms and above. Input ports are 50K (nominal) at the pin. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 12 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO DAC full scale outputs and intended full scale input levels are 1V rms at 5V. Line output ports and Headphone output ports on the 92HD92 codec may be configured for +3dBV full scale output levels by using a vendor specific verb. Output ports are always on to prevent pops/clicks associated with charging and discharging output coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as long as AVDD is available. Unused ports should be left unconnected. When updating existing designs to use the codec, ensure that there are no conflicts between the output ports on the codec and existing circuitry. AFG Power State Input Output Used as output Enable Enable for DAC/Mixer Used as output for analog PC_Beep Don't care NA NA Used as input for ADC, mixer Yes Port Behavior Not allowed. Port is active as input. Not allowed. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Active - Port enabled as input Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Active - Port enabled as output 1 1 1 D0-D2 0 0 0 1 1 D3 0 0 0 D3cold D4 D5 - 1 0 0 1 1 0 1 0 1 1 0 - Don't care NA NA No Yes No currently used by DAC, mixer, beep, or is traditional line or headphone output not currently used by DAC, mixer, beep and is capless HP/BTL port NA NA NA NA NA NA NA Inactive (Power Down) NA Don't care Don't care Don't care Don't care Don't care Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Not allowed. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Low power state. If enabled, Beep will output from the port Inactive (Power Down) Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Inactive (lower power) - Port keeps output coupling caps charged if port uses caps. Inactive (lower power) - Port keeps output coupling caps charged if port uses caps. Off - Charge on coupling caps (if used) will not be maintained. currently used by DAC, mixer, beep, or is traditional line or headphone output not currently used by DAC, mixer, beep and is capless HP/BTL port NA NA Table 2. Analog Output Port Behavior IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 13 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.1.2. Vref_Out Port A supports Vref_Out pins for biasing electret cartridge microphones. Settings of 80% AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read. 2.1.3. Jack Detect Plugs inserted to a jack on Ports A, B & SPDIFOUT0 are detected using SENSE_A. Plugs inserted to a jack on Ports E, F, DMIC0, & SPDIFOUT1 are detected using SENSE_B. Per HDA015-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is invalid. When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will generate a Power State Change Request when a change in port connectivity is sensed and then generate an unsolicited response after the HD Audio link has been brought out of a low power state and the device has been enumerated. Per HDA015-B, this will take less than 10mS. The following table summarizes the proper resistor tolerances for different analog supply voltages.. AVdd Nominal Voltage (+/- 5%) Resistor Tolerance Pull-Up Resistor Tolerance SENSE_A/B 4.75V Resistor 39.2K 20.0K 10.0K 5.11K 2.49K 1% SENSE_A PORT A (HP0) PORT B (HP1) NA SPDIFOUT0 Pull-up to AVDD 1% SENSE_B Port E Port F DMIC0 SPDIFOUT1 (DMIC1) Pull-up to AVDD Table 3. 48pin Jack Detect See reference design for more information on Jack Detect implementation. 2.1.4. SPDIF Output Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with all consumer audio gear and allows for convenient integration into home theater systems and media center PCs. The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached to the same stream, the two SPDIF output converters may be misaligned with respect to their frame boundaries. Per the HDA015-B, the SPDIF outputs support the ability to provide clocking information even when no stream is selected for the converter, or when in a low power state. Also, the SPDIF output ports support port presence detect. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 14 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO SPDIF Outputs are outlined in tables below. AFG Power State D0-D3 RESET# Asserted (Low) De-Asserted (High) De-Asserted (High) - Output Enable Converter Dig Enable - Stream ID Keep Alive Enable 0 1 0 1 1 - Pin Behavior Hi-Z (internal pull-down enabled) immediately after power on, otherwise the previous state is retained. Hi-Z (internal pull-down enabled) Active - Pin drives 0 (internal pull-down NA) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Active - Pin drives SPDIFOut0 data (internal pull-down NA) Hi-Z (internal pull-down enabled) Active - Pin drives 0 (internal pull-down NA) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Hi-Z (internal pull-down enabled) Hi-Z (internal pull-down enabled) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Hi-Z (internal pull-down enabled) Hi-Z (port off) Hi-Z (port off) Disabled Enabled Enabled Enabled Disabled Enabled Enabled D0 De-Asserted (High) De-Asserted (High) De-Asserted (High) 0 1-15 - Disabled Enabled - D1-D2 De-Asserted (High) Enabled - D3 De-Asserted (High) Disabled Enabled Enabled - D3cold D4 D5 - - Table 4. SPDIF OUT 0 Behavior AFG Power State D0-D3 RESET# GPIO0 Enable Input Enable Output Enable Converter Stream Dig En ID Keep Alive En - Pin Behavior Hi-Z (internal pull-down enabled) immediately after power on, otherwise the previous state is retained. Active - Pin reflects GPIO0 configuration (internal pull-down enabled) Pin functions as digital mic input (internal pull-down enabled) Asserted (Low) - - - - - D0-D3 D0-D3 De-Asserted (High) De-Asserted (High) Enabled - - - - - Disabled Enabled Disabled - Table 5. SPDIF OUT 1 Behavior IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 15 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO AFG Power State GPIO0 Enable Input Enable Output Enable Converter Stream Dig En ID 0 Enabled 1-15 Disabled Disabled D1-D2 De-Asserted (High) Disabled Disabled Enabled Enabled Disabled D3 De-Asserted (High) Disabled Disabled Disabled Enabled Enabled 1 0 1 0 Keep Alive En RESET# Pin Behavior Hi-Z (internal pull-down enabled) Active - Pin drives 0 (internal pull-down NA) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Active - Pin drives SPDIFOut1 data (internal pull-down NA) Hi-Z (internal pull-down enabled) Active - Pin drives 0 (internal pull-down NA) Active - Pin drives 0 (internal pull-down NA) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Hi-Z (internal pull-down enabled) Hi-Z (internal pull-down enabled) Hi-Z (internal pull-down enabled) Active - Pin drives SPDIF-format, but data is zeroes (internal pull-down NA) Hi-Z (internal pull-down enabled) Hi-Z (port off) Hi-Z (port off) Disabled Disabled Disabled D0 De-Asserted (High) Disabled Enabled D3cold D4 D5 - Disabled Disabled - Table 5. SPDIF OUT 1 Behavior 2.2. Mono Output The Mono Out port source selection, power state, and mute characteristics are all independently controlled by the mono output port controls. EQ does not apply to this path. An internal 2nd order band-pass filter is provided to restrict the output frequencies when using mono out to drive an external amplified sub-woofer. The following sources are available for the Mono Out pin: • • • DAC0 Output: When selected (by using the port connection list), the DAC0 left and right outputs are summed together. DAC1 Output: When selected (by using the port connection list), the DAC1 left and right outputs are summed together. Mixer Output: When selected (by using the port connection list), the mixer left and right outputs are summed together. The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of the two inputs. The full scale output at mono out is designed to be about 0dBV. It is not possible to adjust to a +3dBV output level. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 16 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.3. Mono output Band-Pass Filter For many applications, the primary speakers are incapable of reproducing low frequency audio. Therefore it is desirable to implement a woofer or sub-woofer speaker. The mono output is ideal for this task. However, the frequency response should be restricted to prevent interference with the primary speakers. Typically an external filter, known as a cross-over filter, is used. The mono processing path includes a band-pass filter with programmable high and low cut-off frequencies to eliminate the need for an external filter. 2.3.1. Filter Description The band-pass filter is derived from the common biquadratic filter and provides a 12dB/octave roll-off. The filter may be programmed for a -3dB lower band edge of: 63Hz, 80Hz, 100Hz, 120Hz, 150Hz, 200Hz, 315Hz, or 400Hz. The filter may be programmed for a -3dB upper band edge of: 150Hz, 200Hz, 250Hz, 315Hz, 400Hz, 500Hz, 630Hz, or 800Hz. The band-pass filter is enabled by default with a cut-off frequencies at 120Hz and 250Hz. The filter may be bypassed using the associated verb (processing state verb). The Analog PC_Beep input is not affected by the band-pass filter. 2.4. Mixer The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as independent mutes on each input. The following inputs are available: • • • • Port A Port F DAC 0 DAC 1 2.5. ADC Multiplexers The codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record gain function :(-16 to +30dB gain in 1dB steps) as an output amp and allow a preselection of one of below possible inputs: • • • • • Port A Port F Mixer Output DMIC 0 DMIC 1 2.6. Power Management The HD Audio specification defines power states, power state widgets, and power state verbs. Power management is implemented at several levels. The Audio Function Group (AFG) , all converter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are active in D0 and inactive in D1-D3. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 17 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO The following table describes what functionality is active in each power state. Function SPDIF Outputs Digital Microphone inputs DAC D2S ADC ADC Volume Control Ref ADC Analog Clocks GPIO pins VrefOut Pins Input Boost Analog mixer Mixer Volumes Digital PC_Beep Lo/HP Amps Capless HP Amps BTL Amp VAG amp Port Sense Reference Bias generator Reference Bandgap core HD Audio-Link 1. 2. D0 On On On On On On On On On On On On On On On On On On On On On On D11 On Off Off Off Off Off Off Off On On On On On On On On On On On On On On D2 On (idle) Off Off Off Off Off Off Off On Off Off Off Off On On On On On On On On On D3 On (idle)5 Off Off Off Off Off Off Off On5 Off Off Off Off On5 Low Drive2 Low Drive2 Low Drive2 Low Drive3 On4 On On On5 D3cold Off Off Off Off Off Off Off Off On Off Off Off Off Off Low Drive2 Low Drive2 Off Low Drive Off On On Limited Vendor Specific D4 Off Off Off Off Off Off Off Off On Off Off Off Off Off Low Drive2 Low Drive2 Off Low Drive Off On On Off Vendor SpecificD5 Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Table 6. Power Management No DAC or ADC streams are active. Analog mixing and loop thru are supported. VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be attenuated and distorted depending on load impedance. The codec will shut down the capless headphone amplifiers and BTL amplifier in D3 and below. In D3, the codec will turn on the BTL and Capless amplifiers if activity is detected on the PC_BEEP input and analog PC_Beep is enabled. VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but in a low power state. Both AVDD and DVDD must be available for Port Sense to operate. Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME) 3. 4. 5. The D3-default state is available for HD Audio compliance. The programmable values, exposed via vendor-specific settings, are under IDT Device Driver control for further power reduction. The analog mixer, line and headphone amps, port presence detect, and internal references may be disabled using vendor specific verbs. Use of these vendor specific verbs will cause pops. The default power state for the Audio Function Group after reset is D3. 2.7. AFG D0 The AFG D0 state is the active state for the device. All functions are active if their power state (if they support power management at their node level) has been set to D0. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 18 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.8. AFG D1 D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions are active. The part will resume from theD1 to theD0 state within 1 mS. 2.9. AFG D2 The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers and internal references remain active to keep port coupling caps charged and the system ready for a quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state within 2mS. 2.10. AFG D3 The D3-default state is available for HD Audio compliance. All converters are shut down. Port amplifiers and references are active but in a low power state to prevent pops. Resume times may be longer than those from D2, but still less than 10mS to meet Intel low power goals. The default power state for the Audio Function Group after power is applied is D3. While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3 state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behavior is as follows (see the HDA015-B section for more information): Function HDA Bus active Port Presence Detect state change Unsolicited Response GPIO state change Unsolicited Response HDA Bus stopped Wake Event followed by an unsolicited response Wake Event followed by an unsolicited response 2.10.1. AFG D3cold The D3cold power state is the lowest power state available that does not use vendor specific verbs. While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (double AFG reset, link reset). However, audio processing, port presence detect, and other functions are disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from D3cold is less than 200mS. 2.11. Vendor Specific Function Group Power States D4/D5 The codec introduces vendor specific power states. A vendor defined verb is added to the Audio Function Group that combines multiple vendor specific power control bits into logical power states for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 further reduces power consumption on the digital supply by turning off GPIO drivers, and reduces analog power consumption by turning off all analog circuitry except for reset circuits. States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition of how the part will behave when the D3cold power state is requested or software may enter D3cold, then set the D4 or D5 before performing the power state get command. The preferred method is to request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered when entering D4 or D5. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 19 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Both power states require a link reset or removal of DVDD to exit. The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for example) may take several seconds. 2.12. Low-voltage HDA Signaling The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48-QFN package the voltage selection is done dynamically based on the input voltage of DVDD_IO. DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be used for the HDA bus signals. When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as they always function at their nominal voltage (DVDD or AVDD). 2.13. Multi-channel capture The capability to assign multiple ADC Converters to the same stream is supported to meet the microphone array requirements of Vista and future operating systems. Single converter streams are still supported this is done by assigning unique non zero Stream IDs to each converter. All capture devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restrictions regarding digital microphones. The ADC Converters can be associated with a single stream as long the sample rate and the bits per sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget and is restricted to even values. The ADC converters will always put out a stereo sample and therefore require 2 channels per converter. The stream will not be generated unless all entries for the targeted converters are set identically, and the total number of assigned converter channels matches the value in the NmbrChan field. These are listed the “Multi-Converter Stream Critical Entries.” table. An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying channels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the number of channels must be set to 4 channels “NmbrChan = 0011”. ADC1 CnvtrID ADC0 CnvtrID (NID = 0x08) [3:0] (NID = 0x07) Ch = 2 Ch=0 [3:0] Table 7. Example channel mapping IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 20 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Figure 1. Multi-channel capture ADC0.CnvrtID.Channel = 0 ADC1.CnvrtID.Channel = 2 ADC0.CnvrtID.Channel = 2 ADC1.CnvrtID.Channel = 0 Stream ID Data Length Data Length ADC0 Left Channel ADC1 Left Channel ADC0 Right Channel ADC1 Right Channel ADC1 Left Channel ADC0 Left Channel ADC1 Right Channel ADC0 Right Channel Stream ID The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1. Figure 2. Multi-channel timing diagram BITCLK SDI 0 0 0 1 0 0 1 1 0 0 ADC0 L23 ADC0 L0 ADC0 R23 ADC0 R0 ADC1 L23 ADC1 L0 ADC1 R23 ADC1 R0 STREAM ID STREAM TAG DATA LENGTH LEFT ADC0 RIGHT LEFT ADC1 DATA BLOCK RIGHT ADC[1:0] Cnvtr Bit Number [15] Sub Field Name StrmType Description Stream Type (TYPE): 0: PCM 1: Non-PCM (not supported) Sample Base Rate 0= 48kHz 1=44.1KHz Sample Base Rate Multiple 000=48kHz/44.1kHz or less 001= x2 010= x3 (not supported) 011= x4 192kHz only, 176.4 not supported 100-111= Reserved Sample Base Rate Divisor 000= Divide by 1 001= Divide by 2 (not supported) 010= Divide by 3 (not supported) 011= Divide by 4 (not supported) 100= Divide by 5 (not supported) 101= Divide by 6 (not supported) 110= Divide by 7 (not supported) 111= Divide by 8 (not supported) [14] FrmtSmplRate [13:11] SmplRateMultp [10:8] SmplRateDiv Table 8: Mult-channel IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 21 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO [6:4] BitsPerSmpl Bits per Sample 000= 8 bits (not supported) 001= 16 bits 010= 20 bits 011= 24 bits 100-111= Reserved Number of Channels Number of channels for this stream in each “sample block” of the “packets” in each “frame” on the link. 0000=1 channel (not supported) 0001 = 2 channels … 1111= 16 channels. Software-programmable integer representing link stream ID used by the converter widget. By convention stream 0 is reserved as unused. Integer representing lowest channel used by converter. 0 and 2 are valid Entries If assigned to the same stream, one ADC must be assigned a value of 0 and the other ADC assigned a value of 2. [3:0] NmbrChan [7:4] Strm [3:0] Ch Table 8: Mult-channel 2.14. EAPD The EAPD pin (pin 47) is a dedicated, bi-directional control pin. Although named External Amplifier Power Down (EAPD) by the HD Audio specification, this pin operates as an external amplifier power up signal. The EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power up (equivalent to D0), and a 0 causes it to power down (equivalent to D3.) When the EAPD value = 1, the EAPD pin must be placed in a state appropriate to the current power state of the associated Pin Widget even though the EAPD value (in the register) may remain 1. The default state of this pin is 0 (driving low.) The pin defaults to an open-drain configuration (an external pull-up is recommended.) Per the HD Audio specification and HDA015-B, multiple ports may control EAPD. The EAPD pin assumes the highest power state of all the the EAPD bits in all of the pin complexes. The default value of EAPD is 1 (powered on), but the FG power state will override and the pin will be low. A port will request External Amp Power Up when its power state is active (FG and pin widget power state is D1 or D0) or (Analog PC_Beep is enabled and port is enabled as an output) and the port’s EAPD bit is set to 1. The state of the EAPD pin (unless configured as an input or held low by an external circuit when configured as an open drain output) will be the logical OR of the external amp power up requests from all ports. By default, the EAPD pin also functions as the Mute#/ShutDown# input for the internal BTL amplifier. In this mode, a low value at the pin (either due to internal EAPD being 0, or to an external entity forcing the pin low) will cause the internal BTL amplifier to mute or enter a low power state depending on the amplifier configuration. (See below) Vendor specific verbs are available to configure this pin. These verbs retain their values across link and single function group resets but are set to their default values by a power on reset: IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 22 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO MODE1 0 0 1 1 MODE0 0 1 0 1 EAPD Pin Function Open Drain I/O CMOS Output CMOS Input CMOS Input Description Value at pin is wired-AND of EAPD bit and external signal.(default) Value of EAPD bit in pin widget is forced at pin External signal controls internal amps. EAPD bit in pin widget ignored External signal controls internal amps. EAPD bit in pin widget ignored Table 9. EAPD Pin Mode Select Control Flag EAPD PIN MODE 1:0 BTL/HP SD BTL/HP SD MODE BTL/HP SD INV Description Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain) 0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only 0 = Amp will mute when disabled./ 1 = Amp will shut down (enter a low power state) when disabled (default for YA forward) 0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute) when EAPD pin is high. Table 10. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations BTL SD 0 0 0 0 0 0 0 0 1 1 BTL SD MODE 0 0 0 0 1 1 1 1 0 1 BTL SD INV 0 0 1 1 0 0 1 1 NA NA EAPD Pin State 0 1 0 1 0 1 0 1 NA NA BTL Amp State Amplifier is mute (default1) Amplifier is active Amplifier is active Amplifier is mute Amplifier is in a low power state Amplifier is active Amplifier is active Amplifier is in a low power state Amplifier follows pin/function group power state and will mute when disabled Amplifier follows pin/function group power state and will enter a low power state when disabled Table 11. BTL Amp Enable Configuration 1. HP SD 0 0 0 0 0 0 EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The state after a single or double function group reset will be compliant with HDA015-B. HP SD MODE 0 0 0 0 1 1 HP SD INV 0 0 1 1 0 0 EAPD Pin State 0 1 0 1 0 1 Headphone Amp State Amplifier is mute (default1) Amplifier is active Amplifier is active Amplifier is mute Amplifier is in a low power state Amplifier is active Table 12. Headphone Amp Enable Configuration IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 23 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO HP SD 0 0 1 1 HP SD MODE 1 1 0 1 HP SD INV 1 1 NA NA EAPD Pin State 0 1 NA NA Headphone Amp State Amplifier is active Amplifier is in a low power state Amplifier follows pin/function group power state and will mute when disabled Amplifier follows pin/function group power state and will enter a low power state when disabled 1. Table 12. Headphone Amp Enable Configuration EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The state after a single or double function group reset will be compliant with HDA015-B. Port E Headphone Amp Enable Configuration Bits Normal Mode supported supported supported Aux Mode Not supported1 SD (EAPD Pin or power setting) SD INV SD MODE (power down or mute) 1. Table 13. Port E Headphone Amp Enable Configuration support by part and mode SD is ignored in Aux mode since the widget power state is “D3” or “D3cold”. Analog BEEP enabled 0 1 EAPD Pin value1 Description Forced to low when in D2 or D3 Forced low in D2 or D3 unless port is enabled as output 1. Follows description in HD Audio spec. External amplifier is shut down when pin or function group power state is D2 or D3 independent of value in EAPD bit. Power state is ignored if port is enabled as output and port EAPD=1 to allow PC_Beep support in D2 and D3 Table 14. EAPD Analog PC_Beep behavior When pin is enabled as Open Drain or CMOS output. RESET# Asserted (Low) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) Analog PC_BEEP Disabled Enabled Disabled Enabled Port Power State D0-D1 D0-D2 D0-D2 D0-D3 D0-D3 Table 15. EAPD Behavior Pin Behavior Active low immediately after power on, otherwise the previous state is retained across FG and link reset events Active - Pin reflects EAPD bit unless held low by external source. Active - Pin reflects EAPD bit unless held low by external source. Pin forced low to disable external amp Active - EAPD Pin high if any port EAPD bit =1 and that port also enabled as output. Pin forced low to disable external amp Active - EAPD Pin high if any port EAPD bit=1 and that port also enabled as output. Pin forced low to disable external amp Pin forced low to disable external amp Pin Hi-Z (off) AFG Power State D0-D3 D0 D1 D2 D2 D3 D3 D3cold D4 D5 IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 24 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Figure 3. HP EAPD Example to be replaced by single pin for internal amp HP AUDIO CONTROL BLOCK DIAGRAM SYNC FROM KBC TO OS OS SCAN CODES SYNC FROM AUDIO GUI TO KBC MUTE + UP/DOWN BUTTONS (MUTE LED ON SAME BOARD) KBC A_EAPD GPIO_1 A_SD CODEC SPKR_EN# SPKR AMP Figure 4. EAPD implementation VDD Internal Headphone Amp SD/Mute Internal BTL Amp SD/Mute EAPD SD# External Power Amp EAPD PIN Control SMU MUTE OTHER CODEC 2.15. Digital Microphone Support The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry individual channels of digital microphone data to the ADC. In the event that a single microphone is used, the data is ported to both ADC channels. This mode is selected using a vendor specific verb and the left time slot is copied to the ADC left and right inputs. The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is synchronous to the internal master clock. The default frequency is 2.352Mhz. The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 25 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO analog ports. Although the internal implementation is different between the analog ports and the digital microphones, the functionality is the same. In most cases, the default values for the DMIC clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected. When switching from the digital microphone to an analog input to the ADC, the analog portion of the ADC will be brought back to a full power state and allowed to stabilize before switching from the digital microphone to the analog input. This should take less than 10mS. DMIC pin widgets support port presence detect directly using SENSE-B input. The codec supports the following digital microphone configurations: Digital Mics 0 Data Sample N/A ADC Conn. N/A Notes No Digital Microphones Available on either DMIC_0 or DMIC_1 When using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone for “Left” and select mono operation using the vendor specific verb. “Left” D-mic data is used for ADC left and right channels. Available on either DMIC_0 or DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge (multiplexed output) capability. Requires both DMIC_0 and DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge (multiplexed output) capability. Two ADC units are required to support this configuration Connected to DMIC_0 and DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge capability. Two ADC units are required to support this configuration Table 16. Valid Digital Mic Configurations 1 Single Edge 0, or 1 2 Double Edge on either DMIC_0 or 1 Double Edge on one DMIC pin and Single Edge on the second DMIC pin. 0, or 1 3 0, or 1 4 Double Edge 0, or 1 Power State D0 D1-D3 D0-D3 D4 D5 DMIC Widget Enabled? Yes Yes No - DMIC_CLK Output Clock Capable Clock Disabled Clock Disabled Clock Disabled Clock Disabled DMIC_0,1 Input Capable Input Disabled Input Disabled Input Disabled Input Disabled Notes DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1 Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 26 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Figure 5. Single Digital Microphone (data is ported to both left and right channels Off-Chip Digital Microphone DMIC_0 OR DMIC_1 Pin DMIC_CLK Pin On-Chip Single Line In Stereo Channels Output STEREO ADC0 or 1 PCM On-Chip Multiplexer Single Microphone not supporting multiplexed output. DMIC_0 Or DMIC_1 Valid Data Right Channel Left Channel Valid Data Valid Data MUX DMIC_CLK Single “Left” Microphone, DMIC input set to mono input mode. DMIC_0 Or DMIC_1 Valid Data Valid Data Valid Data Valid Data Left & Right Channel DMIC_CLK IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 27 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Figure 6. Stereo Digital Microphone Configuration Off-Chip External Multiplexer DMIC_0 Or DMIC_1 MUX On-Chip Digital Microphones On-Chip Multiplexer Stereo Channels Output Pin STEREO ADC0 or 1 PCM MUX DMIC_CLK Pin DMIC_0 Or DMIC_1 Valid Data R Valid Data L Valid Data R Valid Data L Valid Data R Right Channel Left Channel DMIC_CLK Note: Some Digital Microphone Implementations support data on either edge, therefore, the external mux may not be required. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 28 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Figure 7. Quad Digital Microphone Configuration Off-Chip Digital Microphones External Multiplexer DMIC_0 MUX On-Chip On-Chip Multiplexer Stereo Channels Output For DMIC_0 L&R Pin STEREO ADC0 PCM MUX DMIC_CLK Pin On-Chip Multiplexer DMIC_1 MUX Pin STEREO ADC1 PCM Stereo Channels Output For DMIC_1 L&R MUX Digital Microphones External Multiplexer DMIC_0 Valid Data R0 Valid Data L0 Valid Data R0 Valid Data L0 Valid Data R0 DMIC_1 Valid Data R1 Valid Data L1 Valid Data R1 Valid Data L1 Valid Data R1 Right Channel Left Right Channel Channel Left Channel DMIC_CLK Note: Some Digital Microphone Implementations support data on either edge, in this case the external multiplexer is not required. 2.16. Analog PC-Beep The codec supports automatic routing of the PC_Beep pin to Port A, Port B, and Port D outputs when the HD-Link is in reset. When the link is active (not held in reset) Analog PC-Beep may be enabled manually. Analog PC_Beep is mixed at the port and only ports enabled as outputs will pass PC_Beep. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 29 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Beep activity monitoring is provided when the analog beep path is enabled and the CODEC or amplifier is in a low power state (D3). The Analog PC Beep input is sampled for 500us every 1ms. If the beep input is high or low (>200mVpp) for at least 37% of that time, it is considered active. If it is active for less than 7.5% of that time, it is possibly inactive. If no activity is detected for 64ms (128ms, 256ms and 512ms also selectable for the idle threshold), then beep is considered inactive. Figure 8. Analog PC Beep Active Phase 1: analog beep auto-routing phase in the period after application of DVDD, before the first rising edge of link reset. Once Analog PCbeep is detected(BEEP_PRESENCE=1) after 64ms delays (after POR (power on reset)), the Amplifier will be turned on(port_pwd=0, port_output_en=1, there is a timing between these two signals) and analog_beep_en=1. If BEEP_PRESENCE=0 for longer than the threshold time, the amplifiers will be turned off to save power and prevent unwanted system noise from being heard. Phase 2: When not in phase 1 A. If analog beep function is disabled by driver. Analog beep auto-detect will also be disabled. B. If analog beep function is enabled by driver. Once analog PCbeep is detected(BEEP_PRESENCE=1), analog pc_beep will be enabled If in D0-D2, enabled simply means muting or un-muting beep to avoid hearing system noise on the beep input pin but it is acceptable to turn off port amplifiers if not currently used by DACs, mixer, or beep to save power. If in D3, enabled means that the necessary amplifiers are turned on so that the beep signal may be heard on all ports configured as outputs (see analog pc-beep description section above) All needed amplifiers are enabled until BEEP_PRESENCE=0 for longer than the idle threshold A flow chart of Analog PC Beep is below. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 30 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO POR Wait 64mS IDLE NO Analog PC_Beep Enabled? NO Link Reset Active? NO NO NO YES YES Activity on Pin? YES Turn on Amplifiers / Enable Beep Path YES Activity on Pin? Activity on Pin? NO NO Inactivity over threshold? YES Disable Beep Path / Turn off Amplifiers Figure 9. Analog PC Beep Flow chart 2.17. Digital PC-Beep This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 31 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio sources are disabled when digital PC_Beep is active. It should be noted that digital PC Beep is disabled if the divider = 00h. PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load impedance seen by the output amplifier since all ports are in a low power state while in D3. Load impedances of 10K or larger can support full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to indicate that the part requires a clock. 2.18. Headphone Drivers The codec implements both traditional and capless headphone outputs. The Microsoft Windows Logo Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Microsoft allows device and system manufactures to limit output voltages to address EU safety requirements. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.) The codec does not support power limiting. Headphone performance will degrade if more than one port is driving a 32 ohm load. 2.19. BTL Amplifier An integrated class-D stereo BTL amplifier is provided to directly drive 4 ohm speakers (2W @ 4.75V) or 8 ohm speakers (1W @ 4.75V). No external filter is needed for cable runs of 18” or less. An internal DC blocking filter prevents distortion when the audio source has DC content, and prevents unintentional power consumption when pausing audio playback. The amplifier may be controlled using the EAPD pin (see EAPD section.) Using a vendor specific verb, the BTL amplifier may be configured to support a mono speaker connected to the L +/- pins. In this mode, the Left and Right audio is mixed and sent to the left output only. The right channel is turned off to conserve power. Maximum gain for the BTL amplifier is programmable. The following 4 gain settings relative to a nominal line output are desired: +6.5dB, +9.5dB, +14.5dB, +16.5dB. Absolute gain may vary and the suggested accuracy is +/-1.5dB. This gain is exposed in a vendor specific widget and is intended to mimic the pin programmable gain implemented in discrete BTL amplifiers commonly used in notebook computers. The BTL amplifier includes thermal management circuitry. When the CODEC reaches a temperature of about 140 degrees, the output amplitude of the BTL amp is gradually lowered until the temperature falls below 140. All other functions will remain active if the BTL amplifier is shut down due to die temperature. 2.20. BTL Amplifier High-Pass Filter For mobile applications, speakers are often incapable of reproducing low frequency audio and unable to handle the maximum output power of the BTL amplifier. A high-pass filter is implemented in the BTL output path to reduce the amount of low frequency energy reaching speakers attached to the BTL amplifier. This can prevent speaker failure. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 32 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.20.1. Filter Description The high-pass filter is derived from the common biquadratic filter and provides a 12dB/octave roll-off. The filter may be programmed for a -3dB response at: 100Hz, 200Hz, 300Hz, 400Hz, 500Hz, 750Hz, 1KHz, or 2KHz. The high pass filter is enabled by default with a cut-off frequency of 300Hz. The filter may be bypassed using the associated verb (processing state verb). The analog PC_Beep input is not affected by the digital high-pass filter. To ensure that the speakers attached to the BTL amplifier are not harmed by low frequency audio entering the PC_Beep input, an external filter must be implemented. Fortunately, it is common practice to implement an attenuation circuit and DC blocking capacitor at the PC_Beep input. This attenuator/filter is easily adjusted to restrict low frequency audio. The easiest approach is to reduce the value of the DC blocking capacitor but other approaches are equally effective. 2.21. EQ There are 5 bands of parametric EQ (bi-quad) per channel. Due to the flexibility of the bi-quad implementation, each filter band may be configured as a high-pass, low-pass, band-pass, high shelving, low shelving, or other function. Each band has an independent set of coefficients. A bi-quad filter has 6 coefficients. One coefficient is normalized to 1 and 5 are programmed into the core. Each band supports up to +15dB boost or up to -36dB cut. 2.22. Combo Jack Detection 4 conductor (combo) jacks are becoming popular. In the most common implementation the 4 conductor plug has the same mechanical dimensions as a 3 conductor 3.5mm plug but the sleeve portion has been split into two segments:S1 and S2. When a 4-conductor plug (headset) is inserted into the jack T (Tip) = Left headphone audio, R (Ring) = Right headphone audio, S1 (First half of sleeve) = microphone input, and S2 (Second half of sleeve) = return (GND). When a 3-conductor plug (headphones) is inserted into the jack; T=Left audio, R=Right audio, S1=GND, S2=GND. By monitoring the S1 connection to see if it is shorted to ground, we can distinguish between headsets and headphones. Please note that analog microphone plugs (3-conductor-Lmic/Rmic/GND) and optical SPDIF plugs can not be supported using this implementation. Figure 10. Combo Jack G N IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. Plug insertion is reported on the headphone port using the switch integrated into the jack. The internal circuit monitors the voltage at the jack to determine if a low impedance load is present. 33 V 1.1 1/12 92HD92 M IC D 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO Detection of a microphone is not reported unless plug insertion is also detected. 2.23. GPIO 2.23.1. GPIO # 0 1 2 3 4 Pin 46 2 4 48 24 GPIO Pin mapping and shared functions Supply DVDD DVDD DVDD DVDD AVDD YES SPDIF In SPDIF Out YES GPI/O YES YES YES YES YES YES GPI GPO VrefOut DMIC IN CLK IN VOL Pull Up Pull Down 50K 50K 50K 50K 50K 2.23.2. SPDIF/Digital Microphone/GPIO Selection 3 functions are available on the DMIC_1/GPIO0/SPDIFOUT1 pin (pin 46). To determine which function is enabled, the order of precedence is followed: 1. If the GPIOs are enabled, they override both SPDIF_OUT and Digital Mics 2. If the GPIOs are not enabled through the AFG, then at reset, the pin is pulled low by an internal pull-down resistor. 3. If the port is enabled as an input, the digital microphones will be used. 4. If the port is enabled as an output, the SPDIF output will be used. 5. In the event that the port is enabled as an input and an output, the port will be an output and the Digital Mic path will be mute. 2.23.3. Digital Microphone/GPIO Selection 2 functions are available on the DMIC_CLK/GPIO1 (pin 2) and the DMIC_0/GPIO2 (pin 4) pins. To determine which function is enabled, the order of precedence is followed: 1. If GPIOs are not enabled through the AFG, then at reset, pins 2 and 4 are pulled low by an internal pull-down resistor. 2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF use) and pin 2 becomes GPIO with an internal pull-down. 3. If GPIO2 is enabled through the AFG, pin 4 becomes a GPIO and is pulled low by an internal pull-down resistor. 4. If the port is enabled as an input, the digital microphones will be used. 5. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone path will be mute. 2.24. HD Audio HDA015-B support The codec provides complete support for the HDA015-B specification (now DCN) building on the support already present in previous products. HDA015-B features supported are: 1. Persistence of many configuration options through bus and function group reset. 2. The ability to support port presence detect in D3 even when the HD Audio bus is in a low power state (no clock.) IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 34 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 3. Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0. 4. Notification if persistent register settings have been unexpectedly reset. 5. SPDIF active in D3 (required) 2.25. Digital Core Voltage Regulator The digital core operates from a 1.8V (10%) supply voltage. Many systems require that the CODEC use a single 3.3V digital supply, so an integrated regulator is included on die. The regulator uses pin 9, DVDD, as its voltage source. The output of the LDO is connected to pin 1 and the digital core. A 10uF capacitor must be placed on pin 1 for proper load regulation and regulator stability. The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V and may precede or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the application of power and the removal of power is neither defined nor guaranteed. It is common for desktop systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely, the condition where AVDD is active but DVDD and DVDDIO are inactive. IDT CONFIDENTIAL ©2009 INTEGRATED DEVICE TECHNOLOGY, INC. 35 V 1.1 1/12 92HD92 92HD92 SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 2.26. Digital Audio Port (I2S) Digital Input and Output capability is provided on Port F and Port E.. 2.26.1. Characteristics I2S output is represented as an output port with a headphone output amplifier. I2S input is represented as an input port. To ensure compatibility with the Microsoft class driver, the port is described as an analog port and provides the same connectivity as a traditional analog port. The I2S ports share common clocks. Therefore only one set of configuration controls are required. 2 stereo analog ports are replaced by the Data Input(I2S_DIN), Data output(I2S_DOUT), data clock(I2S_SCLK), and frame clock (I2S_LRCLK) signals. Due to the requirement that input and output converters provide independent sample rates, sample rate conversion support is provided. Multiple data formats are supported: Left justified, I2S native (Left justified with 1 clock delay), and Right justified modes. Data lengths of 16, 20 and 24 bits are supported. When there is a mismatch between the I2S configuration and the HD Audio link programming (converter widget word length) the word lengths will be aligned using zero padding or truncation as appropriate. The CODEC may be the clock master or a slave to an external master for the shift clock (SCLK) and frame clock (LRCLK) signals. Data shift clock is programmable with a default providing 64 Fs for 44.1KHz based rates and 84Fs for 48KHz based rates. A 64Fs shift clock is also available for 48KHz rates but the jitter performance will be much worse than 84Fs. By default, the shift clock will automatically adjust for sample rate. However, the shift clock may also be programmed to provide a constant output independent of the selected sample rate. SCLK[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Frequency (MHz) Auto 12.288 6.144 3.072 11.2896 5.6448 2.8224 PLL clock divisor Auto 147/16 147/8 147/4 10 20 40 suggested sample rate1 All 192KHz 96KHz 48KHz 88.2KHz 88.2KHz 44.1KHz clocks/fr ame 64 64 64 64 128 64 64 Notes SCLK is always 64Fs (48KHz based rates have jitter) High jitter (