952601YFLFT

DATASHEET Programmable Timing Control HubTM for Next Gen P4TM Processor Recommended Application: CK409 clock, Intel Yellow Cover part Output Features: • 3 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 7 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 4 - 3V66, 66.66MHz • 1 - VCH/3V66, selectable 48MHz or 66MHz Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps • +/- 300ppm frequency accuracy on CPU & SRC clocks ICS952601 Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA. • Supports spread spectrum modulation, 0 to -0.5% down spread. • • • Supports CPU clks up to 400MHz in test mode. Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning. Supports undriven differential CPU, SRC pair in PD# and CPU_STOP# for power management. Pin Configuration Functionality CPU B6b5 FS_A FS_B MHz 0 0 100 0 MID Ref/N0 0 1 200 0 1 0 133 1 1 166 1 MID Hi-Z 0 0 200 0 1 400 1 1 0 266 1 1 333 SRC MHz 100/200 Ref/N1 100/200 100/200 100/200 Hi-Z 100/200 100/200 100/200 100/200 3V66 MHz 66.66 Ref/N2 66.66 66.66 66.66 Hi-Z 66.66 66.66 66.66 66.66 PCI MHz 33.33 Ref/N3 33.33 33.33 33.33 Hi-Z 33.33 33.33 33.33 33.33 REF USB/DOT MHz MHz 14.318 48.00 Ref/N4 Ref/N5 14.318 48.00 14.318 48.00 14.318 48.00 Hi-Z Hi-Z 14.318 48.00 14.318 48.00 14.318 48.00 14.318 48.00 REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PD# 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_B VDDA GNDA GND IREF FS_A CPU_STOP# PCI_STOP# VDDCPU CPUCLKT2 CPUCLKC2 GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD Vtt_PWRGD# VDD48 GND 48MHz_DOT 48MHz_USB SDATA 3V66_4/VCH 56-pin SSOP & TSSOP IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor ICS952601 701J—01/25/10 1 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PIN TYPE OUT OUT PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT DESCRIPTION 14.318 MHz reference clock. 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nomina 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of SMBus circuitry, 5V tolerant. 21 PD# IN 22 23 24 25 26 27 28 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK OUT OUT PWR PWR OUT OUT IN IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 2 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description (continued) PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PIN NAME 3V66_4/VCH SDATA 48MHz_USB 48MHz_DOT GND VDD48 Vtt_PWRGD# VDD SRCCLKC SRCCLKT GND CPUCLKC0 CPUCLKT0 VDDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC2 CPUCLKT2 VDDCPU PCI_STOP# CPU_STOP# FS_A IREF GND GNDA VDDA FS_B PIN TYPE OUT I/O OUT OUT PWR PWR IN PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR IN IN IN OUT PWR PWR PWR IN DESCRIPTION 66.66MHz clock output for AGP support. AGP-PCI should be aligned with a skew window tolerance of 500ps. VCH is 48MHz clock output for video controller hub. Data pin for SMBus circuitry, 5V tolerant. 48MHz clock output. 48MHz clock output. Ground pin. Power pin for the 48MHz output.3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply for SRC clocks, nominal 3.3V Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic 0 level, when input low. PCI and SRC clocks can be set to Free_Running through I2C. Internal pull-up of 150K nominal. Stops all CPUCLK besides the free running clocks. Internal pull-up of 150K nominal Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. Ground pin for core. 3.3V power for the PLL core. Frequency select pin, see Frequency table for functionality IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 3 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor General Description ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. Block Diagram PLL2 Frequency Dividers 48MHz, USB, DOT, VCH X1 X2 XTAL REF (1:0) CPUCLKT (2:0) CPUCLKC (2:0) SRCCLKT0 SCLK SDATA CPU_STOP# PCI_STOP# Vtt_PWRGD# PD# FS_A FS_B Programmable Spread PLL1 Control Logic Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(4:0) PCICLK (6:0) PCICLKF (2:0) I REF Power Groups Pin Number VDD GND 3 6 24 25 10,16 11,17 36 39 55 54 34 33 N/A 53 48, 42 45 Description Xtal, Ref 3V66 [0:3] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL, SCLK, SDATA IREF CPUCLK clocks IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 4 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Absolute Maximum Ratings Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage VDD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase1 Case Temperature 1 115 °C Tcase2 Case Temperature 2 94 °C ESD prot Input ESD protection human body model 2000 V 1. This case temperature limits the junction temperature to