9DB633AGLFT

DATASHEET Six Output Differential Buffer for PCIe Gen3 Recommended Application: 6 output PCIe Gen3 zero-delay/fanout buffer General Description: The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications. Key Specifications: • Cycle-to-cycle jitter < 50 ps • Output-to-output skew < 50 ps • PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram 9 DB633 Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled Output Features: • 6 - 0.7V current mode differential HCSL output pairs OE1# OE4# DIF1 SRC_IN SRC_IN# SPREAD COMPATIBLE PLL DIF4 PLL_BW SMBDAT SMBCLK CONTROL LOGIC DIF(0,2,3,5) IREF IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 1 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Pin Configuration PLL_BW SRC _IN SRC_IN# vOE1# D IF_0 DIF_0# VDD GND D IF_1 DIF_1# D IF_2 DIF_2# VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF vOE4# DIF_5 DIF_5# VDD GND DIF_4 DIF_4# DIF_3 DIF_3# VDD SMBCLK Note:Pins preceeded by ' v ' have internal 120K ohm pull down resistors Power Distribution Table Pin Number VDD GND 7, 13, 16, 22 8,21 13 8 N/A 27 28 27 Description Differential Outputs SMBus IREF Analog VDD & GND for PLL core IDT® Six Output Differential Buffer for PCIe Gen3 9DB633 1668C—04/20/11 2 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN NAME PLL_BW SRC_IN SRC_IN# vOE1# DIF_0 DIF_0# VDD GND DIF_1 DIF_1# DIF_2 DIF_2# VDD SMBDAT SMBCLK VDD DIF_3# DIF_3 DIF_4# DIF_4 GND VDD DIF_5# DIF_5 vOE4# PIN TYPE IN IN IN IN OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs This pin establishes the reference for the differential current-mode output pairs. It r equires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different v alues. See d ata sheet. Ground pin for the PLL core. 3.3V power for the PLL core. 26 27 28 IREF GNDA VDDA OUT PWR PWR Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 3 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet CONDITIONS UNITS NOTES V V V V V ° Electrical Characteristics - Absolute Maximum Ratings PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage Storage Temperature Junction Temperature Input ESD protection 1 SYMBOL VDDA VDD VIL VIH VIHSMB Ts Tj ESD prot MIN TYP MAX 4.6 4.6 VDD+0.5V 5.5V GND-0.5 Except for SMBus interface SMBus clock and data pins -65 Human Body Model 2000 150 125 C ° C V 1,2 1,2 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Ambient Operating Temperature Input High Voltage Input Low Voltage TCOM TIND VIH VIL IIN Input Current I INP Fibyp Fipll Lpin CIN CINDIF_IN COUT Clk Stabilization Input SS Modulation Frequency OE# Latency Tdrive_PD# Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency 1 2 CONDITIONS MIN 0 -40 2 GND - 0.3 -5 -200 10 33 1.5 1.5 TYP MAX 70 85 V DD + 0.3 0.8 5 200 110 110 7 5 2.7 6 1.8 UNITS NOTES ° C ° C V V uA uA MHz MHz nH pF pF pF ms 1 1 1 1 1 1 2 2 1 1 1,4 1 1,2 Commmercial range Industrial range Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = V DD Single-ended inputs VIN = 0 V ; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode Logic Inputs, except DIF_IN DIF_IN differential clock inputs Output pin capacitance From VDD P ower-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs Input Frequency Pin Inductance Capacitance 100.00 TSTAB f MODIN t LATOE# t DRVPD tF tR V ILSMB V IHSMB V OLSMB I PULLUP V DDSMB t RSMB t FSMB f MAXSMB 30 33 kHz 1 1 3 300 5 5 0.8 cycles us ns ns V V V mA V ns ns kHz 1,3 1,3 1,2 1,2 1 1 1 1 1 1 1 1,5 2.1 @ I PULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Maximum SMBus operating frequency 4 2.7 VDDSMB 0.4 5.5 1000 300 100 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 5 The differential input clock must be running for the SMBus to be active IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 4 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - Clock Input Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage - DIF_IN Input Low Voltage - DIF_IN Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 SYMBOL VIHDIF VILDIF VCOM VSWING dv/dt I IN dtin J DIFIn CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage Peak to Peak value Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement MIN 600 VSS - 300 300 300 0.4 -5 45 0 TYP 800 0 MAX 1150 300 1000 1450 8 5 55 125 UNITS NOTES mV mV mV mV V/ns uA % ps 1 1 1 1 1,2 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% CONDITIONS MIN TYP MAX UNITS NOTES V/ns 1, 2, 3 Scope averaging on 0.6 2.5 4 % Slew rate matching, Scope averaging on 9.5 20 1, 2, 4 Statistical measurement on single-ended signal Voltage High VHigh 660 740 850 1 using oscilloscope math function. (Scope averaging mV Voltage Low VLow -150 8 150 1 on) Measurement on single ended signal using absolute Max Voltage Vmax 760 1150 1 mV value. (Scope averaging off) Min Voltage Vmin -300 -3 1 Vswing Vswing Scope averaging off 300 1506 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 378 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 54 140 mV 1, 6 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 (100Ω differential impedance). Slew rate Slew rate matching Trf ∆Trf 2 3 PARAMETER SYMBOL Measured from differential waveform Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 4 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Operating Supply Current Powerdown Current 1 CONDITIONS MIN TYP 134 MAX 150 N/A N/A UNITS NOTES mA mA mA 1 1 1 I DD3.3OP I DD3.3PD I DD3.3PDZ All outputs active @100MHz, CL = Full load; All diff pairs driven All differential pairs tri-stated Guaranteed by design and characterization, not 100% tested in production. IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 5 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER PLL Bandwidth PLL Jitter Peaking Duty Cycle Duty Cycle Distortion Skew, Input to Output Skew, Output to Output Jitter, Cycle to cycle 1 SYMBOL BW t JPEAK t DC t DCD t pdBYP t pdPLL t sk3 tjcyc-cyc CONDITIONS -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode Measured differentially, Bypass Mode @100MHz Bypass Mode, VT = 50% Hi BW PLL Mode V T = 50% VT = 50% PLL mode Additive J itter in Bypass Mode MIN 2 0.4 45 -2 2500 -250 TYP 2.3 0.5 1 48 1 3660 0 15 40 10 MAX 4 1 2 55 2 4500 250 50 50 50 UNITS NOTES MHz MHz dB % % ps ps ps ps ps 1 1 1 1 1,4 1 1 1 1,3 1,3 2 Guaranteed by design and characterization, not 100% tested in production. I REF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = 0.7V @ ZO=50 . 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. Electrical Characteristics - PCIe Phase Jitter Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL t jphPCIeG1 t jphPCIeG2 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) MIN TYP 32 1.1 2.3 0.5 2 0.2 0.8 0.1 MAX 86 3 3.1 1 5 0.3 1 0.2 UNITS Notes ps (p-p) 1,2,3 ps 1,2 (rms) ps 1,2 (rms) ps 1,2,4 (rms) ps (p-p) ps (rms) ps (rms) ps (rms) 1,2,3 1,2 1,2 1,2,4 Phase Jitter, PLL Mode t jphPCIeG3 t jphPCIeG1 Additive Phase Jitter, Bypass Mode t jphPCIeG2 t jphPCIeG3 1 2 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 6 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max Unit inch inch inch ohm ohm Figure 1 1 1 1 1 inch inch 1 1 inch inch 2 2 Figure 1: Down Device Routing L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt PCI Express Down Device REF_CLK Input L3' L3 Figure 2: PCI Express Connector Routing L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt PCI Express Add-in Board REF_CLK Input L3' L3 IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 7 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 R1a L2 R3 L4 L4' R4 L1' R1b HCSL Output Buffer L2' R2a R2b Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a Cc L4 L4' Cc R6a R5b R6b PCIe Device REF_CLK Input IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 8 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet General SMBus serial interface information for the 9DB633 How to Write: • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controlle r (Host) starT bit T S lave Address D4(H ) WR W Rite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r) Index Block Read Operation Controlle r (Host) T starT bit S lave Address D4(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 9 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet SMB usTable: Device Control Register, READ /WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Control Function Type 0 PLL controlled Enables SMBus SW_EN RW by SMBus Bit 7 Control of bits (1:0) r egisters RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 Selects PLL Bit 1 PLL BW #adjust RW Low BW Bandwidth PLL bypassed Bypasses PLL for RW PLL Enable Bit 0 board test (fan out mode) SMB usTable: Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Enable Register Pin # Name Control Function Type RW RESERVED RW RESERVED PCIEX5 Output Control RW 24,23 RW RESERVED PCIEX3 Output Control RW 18,17 PCIEX2 Output Control RW 11,12 RW RESERVED 5,6 PCIEX0 Output Control RW 1 PLL controlled by device pins Default 1 X X X X X High BW PLL enabled ( ZDB mode) 1 1 0 Disable Disable Disable Disable 1 Enable Enable Enable Enable Default X X 1 X 1 1 X 1 SMB usTable: Function Select Register Pin # Name Control Function Type Byte 2 RESERVED Bit 7 RW RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RW RESERVED Bit 0 RW SMB usTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID Bit 1 VID1 R VID0 R Bit 0 0 - 1 Default X X X X X X X X 0 - 1 - Default 0 0 0 1 0 0 0 1 IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 10 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet SMBusTable: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R = 06 Hex R R R R 0 - 1 Default 0 0 0 0 0 1 1 0 SMBusTable: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 1 1 0 IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 11 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet 28-pin SSOP Package Drawing and Dimensions 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N α VARIATIONS N 28 D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 12 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet 28-pin TSSOP Package Drawing and Dimensions c 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) L N (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 SYMBOL A A1 A2 b c D E E1 e L N α aaa VARIATIONS N E1 INDEX AREA E 12 a D In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 A2 A1 A D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 28 -CReference Doc.: JEDEC Publication 95, MO-153 e b SEATING PLANE 10-0035 aaa C Ordering Information Part / Order Number 9DB633AFLF 9DB633AFLFT 9DB633AFILF 9DB633AFLIFT 9DB633AGLF 9DB633AGLFT 9DB633AGILF 9DB633AGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "A" is the device revision designator (will not correlate to the datasheet revision). IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11 13 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Revision History Rev. A B C O riginator RDW RDW RDW Issue Date 6/30/2010 7/12/2010 4/20/2011 Description Released to final Changed "PWD" to "Default" in SMBus Register descriptions Changed pull down indicator from '**' to 'v'. P age # 10,11 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. A ccelerated T hinking is a service mark of Integrated Device Technology, Inc. A ll other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 14