9DS400AGLF

Advance Information Four Output Differential Buffer for PCIe Gen 2 with Spread General Description The 9DS400 is pin compatible to the 9DB403, but adds the ability to inject spread spectrum onto the incoming differential clock, while maintaining good phase noise. ICS9DS400 Features/Benefits • • Bypass mode Supports undriven differential outputs in PD# and SRC_STOP# modes for power management. Recommended Application DB400 where spread spectrum needs to be added to the incoming clock. Output Features • • • • • 4 - 0.7V current-mode differential output pairs. Supports Spread Injection mode and fanout mode. Two pin selectable down spread amounts: 0.5% and 0.25%. 50-110 MHz operation in PLL mode 50-400 MHz operation in Bypass mode Key Specifications • • • • Output cycle-cycle jitter < 50ps Output to Output skew 200 mV 4 SRC_IN input 5 The differential input clock must be running for the SMBus to be active IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 5 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Electrical Characteristics - Differential Clock Input Parameters TA =Over the Specified Operating Range; VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 MIN 600 VSS - 300 300 300 0.4 -5 45 0 TYP 800 0 MAX 1150 300 1000 1450 8 5 55 125 UNITS NOTES mV mV mV mV V/ns uA % ps 1 1 1 1 1,2 1 1 1 VIHDIF VILDIF VCOM VSWING dv/dt I IN dtin J DIFIn Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage Peak to Peak value Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing min centered around differential zero IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 6 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA =Over the Specified Operating Range; VDD = 3.3 V +/-5%; CL = 2pF, RS=33 , RP=49.9 , RREF=475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, Input to Output Skew, Output to Output Jitter, Cycle to cycle SYMBOL Zo1 VHigh VLow Statistical measurement on single ended signal using oscilloscope math function. CONDITIONS MIN 3000 660 -150 -300 250 175 175 550 140 700 700 125 125 55 4500 250 50 50 50 10 0.1 0.5 86 3 3.1 850 mV 150 1150 mV mV mV ps ps ps ps % ps ps ps ps ps ps (pk2pk) ps (rms) ps (rms) ps (pk2pk) ps (rms) ps (rms) 1,2 1 1 1 1 1 1 1 1 1 1 1 1 1,3 1,3 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 TYP MAX UNITS NOTES 1 1,2 Jitter, Phase Measurement on single ended signal Vovs using absolute value. Vuds Vcross(ab s) d-Vcross Variation of crossing over all edges VOL = 0.175V, VOH = 0.525V tr tf VOH = 0.525V VOL = 0.175V d-tr d-tf dt3 Measurement from differential wavefrom t pdBYP Bypass Mode, VT = 50% PLL Mode VT = 50%, Spread Off t pdPLL t sk3 VT = 50% PLL mode tjcyc-cyc Additive J itter in Bypass Mode PCIe Gen1 phase jitter (Additive in Bypass Mode) PCIe Gen 2 Low Band phase jitter t jphaseBYP (Additive in Bypass Mode) PCIe Gen 2 High Band phase jitter (Additive in Bypass Mode) PCIe Gen 1 phase jitter t jphasePLL PCIe Gen 2 Low Band phase jitter PCIe Gen 2 High Band phase jitter 45 2500 -250 1 2 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50 . 3 Measured from differential waveform 4 See http://www.pcisig.com for complete specs 5 Device driven by 932S421C or equivalent. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 7 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 7.41425 5.91440 4.91450 3.66463 2.91470 2.41475 1us -SSC Short-term A verage Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s -ppm error Long-Term Average Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s 0ppm Period Nominal 10.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 0.1s 1us + ppm error +SSC Long-Term Short-term Average Average Maximum 10.00100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 Maximum 10.05130 7.53845 6.03076 5.02563 3.76922 3.01538 2.51282 1 Clock Lg+ Period Maximum 10.17630 7.62345 6.11576 5.11063 3.85422 3.10038 2.59782 Units ns ns ns ns ns ns ns Notes 1,2,3 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 Definition DIF 100 DIF 133 DIF 166 DIF 200 DIF 266 DIF 333 DIF 400 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 7.41425 5.91440 4.91450 3.66463 2.91470 2.41475 1us -SSC Short-term A verage Minimum Absolute Period 0.1s -ppm error Long-Term Average Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s 0ppm Period Nominal 10.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 0.1s 1us + ppm error +SSC Long-Term Short-term Average Average Maximum 10.00100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 Maximum 1 Clock Lg+ Period Maximum 10.17630 7.62345 6.11576 5.11063 3.85422 3.10038 2.59782 Units ns ns ns ns ns ns ns Notes 1,2,3 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 Signal Name 1 2 3 4 Definition DIF 100 DIF 133 DIF 166 DIF 200 DIF 266 DIF 333 DIF 400 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK409/CK410B/CK505 accuracy requirements. The 9DS400/800 itself does not contribute to ppm error. Driven by SRC output of main clock, PLL or Bypass mode Driven by CPU output of CK410B/CK505 main clock, Bypass mode only IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread Signal Name 1626 09/17/09 8 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Unit inch inch inch ohm ohm Figure 1 1 1 1 1 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 1 1 inch inch 2 2 Figure 1: Down Device Routing L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt PCI Express Down Device REF_CLK Input L3' L3 Figure 2: PCI Express Connector Routing L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt PCI Express Add-in Board REF_CLK Input L3' L3 IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 9 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 R1a L2 R3 L4 L4' R4 L1' R1b HCSL Output Buffer L2' R2a R2b Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a Cc L4 L4' Cc R6a R5b R6b PCIe Device REF_CLK Input IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 10 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information General SMBus serial interface information for the ICS9DS400 How to Write: • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D8 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D8 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D9 (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D8(h) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D8(h) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D9(h) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread Not acknowledge stoP bit 1626 09/17/09 11 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Type RW RW RW RW 0 driven driven 1 Hi-Z Hi-Z Default 0 0 0 Latch 1 SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (D8/D9) Byte 0 Pin # Name Control Function PD_Mode PD# drive mode Bit 7 STOP_Mode SRC_Stop# drive mode Bit 6 Reserved Bit 5 Bit 4 Bit 3 1 SPREAD_AMT(1) SPREAD_AMT(0) Spread % MSB Spread % LSB 00 = -0.125% 01 = -0.25% 10 = -0.375% 11 = -0.50% 28 SPREAD_EN Turns on spread RW SS Off SS On Latch Bit 2 22 BYPASS# BYPASS#_SSCG RW fan-out SSCG Latch Bit 1 Byte0 CONTROL Selects control source of Byte 0 RW Smbus Input Pins 1 Bit 0 Notes: Pins 1, 22 and 28 are latched into Byte 0 on the first power up of the device. Bits [4:1] will NOT reflect changes in these pin states after power up, even though the pins are controlling the function of the part. Setting Byte 0 bit 0 to 0 allows the SMBus to write Bits [4:1] and transfers control of the functions from the pins to SMBus. Once Byte 0 bit 0 is set to 0, the pins no longer impact Byte 0, bits [4:1] or the device function. SMBus Table: Output Control Register Byte 1 Pin # Name Control Function Type 0 1 Reserved Reserved RW Reserved Bit 7 22,23 DIF_6 Output Enable RW Disable Enable Bit 6 19,20 DIF_5 Output Enable RW Disable Enable Bit 5 Reserved Reserved RW Reserved Bit 4 Reserved Reserved RW Reserved Bit 3 9,10 DIF_2 Output Enable RW Disable Enable Bit 2 6,7 DIF_1 Output Enable RW Disable Enable Bit 1 Reserved Reserved RW Reserved Bit 0 NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run! SMBus Table: OE Pin Control Register Byte 2 Pin # Name Reserved Bit 7 22,23 DIF_6 Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 6,7 DIF_1 Bit 1 Reserved Bit 0 SMBus Table: Reserved Register Byte 3 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 1 1 1 1 1 1 1 Control Function Reserved DIF_6 Stoppable with OE6 Reserved Reserved Reserved Reserved DIF_1 Stoppable with OE1 Reserved Type RW RW RW RW RW RW RW RW Default Reserved 0 Free-run Stoppable 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Free-run Stoppable 0 Reserved 0 0 1 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default X X X X X X X X 1626 09/17/09 IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 12 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 5 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function REVISION ID VENDOR ID Type R R R R R R R R 0 - 1 - Default 0 0 0 0 0 0 0 1 Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Type R R R R R R R R 0 1 Device ID is 80 Hex for 9DS800 and 40 Hex for 9DS400 Default X X 0 0 0 0 0 0 Control Function Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 0 0 0 0 1 1 1 Writing to this register configures how many bytes will be read back. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 13 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion. Tstable 200 mV) within 10 ns of de-assertion. DIF_STOP_1 (DIF_Stop = Driven, PD = Driven) 1mS SRC_Stop# DIF PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) DIF_STOP_2 (DIF_Stop =Tristate, PD = Driven) 1mS SRC_Stop# DIF PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 15 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information DIF_STOP_3 (DIF_Stop = Driven, PD = Tristate) 1mS DIF SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) DIF_STOP_4 (DIF_Stop = Tristate, PD = Tristate) 1mS SRC_Stop# DIF PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 16 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information 28-pin SSOP Package Dimensions 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N α VARIATIONS N 28 D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° Reference Doc.: JEDEC Publication 95, MO-150 209 mil SSOP 10-0033 IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 17 ICS9DS400 Four Output Differential Buffer for PCIe for Gen 2 with Spread Advance Information 28-pin TSSOP Package Dimensions N c 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) L (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 SYMBOL A A1 A2 b c D E E1 e L N α aaa VARIATIONS N 28 E1 INDEX AREA E 12 a D A2 A1 A In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 -Ce b SEATING PLANE D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 aaa C Reference Doc.: JEDEC Publication 95, MO-153 10-0035 9DS400 Ordering Information Part / Order Number 9DS400AGLF 9DS400AGLFT 9DS400AGILF 9DS400AGILFT 9DS400AFLF 9DS400AFLFT 9DS400AFILF 9DS400AFILFT Marking 9DS400AGLF 9DS400AGLF 9DS400AGILF 9DS400AGILF 9DS400AFLF 9DS400AFLF 9DS400AFILF 9DS400AFILF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP Ambient Operating Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread 1626 09/17/09 18 ICS9DS400 Four Output Differential Buffer for PCIe Gen 2 with Spread Advance Information Revision History Rev. 0.1 0.2 Issue Date Description 9/16/2009 Initial release. 9/17/2009 Updated IDD specs in Input/Supply/Common Output Parameters table Page # 5 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 19