9FG430AFLFT

DATASHEET Four Output Differential Frequency Generator for PCIe Gen3 and QPI General Description: The 9FG430 is a Frequency Timing Generator that provides 4 HCSL differential output pairs. These outputs support PCI-Express Gen3, and QPI applications. The part supports Spread Spectrum and synthesizes several additional output frequencies from either a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock. The 9FG430 also outputs a copy of the reference clock. Complete control of the device is available via strapping pins or via the SMBus inteface. 9 FG430 Features/Benefits: • • • • • Pin-to-Pin with 9FG104D/Easy upgrade to PCIe Gen3 Generates common frequencies from 14.318 MHz or 25 MHz; single part supports mulitple applications Provides copy of reference output; eleminates need for additional crystal or oscillator Unused outputs may be disabled in Hi-Z; save system power Device may be configured by SMBus and/or strap pins; can be used in systems without SMBus Recommended Application: 4 Output Differential Frequency Generator for PCIe Gen3 and QPI • • • • • Key Specifications: Cycle-to-cycle jitter: < 50ps with 25MHz input Output-to-output skew: 200 mV 4 DIF_IN input 5 The differential input clock must be running for the SMBus to be active IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 4 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions. PARAMETER Slew rate Slew rate matching Voltage High Voltage Low Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) 1 SYMBOL Trf ∆Trf VHigh VLow Vmax Vmin Vswing Vcross_abs ∆-Vcross CONDITIONS Scope averaging on Slew rate matching, Scope averaging on Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MIN 1 660 -150 -300 300 250 TYP MAX UNITS NOTES 4 20 850 mV 150 1150 mV mV mV mV 1 1 1 1, 2 1, 5 1, 6 V/ns % 1, 2, 3 1, 2, 4 1 550 140 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 IOH = 6 x I REF and VOH = 0.7V @ ZO=50 (100 differential impedance). 2 3 (1%), IREF = 2.32mA. Measured from differential waveform Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 4 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. 6 Electrical Characteristics - Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading PARAMETER SYMBOL IDD3.3 Operating Supply Current IDDA3.3OP IDD3.3 IDDA3.3OP IDD3.3PD IDDA3.3PD IDD3.3PDZ IDDA3.3PDZ CONDITIONS VDD, All outputs active @100MHz VDDA, All outputs active @100MHz VDD, All outputs active @400MHz VDDA, All outputs active @400MHz VDD, All differential pairs driven VDDA, All differential pairs driven VDD, All differential pairs tri-stated VDDA, All differential pairs tri-stated MIN TYP 80 25 100 25 75 25 25 25 MAX 95 30 120 30 90 30 30 30 UNITS NOTES mA mA mA mA mA mA mA mA 1 1 1 1 1 1 1 1 Powerdown Current 1 2 Guaranteed by design and characterization, not 100% tested in production. I REF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. IOH = 6 x I REF and VOH = 0.7V @ ZO=50 . Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading PARAMETER Duty Cycle Skew, Output to Output Jitter, Cycle to cycle Jitter, Cycle to cycle 1 2 SYMBOL t DC t sk3 t jcyc-cyc t jcyc-cyc CONDITIONS Measured differentially, PLL Mode VT = 50% 25M input 14.318M input MIN 45 TYP MAX 55 50 50 60 UNITS NOTES % ps ps ps 1 1 1,3 1,3 Guaranteed by design and characterization, not 100% tested in production. I REF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. IOH = 6 x I REF and VOH = 0.7V @ ZO=50 . 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 5 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Electrical Characteristics - Phase Jitter Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions PARAMETER SYMBOL t jphPCIeG1 t jphPCIeG2 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) MIN TYP MAX 86 3 3.1 1 0.5 0.3 0.2 UNITS Notes ps (p-p) 1,2,3,6 ps 1,2,6 (rms) ps 1,2,6 (rms) ps 1,2,4,5, (rms) 6 ps 1,5,6 (rms) ps 1,5,6 (rms) ps 1,5,6 (rms) Phase Jitter, PCI Express t jphPCIeG3 Phase Jitter, QPI/SMI t jphQPI_SMI Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3 6 Applies to all differential outputs 2 1 Electrical Characteristics - REF-14.318/25 MHz TA = TCOM or TIND; Supply Voltage VDD = 3.3 V PARAMETER SYMBOL Long Accuracy ppm Clock period Tperiod Clock period Tperiod Output High Voltage Output Low Voltage Output High Current Output Low Current Rise/Fall Time Duty Cycle Jitter 1 2 +/-5%, See Test Loads for loading CONDITIONS see Tperiod min-max values 14.318MHz output nominal 25.000MHz output nominal I OH = -1 mA MIN TYP 0 69.8413 40 MAX UNITS ppm ns ns V V mA mA ns % ps Notes 1 1,2 1,2 1 1 1 1 1 1 1 V OH VOL I OH I OL t rf1 dt1 tjcyc-cyc 2.4 -29 29 0.5 45 250 0.4 -23 27 2 55 400 I OL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V V OL = 0.4 V, VOH = 2.4 V VT = 1.5 V VT = 1.5 V 0.8 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818 or 25.00 MHz IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 6 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Output Termination and Layout Information Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max Figure 1: Down Device Routing (Test Load) L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt Unit inch inch inch ohm ohm Figure 1 1 1 1 1 inch inch 1 1 inch inch 2 2 PCI Express Down Device REF_CLK Input L3' L3 Figure 2: PCI Express Connector Routing L1 Rs L2 L4 L4' L1' Rs HCSL Output Buffer L2' Rt Rt PCI Express Add-in Board REF_CLK Input L3' L3 IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 7 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 R1a L2 R3 L4 L4' R4 L1' R1b HCSL Output Buffer L2' R2a R2b Down Device REF_CLK Input L3' L3 Termination for Cable AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a Cc L4 L4' Cc R6a R5b R6b PCIe Device REF_CLK Input Figure 5. REF Output Test Load Zo = 50 ohms 33 5pF 9FGxxx REF Output IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 8 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Differential Clock Tolerances x1 = 25MHz Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF or SSC +/- Synthesis 0.25% Error Center (ppm) Spread 0 0 0 10 0 6 10 0 1 Clock Center Freq. MHz 1us Measurement Window 0.1s 0.1s 0.1s 1us 1 Clock +SSC + ppm +c2c Units ShortLong-Term jitter Term Average AbsPer Average Max Max Max 10.00000 10.05000 ns 8.00000 8.05000 ns 7.50000 7.55000 ns 6.00006 6.05006 ns 5.00000 5.05000 ns 3.75002 3.80002 ns 3.00003 3.05003 ns 2.50000 2.55000 ns -SSC - ppm -c2c jitter 0 ppm Short-Term Long-Term Period AbsPer Average Average Nominal Min Min Min 9.95000 7.95000 7.45000 5.94994 4.95000 3.69998 2.94997 2.45000 10.00000 8.00000 7.50000 5.99994 5.00000 3.74998 2.99997 2.50000 10.00000 8.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 Notes DIF 100.00 125.00 133.33 166.67 200.00 266.67 333.33 400.00 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Clock Periods - Differential Outputs with Spread Spectrum Enabled SSC ON -0.5% Down Spread 1 Clock Synthesis Error (ppm) Center Freq. MHz 1us Measurement Window 0.1s 0.1s 0.1s 1us +SSC + ppm ShortLong-Term Term Average Average Max Max 10.02603 10.05103 8.02020 8.04020 7.51952 7.53827 6.01510 6.03010 5.01301 5.02551 3.75903 3.76841 3.00755 3.01505 2.50651 2.51276 1 Clock +c2c jitter AbsPer Max 10.10103 8.09020 7.58827 6.08010 5.07551 3.81841 3.06505 2.56276 Units Notes -SSC - ppm 0 ppm -c2c jitter Short-Term Long-Term Period AbsPer Average Average Nominal Min Min Min 9.94906 7.94925 7.44930 5.94943 4.94953 3.69965 2.94972 2.44977 9.99906 7.99925 7.49930 5.99943 4.99953 3.74965 2.99972 2.49977 10.02406 8.01925 7.51805 6.01443 5.01203 3.75902 3.00722 2.50602 10.02506 8.02005 7.51880 6.01504 5.01253 3.75940 3.00752 2.50627 DIF 96 19 96 10 96 -98 10 96 99.75 124.69 133.00 166.25 199.50 266.00 332.50 399.00 ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 2 Guaranteed by design and characterization, not 100% tested in production. A ll ppm specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL frequency. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 9 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Differential Clock Tolerances, x1 = 14.31818MHz Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF or SSC +/- Synthesis 0.25% Error Center (ppm) Spread 35 -114 35 -104 35 42 -104 35 1 Clock Center Freq. MHz 1us Measurement Window 0.1s 0.1s 0.1s 1us 1 Clock +SSC + ppm +c2c Units ShortLong-Term jitter Term Average AbsPer Average Max Max Max 10.00035 10.05035 ns 7.99909 8.04909 ns 7.50026 7.55026 ns 5.99937 6.04937 ns 5.00018 5.05018 ns 3.75016 3.80016 ns 2.99969 3.04969 ns 2.50009 2.55009 ns -SSC - ppm 0 ppm -c2c jitter Short-Term Long-Term Period AbsPer Average Average Nominal Min Min Min 9.94965 7.95091 7.44974 5.95062 4.94983 3.69984 2.95031 2.44991 9.99965 8.00091 7.49974 6.00062 4.99983 3.74984 3.00031 2.49991 10.00000 8.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 Notes DIF 100.00 125.00 133.33 166.67 200.00 266.67 333.33 400.00 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Clock Periods - Differential Outputs with Spread Spectrum Enabled SSC ON -0.5% Down Spread 1 Clock Synthesis Error (ppm) Center Freq. MHz 1us Measurement Window 0.1s 0.1s 0.1s 1us +SSC + ppm ShortLong-Term Term Average Average Max Max 10.02706 10.05206 8.01925 8.03925 7.52029 7.53904 6.01510 6.03010 5.01353 5.02603 3.75887 3.76825 3.00755 3.01505 2.50676 2.51301 1 Clock +c2c Units jitter AbsPer Max 10.10206 8.08925 7.58904 6.08010 5.07603 3.81825 3.06505 2.56301 ns ns ns ns ns ns ns ns Notes -SSC - ppm -c2c jitter 0 ppm Short-Term Long-Term Period AbsPer Average Average Nominal Min Min Min 9.94906 7.94925 7.44930 5.94943 4.94953 3.69965 2.94972 2.44977 9.99906 7.99925 7.49930 5.99943 4.99953 3.74965 2.99972 2.49977 10.02406 8.01925 7.51805 6.01443 5.01203 3.75902 3.00722 2.50602 10.02506 8.02005 7.51880 6.01504 5.01253 3.75940 3.00752 2.50627 DIF 199 -100 199 10 199 -140 10 199 99.75 124.69 133.00 166.25 199.50 266.00 332.50 399.00 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 2 Guaranteed by design and characterization, not 100% tested in production. All ppm specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL frequency. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 10 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI General SMBus serial interface information for the 9FG430 How to Write: • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address DC (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address DC (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controlle r (Host) starT bit T S lave Address DC(H ) WR W Rite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte IDT (Sla ve /Re ce ive r) Index Block Read Operation Controlle r (Host) T starT bit S lave Address DC(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte IDT (Sla ve /Re ce ive r) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 11 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 6 24 25 16 Name FS31 FS21 FS11 FS01 Spread Enable1 Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) DIF_STOP# drive mode SPREAD TYPE Control Function Type RW RW RW RW RW RW RW RW 0 1 Default Pin 17 Pin 6 Pin 24 Pin 25 Pin 16 0 0 0 See Frequency Selection Table, Page 1 Off On Hardware Select Software Select Driven Down Hi-Z Center Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 EN DIF_0 EN DIF_3 EN DIF_2 EN Name Control Function Reserved Output Enable Output Enable Reserved Reserved Output Enable Output Enable Reserved RW RW Disable Disable Enable Enable RW RW Disable Disable Enable Enable Type 0 1 Default 1 1 1 1 1 1 1 1 SMBus Table: Output Stop Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 STOP EN DIF_0 STOP EN DIF_3 STOP EN DIF_2 STOP EN Name Control Function Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved RW RW Free-run Free-run Stop-able Stop-able RW RW Free-run Free-run Stop-able Stop-able Type 0 1 Default 0 0 0 0 0 0 0 0 IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 12 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Frequency Select Readback Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 6 44 45 16 Name SEL14M_25M# (FS3) FS21 FS1 1 1 Control Function State of pin 17 State of pin 6 State of pin 24 State of pin 25 State of pin 26 Reserved Reserved Reserved Type R R R R R 0 1 Default Pin 17 See Frequency Selection Table, Page 1 Pin 6 Pin 24 Pin 25 FS01 SPREAD1 Off On Pin 16 0 0 0 Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 VENDOR ID REVISION ID Control Function Type R R R R R R R R 0 1 Default 0 0 0 0 0 0 0 1 SMBus Table: DEVICE ID Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 Device ID = 43 hex Control Function Type R R R R R R R R 0 1 Default 0 1 0 0 0 0 1 1 SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Control Function Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 1 1 1 1681C—08/26/10 IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 13 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Reserved Register Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 SMBus Table: Reserved Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 SMBus Table: M/N Programming Enable Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 5 REFOUT_En Name M/N_Enable Control Function M/N Prog. Enable Reserved REFOUT Enable Reserved Reserved Reserved Reserved Reserved RW Disable Enable Type RW 0 Disable 1 Enable Default 0 1 1 0 0 0 0 0 SMBus Table: PLL Frequency Control Register Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div8 PLL N Div9 PLL M Div5 PLL M Div4 PLL M Div3 PLL M Div2 PLL M Div1 PLL M Div0 M Divider Programming bit (5:0) Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X The decimal representation of M and N Divider in Byte 10 and 11 will c onfigure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2]. The user does NOT need to program these resgisters for standard frequencies. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 14 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: PLL Frequency Control Register Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div7 PLL N Div6 PLL N Div5 PLL N Div4 PLL N Div3 PLL N Div2 PLL N Div1 PLL N Div0 N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Control Function Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X The decimal representation of M and N Divider in Byte 10 and 11 will c onfigure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2]. The user does NOT need to program these resgisters for standard frequencies. SMBus Table: PLL Spread Spectrum Control Register Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL SSP7 PLL SSP6 PLL SSP5 PLL SSP4 PLL SSP3 PLL SSP2 PLL SSP1 PLL SSP0 Spread Spectrum Programming bit(7:0) Control Function Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X These Spread Spectrum bits in Byte 12 and 13 will program the spread pecentage of PLL. The user does not need to modify these settings unless nonstandard spread amounts are required. The part defaults to 0.5% spread when spread is enabled. SMBus Table: PLL Spread Spectrum Control Register Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PLL SSP14 PLL SSP13 PLL SSP12 PLL SSP11 PLL SSP10 PLL SSP9 PLL SSP8 Spread Spectrum Programming bit(14:8) Name Control Function Reserved RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 12 and 13 will program the spread pecentage of PLL. The user does not need to modify these settings unless nonstandard spread amounts are required. The part defaults to 0.5% spread when spread is enabled. Type 0 1 Default 0 X X X X X X X IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 15 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI 28-Pin SSOP Package Drawing and Dimensions c N 209 mil SSOP SYMBOL L E1 INDEX AREA E 12 h x 45° D α A A1 A2 b c D E E1 e L N α VARIATIONS N In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 A 28 A1 Reference Doc.: JEDEC Publication 95, MO-150 -Ce b SEATING PLANE .10 (.004) C 10-0033 IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 16 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI 28-Pin TSSOP Package Drawing and Dimensions 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) SYMBOL L N c (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 E1 INDEX AREA E 12 α D A A1 A2 b c D E E1 e L N α aaa VARIATIONS In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 A2 A1 A N 28 D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 - Ce b SEA TING PLANE Reference Doc.: JEDEC Publication 95, MO-153 10-0035 aaa C Ordering Information Part / Order Number 9FG430AFLF 9FG430AFLFT 9FG430AFILF 9FG430AFILFT 9FG430AGLF 9FG430AGLFT 9FG430AGILF 9FG430AGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant. “ A” is the device revision designator (w ill not correlate w ith the datasheet revision). IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681C—08/26/10 17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Revision History Rev. 0.1 A B Issue Date Who Description Page # 7/13/2010 RDW New datasheet. 7/13/2010 RDW Release 1. Added PPM tables to DS for both 25M and 14.318M inputs 7/20/2010 RDW 2. Added Test load figures 1. Updated/reformatted Electrical Tables 2. Corrected Features/Benefits and General Description 3. Updated pull up ^ and pull down v indicators. 4. Updated termination figures to include Fig. 5 for REF output, merged test 1, Various 8/25/2010 RDW load figures into these figures. C Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. A ccelerated T hinking is a service mark of Integrated Device Technology, Inc. A ll other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 18