9UMS9610CKLFT

DATASHEET PC MAIN CLOCK Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) - CK610 ICS9UMS9610 Features/Benefits: • • • • • • Supports Dothan ULV CPUs with 100 to 200 MHz CPU outputs Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins CPU STOP# input for power manangment Fully integrated Vreg Integrated series resistors on differential outputs 1.5V VDD IO, 1.5V VDD core, 3.3V VDD supply pin for REF Output Features: • • • • • 3 - CPU low power differential push-pull pairss 3 - SRC low power differential push-pull pairs 1 - LCD100 SSCD low power differential push-pull pair 1 - DOT96 low power differential push-pull pair 1 - REF, 14.31818MHz, 3.3V SE output Pin Configuration VDDCORE_1.5 CPUC0_LPR CPUC1_LPR CPUC2_LPR CPUT0_LPR CPUT1_LPR CPUT2_LPR VDDIO_1.5 VDDIO_1.5 FSB_L_1.5 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO_1.5 VDDCORE_1.5 *CR#0_1.5 *CR#2_1.5 SRCT2_LPR SRCC2_LPR GNDSRC SRCT1_LPR SRCC1_LPR VDDIO_1.5 VDDCORE_1.5 *CR#1_1.5 SRCT0_LPR SRCC0_LPR GNDSRC GNDCPU 48 47 46 45 44 43 42 41 40 39 38 37 CPU_STOP#_3.3 CLKPWRGD#/PD_3.3 X2 X1 VDDREF_3.3 REF_3.3_2x GNDREF VDDCORE_1.5 FSC_L_1.5 TEST_MODE_1.5 TEST_SEL_1.5 SCLK_3.3 1 2 3 4 5 6 7 8 9 10 11 12 VDDCORE_1.5 SDATA_3.3 VDDIO_1.5 9UMS9610 13 14 15 16 17 18 19 20 21 22 23 24 DOT96C_LPR GNDLCD LCD100C_LPR DOT96T_LPR LCD100T_LPR GNDDOT 48-pin MLF, 6x6 mm, 0.4mm pitch * indicates inputs with internal pull up of ~10Kohm to 1.5V IDTTM/ICSTM PC MAIN CLOCK GNDCPU 1336—06/01/09 1 ICS9UMS9610 PC MAIN CLOCK Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 PIN NAME CPU_STOP#_3.3 CLKPWRGD#/PD_3.3 X2 X1 VDDREF_3.3 REF_3.3_2x GNDREF VDDCORE_1.5 FSC_L_1.5 TEST_MODE_1.5 TYPE IN IN OUT IN PWR OUT GND PWR IN IN DESCRIPTION This active-low input stops all CPU clocks that are set to be stoppable. This level sensitive strobe determines when latch inputs are valid and are ready to be sampled. When high, this asynchronous input places the device into the power down state. Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Power pin for the XTAL and REF clocks, nominal 3.3V 3.3V 14.318 MHz reference clock. Default 2 load drive strength Ground pin for the REF outputs. 1.5V power for the PLL core Low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Max input voltage is 1.5V. TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V 1 = All outputs are tri-stated for test 0 = All outputs behave normally. Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. 1.5V power for the PLL core Power supply for low power differential outputs, nominal 1.5V. Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor to GND needed. No Rs needed. Ground pin for DOT clock output Ground pin for LCD clock output Complement clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to GND needed. No Rs needed. Power supply for low power differential outputs, nominal 1.5V. 1.5V power for the PLL core 1.5V Clock request for SRC0, 0 = enable, 1 = disable Logic Level (V) 3.3 3.3 N/A 1.5 3.3 3.3 0 1.5 1.5 1.5 Input Level Tolerance (V) 3.3 3.3 N/A 1.5 3.3 N/A N/A 1.5 1.5 3.3 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TEST_SEL_1.5 SCLK_3.3 SDATA_3.3 VDDCORE_1.5 VDDIO_1.5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.5 VDDCORE_1.5 *CR#0_1.5 IN IN I/O PWR PWR OUT OUT GND GND OUT OUT PWR PWR IN 1.5 3.3 3.3 1.5 1.5 0.8 0.8 0 0 0.8 0.8 1.5 1.5 1.5 3.3 3.3 3.3 1.5 1.5 N/A N/A N/A N/A N/A N/A 1.5 1.5 1.5 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 2 ICS9UMS9610 PC MAIN CLOCK Pin Description (continued) PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME GNDSRC SRCC0_LPR SRCT0_LPR *CR#1_1.5 VDDCORE_1.5 VDDIO_1.5 SRCC1_LPR SRCT1_LPR GNDSRC SRCC2_LPR SRCT2_LPR *CR#2_1.5 FSB_L_1.5 CPUC2_LPR CPUT2_LPR GNDCPU VDDIO_1.5 VDDCORE_1.5 CPUC1_LPR CPUT1_LPR GNDCPU VDDIO_1.5 CPUC0_LPR CPUT0_LPR TYPE DESCRIPTION GND Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. IN 1.5V Clock request for SRC1, 0 = enable, 1 = disable PWR 1.5V power for the PLL core PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of differential 0.8V push-pull SRC output with OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. GND Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. IN 1.5V Clock request for SRC2, 0 = enable, 1 = disable Low threshold input for CPU frequency selection. Refer to input electrical IN characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage. Complementary clock of differential pair 0.8V push-pull CPU outputs with OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. GND Ground pin for the CPU outputs PWR Power supply for low power differential outputs, nominal 1.5V. PWR 1.5V power for the PLL core Complementary clock of differential pair 0.8V push-pull CPU outputs with OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. GND Ground pin for the CPU outputs PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of differential pair 0.8V push-pull CPU outputs with OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. Logic Level (V) 0 0.8 0.8 1.5 1.5 1.5 0.8 0.8 0 0.8 0.8 1.5 1.5 0.8 0.8 0 1.5 1.5 0.8 0.8 0 1.5 0.8 0.8 Input Level Tolerance (V) N/A N/A N/A 1.5 1.5 1.5 N/A N/A N/A N/A N/A 1.5 1.5 N/A N/A N/A 1.5 1.5 N/A N/A N/A 1.5 N/A N/A IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 3 ICS9UMS9610 PC MAIN CLOCK Funtional Block Diagram X1 X2 REF OSC SRC(2:0) CPU, SRC SS-PLL CPU(2:0) LCD SS-PLL LCD100_SSC 96M Non-SS PLL DOT96MHz FSLC FSLB CKPWRGD/PD# CPU_STOP# CR(2:0)# TESTSEL TESTMODE SMBDAT SMBCLK Control Logic Power Groups Pin Number Description VDD GND 41, 46 Low power outputs 40, 45 CPUCLK 42 VDDCORE_1.5V 30 Low power outputs 25, 33 SRCCLK 29 VDDCORE_1.5V 22 Low power outputs 19 LCDCLK 23 VDDCORE_1.5V 15 Low power outputs 18 DOT 96Mhz 14 VDDCORE_1.5V Xtal, REF 5 7 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 4 ICS9UMS9610 PC MAIN CLOCK Absolute Maximum Ratings PARAMETER 3.3V Supply Voltage 1.5V Supply Voltage 3.3_Input High Voltage 1.5_Input High Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx_3.3 VDDxxx_1.5 VIH3.3 VIH1.5 VIL Ts ESD prot CONDITIONS Supply Voltage Supply Voltage 3.3V Inputs 1.5V Inputs Any Input Human Body Model GND - 0.5 -65 2000 150 MIN MAX 3.9 2.1 VDD_3.3+ 0.3V VDD_1.5+ 0.3V UNITS Notes V V V V V ° 1,2 1,2 1,2,3 1,2,3 1 1,2 1,2 C V Notes: 1 2 3 Guaranteed by design and characterization, not 100% tested in production. O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Ambient Operating Temp 3.3V Supply Voltage 1.5V Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage 1.5V Input High Voltage 1.5V Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage Low Threshold InputLow Voltage SYMBOL Tambient VDDxxx_3.3 VDDxxx_1.5 VIHSE3.3 VILSE3.3 VIHSE1.5 VILSE1.5 IIN IINRES VOHSE VOLSE VIH_FS VIL_FS IDD_3.3 IDD_DEFAULT1.5 Operating Supply Current IDD_LCDEN1.5 IDD_IO1.5 IDD_PD3.3 Power Down Current IDD_PD1.5CORE IDD_PD1.5IO Input Frequency Pin Inductance Input Capacitance Spread Spectrum Modulation Frequency Fi Lpin CIN COUT CINX fSSMOD Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation 3 30 1.5 CONDITIONS No Airflow 3.3V +/- 5% 1.5V +/- 5% Single-ended inputs Single-ended inputs Single-ended inputs Single-ended inputs VIN = VDD , VIN = G ND Inputs with pull or pull down resistors VIN = VDD , VIN = G ND Single-ended output, IOH = -1mA Single-ended output, IOL = 1 mA 1.5 V +/-5% 1.5 V +/-5% 3.3V supply 1.5V core supply, LCDPLL off 1.5V core supply, LCDPLL enabled 1.5V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 1.5V CORE supply, Power Down Mode 1.5V IO supply, Power Down Mode VDD = 3.3 V 0.7 VSS - 0.3 MIN 0 3.135 1.425 2 VSS - 0.3 1.2 VSS - 0.3 -5 -200 2.4 0.4 1.5 0.35 10 45 55 15 0.5 0.5 0.1 15 7 5 6 5 33 MAX 85 3.465 1.575 VDDxx_3.3 + 0.3 0.8 VDDxxx_1.5 + 0.3 0.3 5 200 UNITS Notes °C V V V V V V uA uA V V V V mA mA mA mA mA mA mA MHz nH pF pF pF kHz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 5 ICS9UMS9610 PC MAIN CLOCK AC Electrical Characteristics - Input/Common Parameters PARAMETER Clk Stabilization Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB TDRPD TDRSRC TFALL TRISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD# and CPU_STOP# inputs MIN MAX 1.8 300 2 6 5 5 UNITS Notes ms us Cycles ns ns 1 1 1 1 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Rise/Fall Time Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle LCD Jitter - Cycle to Cycle CPU[2:0] Skew SRC[2:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C LCDJ C2C CPUSKEW10 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 85 100 250 MIN 0.6 0.6 MAX 4 4 125 1150 UNITS NOTES V/ns V/ns ps mV mV mV mV mV % ps ps ps ps ps ps 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = - 1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS Notes ppm ns ns V V mA mA V/ns V/ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 6 ICS9UMS9610 PC MAIN CLOCK Electrical Characteristics - SMBus Interface PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 3.6 0.4 UNITS Notes V V mA ns ns kHz 1 1 1 1 1 1 Notes on Electrical Characteristics: 1 2 3 4 5 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# O nly applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6 7 8 9 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol 1 Clock LgAbsolute Period Definition Minimum Absolute Period 9.87400 9.91400 7.41425 1us -SSC 0.1s -ppm error 0.1s 0ppm Period 0.1s + ppm error Long-Term Average 1us +SSC Short-term Average 1 Clock Lg+ Period Short-term Long-Term Average Average Minimum Absolute Period 9.99900 9.99900 7.49925 Minimum Absolute Period 9.99900 9.99900 7.49925 Nominal 10.00000 10.00000 7.50000 Maximum 10.00100 10.00100 7.50075 Maximum 10.05130 10.05130 7.53845 Maximum 10.17630 10.13630 7.62345 Units ns ns ns Notes 1,2 1,2 1,2 Signal Name SRC 100 CPU 100 CPU 133 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol 1 Clock LgAbsolute Period Definition Minimum Absolute Period 9.87400 9.91400 7.41425 1us -SSC 0.1s -ppm error 0.1s 0ppm Period 0.1s + ppm error Long-Term Average 1us +SSC Short-term Average 1 Clock Lg+ Period Short-term Long-Term Average Average Minimum Absolute Period Minimum Absolute Period 9.99900 9.99900 7.49925 Nominal 10.00000 10.00000 7.50000 Maximum 10.00100 10.00100 7.50075 10.41770 Maximum Maximum 10.17630 10.13630 7.62345 10.66770 Units ns ns ns ns Notes 1,2 1,2 1,2 1,2 SRC 100 Signal Name CPU 100 CPU 133 1 2 10.16560 10.41560 10.41670 DOT 96 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 7 ICS9UMS9610 PC MAIN CLOCK Table 1: CPU Frequency Select Table CPU SRC DOT 1 1 FS LC FS LB MHz MHz MHz 0 0 133.33 0 1 166.67 100.00 96.00 1 0 100.00 1 1 200.00 LCD100 MHz REF MHz 100.00 14.318 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Table 2: LCD Spread Select Table (Pin 20/21) B1b5 0 0 0 0 1 1 1 1 B1b4 0 0 1 1 0 0 1 1 B1b3 0 1 0 1 0 1 0 1 Spread Comment % -0.5% LCD100 -1% LCD100 -2% LCD100 -2.5% LCD100 +/- 0.25% LCD100 +/-0.5% LCD100 +/-1% LCD100 +/-1.25% LCD100 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 8 ICS9UMS9610 PC MAIN CLOCK General I2C serial interface information for the ICS9UMS9610 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit Slave Address D2(H) WR WRite T Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 9 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) 7 6 5 4 3 2 1 0 0 PLL & Divider Enable Register Pin # Name Descri ption Type This bit controls whether the PLL driving the PLL1 Enable RW CPU and SRC clocks is enabled or not. This bit controls whether the PLL driving the PLL2 Enable RW DOT and clock is enabled or not. This bit controls whether the PLL driving the PLL3 Enable RW LCD clock is enabled or not. Reserved This bit controls whether the CPU output CPU Divider divider is enabled or not. RW Enable NOTE: This bit should be automatically set to ‘0’ if bit 7 is set to ‘0’. This bit controls whether the SRC output SRC Output divider is enabled or not. RW Divider Enable NOTE: This bit should be automatically set to ‘0’ if bit 7 is set to ‘0’. This bit controls whether the LCD output divider is enabled or not. LCD Output RW Divider Enable NOTE: This bit should be automatically set to ‘0’ if bit 5 is set to ‘0’. This bit controls whether the DOT output DOT Output divider is enabled or not. RW Divider Enable NOTE: This bit should be automatically set to ‘0’ if bit 6 is set to ‘0’. 1 PLL SS Enable/Control Register Pin # Name Descri ption This bit controls whether PLL1 has spread enabled or not. Spread spectrum for PLL1 is PLL1 SS Enable set at -0.5% down-spread. Note that PLL1 drives the CPU and SRC clocks. This bit controls whether PLL3 has spread enabled or not. Note that PLL3 drives the SSC PLL3 SS Enable clock, and that the spread spectrum amount is set in bits 3-5. These 3 bits select the frequency of PLL3 and PLL3 FS Select the SSC clock when Byte 1 Bit 6 (PLL3 Spread Spectrum Enable) is set. Reserved Reserved Reserved 0 0 = Disabled 0 = Disabled 0 = Disabled 1 1 = Enabled 1 = Enabled 1 = Enabled Default 1 1 1 0 0 = Disabled 1 = Enabled 1 0 = Disabled 1 = Enabled 1 0 = Disabled 1 = Enabled 1 0 = Disabled 1 = Enabled 1 Byte Bit(s) 7 Type RW 0 0 = Disabled 1 1 = Enabled Default 1 6 5 4 3 2 1 0 RW 0 = Disabled 1 = Enabled 1 0 0 0 0 0 0 RW See Table 2: LCD Spread Select Table IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 10 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) 7 6 5 4 2 Output Enable Register Pin # Name Descri ption This bit controls whether the CPU[0] output CPU0 Enable buffer is enabled or not. This bit controls whether the CPU[1] output CPU1 Enable buffer is enabled or not. This bit controls whether the CPU[2] output CPU2 Enable buffer is enabled or not. This bit controls whether the SRC[0] output SRC0 Enable buffer is enabled or not. This bit controls whether the SRC[1] output SRC1 Enable buffer is enabled or not. This bit controls whether the SRC[2] output SRC2 Enable buffer is enabled or not. This bit controls whether the DOT output DOT Enable buffer is enabled or not. This bit controls whether the LCD output buffer LCD100 Enable is enabled or not. 3 Output Control Register Pin # Name Descri ption Reserved Reserved This bit controls whether the REF output REF Enable buffer is enabled or not. These bits control the edge rate of the REF clock. This bit controls whether the CPU[0] output buffer is free-running or stoppable. If it is set to stoppable the CPU[0] output buffer will be disabled with the assertion of CPU_STP#. This bit controls whether the CPU[1] output buffer is free-running or stoppable. If it is set to stoppable the CPU[1] output buffer will be disabled with the assertion of CPU_STP#. This bit controls whether the CPU[2] output buffer is free-running or stoppable. If it is set to stoppable the CPU[2] output buffer will be disabled with the assertion of CPU_STP#. Type RW RW RW RW RW RW RW RW 0 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 1 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Default 1 1 1 1 1 1 1 1 Type 0 1 Default 0 0 1 RW 0 = Disabled 1 = Enabled REF Slew 3 RW 00 = Slow Edge Rate 01 = Medium Edge Rate 10 = Fast Edge Rate 11 = Reserved 10 2 CPU0 Stop Enable RW Free Running Stoppable 0 1 CPU1 Stop Enable RW Free Running Stoppable 0 0 CPU2 Stop Enable RW Free Running Stoppable 0 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 11 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 CPU PLL M/N Register Pin # Name CPU N Div8 CPU N Div9 CPU M Div5 CPU M Div4 CPU M Div3 CPU M Div2 CPU M Div1 CPU M Div0 Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bit (5:0) Type 0 1 Default RW X The decimal representation of M RW X and N Divider in Byte 4 and 5 will RW X configure the CPU VCO RW X frequency. Default at power up RW X = latch-in. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X 5 CPU PLL M/N Register Pin # Name Control Function CPU N Div7 CPU N Div6 CPU N Div5 N Divider Programming Byte5 bit(7:0) and CPU N Div4 Byte5 bit(7:6) CPU N Div3 CPU N Div2 CPU N Div1 CPU N Div0 6 DOT96 PLL M/N Register Pin # Name DOT N Div8 DOT N Div9 DOT M Div5 DOT M Div4 DOT M Div3 DOT M Div2 DOT M Div1 DOT M Div0 Type 0 1 Default RW X The decimal representation of M RW X and N Divider in Byte 4 and 5 will RW X configure the CPU VCO RW X frequency. Default at power up RW X = latch-in. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bit (5:0) Type 0 1 Default RW X RW The decimal representation of M X RW and N Divider in Byte 6 and 7 will X configure the DOT VCO RW X frequency. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X RW X 7 DOT96 PLL M/N Register Pin # Name Control Function DOT N Div7 DOT N Div6 DOT N Div5 N Divider Programming Byte7 bit(7:0) and DOT N Div4 Byte6 bit(7:6) DOT N Div3 DOT N Div2 DOT N Div1 DOT N Div0 Type 0 1 Default RW X RW The decimal representation of M X RW and N Divider in Byte 6 and 7 will X configure the DOT VCO RW X frequency. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X RW X IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 12 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) 7 6 5 4 3 2 1 0 8 LCD100 PLL M/N Register Pin # Name LCD100 N Div8 LCD100 N Div9 LCD100 M Div5 LCD100 M Div4 LCD100 M Div3 LCD100 M Div2 LCD100 M Div1 LCD100 M Div0 Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bit (5:0) Type 0 1 Default RW X RW The decimal representation of M X RW and N Divider in Byte 8 and 9 will X configure the DOT VCO RW X frequency. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X RW X 9 LCD100 PLL M/N Register Pin # Name Control Function LCD100 N Div7 LCD100 N Div6 LCD100 N Div5 N Divider Programming Byte9 bit(7:0) and LCD100 N Div4 Byte8 bit(7:6) LCD100 N Div3 LCD100 N Div2 LCD100 N Div1 LCD100 N Div0 10 Status Readback Register Pin # Name 37 FSB 9 FSC 24 CR0# Readbk Real 28 CR1# Readbk Real 36 CR2# Readbk Real Reserved Reserved Reserved Type 0 1 Default RW X RW The decimal representation of M X RW and N Divider in Byte 8 and 9 will X configure the DOT VCO RW X frequency. VCO Frequency = RW X 14.318 x [NDiv(11:0)] / RW X [MDiv(5:0)] RW X RW X Descri ption Frequency Select B Frequency Select C time CR0# State Indicator time CR1# State Indicator time CR2# State Indicator Type R R R R R 0 1 See Table 1: CPU Frequency Select Table CR0# is Low CR0# is High CR1# is Low CR1# is High CR2# is Low CR2# is High Default Latch Latch X X X 0 0 0 11 Revision ID/Vendor ID Register Pin # Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Descri ption Revision ID Vendor ID Type R R R R R R R R 0 1 Vendor specific Default X X X X 0 0 0 1 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 13 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 12 Device ID Register Pin # Name DEV_ID3 DEV_ID2 DEV_ID1 DEV_ID0 Reserved Reserved Reserved Reserved 13 Reserved Register Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 14 Reserved Register Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 15 Byte Count Register Pin # Name Reserved BC6 BC5 BC4 BC3 BC2 BC1 BC0 Descri ption Device ID MSB Device ID 2 Device ID 1 Device ID LSB Type R R R R 0 1 Default 1 0 1 0 0 0 0 0 Control Function Type 0 1 Default 0 0 0 0 0 0 0 0 Control Function Type 0 1 Default 0 0 0 0 0 0 0 0 Control Function Byte Count 6 (MSB) Byte Count 5 Byte Count 4 Byte Count 3 Byte Count 2 Byte Count 1 Byte Count LSB Type RW RW RW RW RW RW RW 0 1 Specifies Number of bytes to be read back during an SMBus read. Default is 0xF. Default 0 0 0 0 1 1 1 1 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 14 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16 M/N Enable Register Pin # Name MN Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Enables PLL MN programming Type RW 0 MN Disabled 1 MN Enabled Default 0 0 0 0 0 0 0 0 17 CPU PLL Spread Spectrum Index Register Pin # Name Control Function CPUSSP7 CPUSSP6 CPUSSP5 Spread Spectrum Programming bit(7:0) CPUSSP4 Contact IDT before editing these values. CPUSSP3 CPUSSP2 CPUSSP1 CPUSSP0 18 CPU PLL Spread Spectrum Index Register Pin # Name Control Function CPUSSP15 CPUSSP14 CPUSSP13 Spread Spectrum Programming bit(15:8) CPUSSP12 Contact IDT before editing these values. CPUSSP11 CPUSSP10 CPUSSP9 CPUSSP8 19 LCD100 PLL Spread Spectrum Index Register Pin # Name Control Function LCDSSP7 LCDSSP6 LCDSSP5 Spread Spectrum Programming bit(7:0) LCDSSP4 Contact IDT before editing these values. LCDSSP3 LCDSSP2 LCDSSP1 LCDSSP0 Type 0 1 RW RW RW These Spread Spectrum bits in RW Byte 17 and 18 will program the spread percentage of the CPU RW and SRC outputs RW RW RW Default X X X X X X X X Type 0 1 RW RW RW These Spread Spectrum bits in RW Byte 17 and 18 will program the spread percentage of the CPU RW and SRC outputs RW RW RW Default X X X X X X X X Type 0 1 RW RW RW These Spread Spectrum bits in RW Byte 19 and 20 will program the spread percentage of the CPU RW and SRC outputs RW RW RW Default X X X X X X X X IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 15 ICS9UMS9610 PC MAIN CLOCK Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 LCD100 PLL Spread Spectrum Index Register Pin # Name Control Function LCDSSP15 LCDSSP14 LCDSSP13 Spread Spectrum Programming bit(15:8) LCDSSP12 Contact IDT before editing these values. LCDSSP11 LCDSSP10 LCDSSP9 LCDSSP8 21 CPU PLL M/N Register Pin # Name CPU NDIV 10 CPU NDIV 11 Reserved Reserved Reserved Reserved Reserved Reserved 22 LCD100 PLL M/N Register Pin # Name LCD NDIV 10 LCD NDIV 11 Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 RW RW RW These Spread Spectrum bits in RW Byte 19 and 20 will program the spread percentage of the CPU RW and SRC outputs RW RW RW Default X X X X X X X X Control Function N Divider Prog bit 10 N Divider Prog bit 11 Type RW RW 0 1 See Byte 4/5 Description Default X X 0 0 0 0 0 0 Control Function N Divider Prog bit 10 N Divider Prog bit 11 Type RW RW 0 1 See Byte 8/9 Description Default X X 0 0 0 0 0 0 IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 16 ICS9UMS9610 PC MAIN CLOCK Test Clarification Table Comments HW TEST_SEL HW PIN TEST_MODE OUTPUT HW PIN low Vth input TEST_MODE is a real time input >0.7V >0.7V X 0.7V NORMAL HI-Z REF/N IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 17 ICS9UMS9610 PC MAIN CLOCK MLF Top Mark Information (9UMS9610) 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 ICS UMS9610yL YYWW C of O ####### 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 Line 1. Company name Line 2. Part Number Line 3. YYWW = Date Code Line 3. Country of Origin Line 4. ####### = Lot Number IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 18 ICS9UMS9610 PC MAIN CLOCK Seating Plane Index Area N Anvil Singulation A1 A3 L (Ref.) (N D -1)x e (Ref.) ND & N Even N 1 (Typ.) e 2 If N & N D are Even (N -1)x e 2 E2 E2 2 (Ref.) OR Top View Sawn Singulation b A (Re f.) e D2 2 D2 D ND & N Odd C Thermal Base Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.40 BASIC DIMENSIONS SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 48L TOLERANCE 48 12 12 6.00 x 6.00 3.95 / 4.25 3.95 / 4.25 0.30 / 0.50 Ordering Information Pa rt / Order Num ber 9UMS9610CKLF 9UMS9610CKLFT Ma rking see page 18 Shipping Packa ging Tubes Tape and Reel Pa ckage 48-pin MLF 48-pin MLF Tem pera ture 0 to +85° C 0 to +85° C Par ts that ar e orde r e d w ith a "LF" s uffix to the part num be r are the Pb-Fr e e configuration and ar e RoHS com pliant. IDTTM/ICSTM PC MAIN CLOCK 1336—06/01/09 19 ICS9UMS9610 PC MAIN CLOCK Revision History Rev. 0.1 0.15 0.2 0.3 0.4 0.5 Issue Date 04/25/07 05/03/07 5/18/2007 8/31/2007 9/11/2007 9/13/2007 Description Initial Release Corrected CLKPWRGD#/PD polarity Updated Test Clarification Table with the correct voltage levels. Updated Input Pin names to indicate maximum Input voltage level Added Logic Level and Input Level Tolerance Columns to Pin Descriptions. Clarified that X1 is 1.5V only input 1. Byte Count in Byte 15 is 7 bits, not 8 bits. B15b7 is now reserved. 2. Modified PLL programming formulas in Bytes(4:9). N is 12 bits instead of 10 bits. 3. Changed REF_3.3 output name to reflect default drive strength (new name is REF_3.3_2x). Updated By tes [9:4]. Added Bytes 16-22 to the SMBUS. Added MLF Top Mark Information. Updated Electrical Specifications Updated Electrical Specifications Moved to final. Updated electrical specs; TA spec in ordering information. Page # 1 2, 3 2 0.6 0.7 0.8 0.9 0.91 0.92 A B 10/23/007 11/6/2007 11/29/2007 2/26/2008 7/8/2008 7/21/2008 5/21/2009 6/1/2009 Various 12-13 15-16 18 5-7 5-7 Various Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 20