IDT70121L55J

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT Integrated Device Technology, Inc. IDT70121S/L IDT70125S/L FEATURES: • High-speed access – Commercial: 25/35/45/55ns (max.) • Low-power operation – IDT70121/70125S Active: 500mW (typ.) Standby: 5mW (typ.) – IDT70121/70125L Active: 500mW (typ.) Standby: 1mW (typ.) • Fully asychronous operation from either port • MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip • On-chip port arbitration logic (IDT70121 only) • BUSY output flag on Master; BUSY input on Slave • INT flag for port-to-port communication • Battery backup operation—2V data retention • TTL-compatible, signal 5V (± 10%) power supply • Available in 52-pin PLCC • Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications DESCRIPTION: The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM together with the IDT70125 “SLAVE” Dual-Port in 18bit-or-more word width systems. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 18-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power-down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for Data/Control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. FUNCTIONAL BLOCK DIAGRAM OE L CE L R/ WL OER R/WR CER I/O0L - I/O8L I/O Control I/O Control I/O0R-I/O 8R BUSY L (1,2) BUSY R Address Decoder 11 (1,2) A10L A0L MEMORY ARRAY Address Decoder A11R A0R 11 NOTES: 1. 70121 (MASTER): BUSY is non-tristated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is totem-pole output. CE L OE L R/ WL ARBITRATION INTERRUPT SEMAPHORE LOGIC CE R OE R R/WR INTL(2) INTR 2654 drw 01 (2) The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. OCTOBER 1996 DSC-2654/4 6.10 1 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE DESCRIPTION (Cont'd): Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 500mW of power. Low-power (L) versions offer battery backup data retention capability with each port typically consuming 200µW from a 2V battery. The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. PIN CONFIGURATIONS (1,2) WL WR R/ INTR INTL R/ VCC A10R A10L CEL CER A0L OEL INDEX BUSYR BUSYL 21 22 23 24 25 26 27 28 29 30 31 32 I/O4L I/O5L I/O6L I/O7L I/O8L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R 33 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 9 10 11 12 13 14 15 16 17 18 19 20 1 8 46 45 44 43 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O8R I/O7R RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Commercial Ambient Temperature 0°C to +70°C GND 0V VCC 5.0V ± 10% 2654 tbl 02 51 50 7 6 3 52 49 5 2 48 4 IDT70121/125 J52-1 PLCC TOP VIEW(3) 47 42 41 40 39 38 37 36 35 34 RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 –0.5 (1) Typ. 5 0 – – Max. 5.5 0.0 6.0(2) 0.8 Unit V V V V 2654 tbl 03 2654 drw 02 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the orientation of the actual part-marking. NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TBIAS TSTG IOUT (2) CAPACITANCE(1) (TA = +25°C, f = 1.0MHz) Unit V °C °C °C mA Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial –0.5 to +7.0 0 to +70 –55 to +125 –55 to +125 50 NOTES: 2654 tbl 13 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. NOTES: 2654 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V. 6.10 2 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%) 70121S 70125S Min. Max. — — — 2.4 10 10 0.4 — 70121L 70125L Min. Max. Unit — — — 2.4 5 5 0.4 — µA µA V V 2654 tbl 04 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(5) Output Leakage Current Output Low Voltage Output High Voltage (5) Test Condition VCC = 5.5V, VIN = 0V to VCC VCC = 5.5V, CE = VIH VOUT = 0V to VCC IOL = 4mA IOH = –4mA NOTE: 1. At Vcc < 2.0V leakages are undefined. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (VCC = 5V ± 10%) Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports—TTL Level Inputs) Standby Current (One Port—TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition 70121X25 70125X25 70121X35 70125X35 70121X45 70125X45 70121X55 70125X55 Version Com’l. S L S L S L S L S L Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit 125 260 125 250 125 245 125 240 125 220 125 210 125 205 125 200 30 30 80 80 1.0 0.2 70 70 65 45 175 145 15 5 170 140 30 30 80 80 1.0 0.2 70 70 65 45 165 135 15 5 160 130 30 30 80 80 1.0 0.2 70 70 65 45 160 130 15 5 155 125 30 30 80 80 1.0 0.2 70 70 65 45 155 125 15 5 150 120 mA CE = VIL,Outputs Open, f = fMAX(2) ISB1 CE"A" and CE"B" = VIH, f = fMAX(2) CE"A"=VIL and CE"B"=VIH(5) Active Port Outputs Open, f = fMAX(2) VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0(3) Com’l. mA ISB2 Com’l. mA ISB3 CE"A" and CE"B" ≥ VCC – 0.2V, CE"A"VCC-0.2V(5 ) Com’l. mA ISB4 Com’l. mA VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs Open, f = fMAX(2) NOTES: 1. “X” in part numbers indicates power rating (S or L). 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc=5V, TA=+25°C for Typical values, and they are not production tested. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 2654 tbl 05 6.10 3 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE DATA RETENTION CHARACTERISTICS (L Version Only) 70121L/70125L Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition VCC = 2.0V, CE ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Com’l. Min. 2 — 0 tRC(2) Typ.(1) — 100 — — Max. — 1500 — — Unit V µA ns ns 2654 tbl 06 NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested. DATA RETENTION WAVEFORM DATA RETENTION MODE Vcc 4.5V tCDR VDR ≥ 2V 4.5V tR VDR VIH 2654 drw 03 CE VIH 5V 5V 1250Ω 1250Ω DATAOUT AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2 2654 tbl 07 DATAOUT BUSY INT 775Ω 30pF 775Ω 5pF 2654 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ, tHZ, tWZ, tOW) Including scope and jig. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) 70121X25 70125X25 70121X35 70125X35 70121X45 70125X45 70121X55 70125X55 Symbol Parameter Read Cycle tRC Read Cycle Time tAA Address Access Time tACE Chip Enable Access Time tAOE Output Enable Access Time tOH Output Hold from Address Change tLZ Output Low-Z Time(1,2) tHZ Output High-Z Time(1,2) tPU Chip Enable to Power-Up Time(2) tPD Chip Disable to Power-Down Time(2) Min. Max. Min. Max. Min. Max. Min. Max. Unit 25 — — — 0 0 — 0 — — 25 25 12 — — 10 — 50 35 — — — 0 0 — 0 — — 35 35 25 — — 15 — 50 45 — — — 0 0 — 0 — — 45 45 30 — — 20 — 50 55 — — — 0 0 — 0 — — 55 55 35 — — 30 — 50 ns ns ns ns ns ns ns ns ns NOTES: 1. Transition is measured ± 500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. “X” in part numbers indicates power rating (S or L). 2654 tbl 08 6.10 4 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1,2,4) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID 2654 drw 05 tOH BUSYOUT tBDD (3,4) TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5,6) tACE CE tAOE (4) tHZ (2) OE tLZ DATAOUT tLZ ICC CURRENT ISS tPU (1) (1) tHZ VALID DATA tPD (4) (2) 50% 50% 2654 drw 06 NOTES: 1. Timing depends on which signal is aserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultanious read operations BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low. 6. R/W = VIH, CE = V IL, and OE = VIL. Address is valid prior to or coincident with CE transition Low. 6.10 5 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) 70121X25 70125X25 70121X35 70125X35 70121X45 70125X45 70121X55 70125X55 Symbol Parameter Write Cycle Write Cycle Time(3) tWC tEW Chip Enable to End-of-Write tAW Address Valid to End-of-Write tAS Address Set-up Time tWP Write Pulse Width(6) tWR Write Recovery Time tDW Data Valid to End-of-Write tHZ Output High-Z Time(1,2) tDH Data Hold Time(5) tWZ Write Enabled to Output in High-Z(1,2) tOW Output Active from End-of-Write(1,2) Min. Max. Min. Max. Min. Max. Min. Max. Unit 25 20 20 0 20 0 12 — 0 — 0 — — — — — — — 10 — 10 — 35 30 30 0 30 0 20 — 0 — 0 — — — — — — — 15 — 15 — 45 35 35 0 35 0 20 — 0 — 0 — — — — — — — 20 — 20 — 55 40 40 0 40 0 20 — 0 — 0 — — — — — — — 30 — 30 — ns ns ns ns ns ns ns ns ns ns ns NOTES: 2654 tbl 09 1. Transition is measured ± 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA . 4. “X” in part numbers indicates power rating (S or L). 5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.Although tDH and tow values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW. 6. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) tWC ADDRESS tHZ (7) OE tAW (3) tWR (2) (7) CE R/ W tAS (6) tWP tHZ tWZ DATAOUT (4) (7) tOW (4) tDW DATAIN tDH NOTES: 2654 drw 07 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 6.10 6 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5) CE tWC ADDRESS tAW CE tAS R/ (6) tEW (2) tWR (3) W tDW tDH DATAIN 2654 drw 08 NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6) 70121X25 70125X25 70121X35 70125X35 70121X45 70125X45 70121X55 70125X55 Symbol Parameter Busy Timing (For Master IDT70121 Only) tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD tWH tWB tWH tWDD tDDD Min. Max. Min. Max. Min. Max. Min. Max. Unit — — — — — — 5 — 15 0 20 20 20 20 50 35 — 30 — — — 50 35 — — — — — — 5 — 20 0 20 — — 20 20 20 20 60 45 — 30 — — — 60 45 — — — — — — 5 — 20 0 20 — — 20 20 20 20 70 55 — 35 — — — 70 55 — — — — — — 5 — 20 0 20 — — 30 30 30 30 80 65 — 45 — — — 80 65 ns ns ns ns ns ns ns ns ns ns ns ns ns BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay(1) Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data(3) Write Hold After BUSY(5) Write to BUSY Input(4) Write Hold After BUSY (5) Busy Timing (For Slave IDT70125 Only) 15 — — Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay(1) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY“. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.. 5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 6. “X” in part numbers indicates power rating (S or L). 2654 tbl 10 6.10 7 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND tWC ADDR 'A' MATCH tWP R/ BUSY (1,2,3) BUSY W'A' tDW tDH VALID tAPS (1) DATAIN 'A' ADDR'B' MATCH tBDA tBDD BUSY'B' tWDD DATAOUT 'B' tDDD (4) 2654 drw 09 VALID NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT 70125). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'. TIMING WAVEFORM OF WRITE WITH BUSY BUSY tWP R/ W'A' tWB tWH (1) BUSY'B' R/ W'B' (2) 2654 drw 10 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 6.10 8 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) CE ADDR L and R ADDRESSES MATCH CER tAPS CEL tBAC tBDC BUSYL 2654 drw 12 NOTES: 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS (1) tRC OR tWC ADDR'A' tAPS ADDR'B' tBAA tBDA ADDRESSES MATCH ADDRESSES DO NOT MATCH BUSY'B' 2654 drw 13 NOTES: 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) 70121X25 70125X25 70121X35 70125X35 70121X45 70125X45 70121X55 70125X55 Symbol Parameter Interrupt Timing tAS Address Set-up Time tWR Write Recovery Time tINS Interrupt Set Time tINR Interrupt Reset Time NOTE: 1. "X" in part numbers indicates power rating (S or L). Min. Max. Min. Max. Min. Max. Min. Max. Unit 0 0 — — — — 25 25 0 0 — — — — 25 35 0 0 — — — — 40 40 0 0 — — — — 45 45 ns ns ns ns 2654 tbl 11 6.10 9 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF INTERRUPT MODE tWC ADDR'A' INTERRUPT SET ADDRESS tAS(3) R/ (2) tWR (4) W'A' tINS(3) INT'B' NOTES:. 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. See Interupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 2654 drw 14 TRUTH TABLES TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL(4) Left or Right Port(1) R/W CE D0–8 OE X H X Z X L H H H L L L X X L H Z DATAIN DATAOUT Z Function Port Disabled and in PowerDown Mode, ISB2 or ISB4 CER = CEL = H, Power-Down Mode, ISB1 or ISB3 Data on Port Written Into Memory(2) Data in Memory Output on Port(3) High-impedance Outputs 2654 tbl 12 NOTES: 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = VIL, data is not written. 3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance. TRUTH TABLE II – INTERRUPT FLAG(1,4) R/WL L X X X CEL L X X L Left Port OEL X X X L A0L – A10L 7FF X X 7FE INTL X X L(3) H(2) R/WR X X L X CER X L L X Right Port OER X L X X A0L – A10R X 7FF 7FE X INTR L H(3) X X (2) Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 2654 tbl 13 NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = VIH,' L' = VIL,' X' = DON’T CARE. 6.10 10 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION The IDT70121/125 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70121/125 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. INTERRUPTS If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table. The left port clears the interrupt by access address location 7FE access when CER = OER = VIL, R/W is a "Don't Care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (9 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Table I for the interrupt operation. BUSY LOGIC Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by using the IDT70125 (SLAVE). In the IDT70125, the busy pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT70121/125 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT70121/125 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70121 RAM the busy pin is an output of the part, and the busy pin is an input of the IDT70125 as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write DECODER IDT70121 MASTER Dual Port RAM IDT70125 CE BUSYR BUSYL SLAVE Dual Port RAM CE BUSYR BUSYL IDT70121 MASTER Dual Port RAM IDT70125 CE BUSYR BUSYL BUSYL SLAVE Dual Port RAM CE BUSYR BUSYR BUSYL 2654 drw 15 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70121 (Master) and IDT70125 (Slave) RAMs. operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/ signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. W 6.10 11 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0°C to +70°C) J 52-pin PLCC (J52-1) 25 35 45 55 L S 70121 70125 Speed in nanoseconds Low Power Standard Power 18K (2K x 9-Bit) MASTER Dual-Port RAM w/ Interrupt 18K (2K x 9-Bit) SLAVE Dual-Port RAM w/ Interrupt 2654 drw 16 6.10 12