IDT71V124

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout Features ◆ ◆ IDT71V124 Description The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT’s high-performance, highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 7ns, with address access times as fast as 15ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ. ◆ ◆ ◆ ◆ ◆ ◆ 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Commercial (0°C to +70°C) and Industrial (–40°C to +85°C) temperature options Equal access and cycle times — Industrial and Commercial: 15/20ns One Chip Select plus one Output Enable pin Bidirectional inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Available in 32-pin 400 mil Plastic SOJ. Functional Block Diagram A0 A16 I/O0 - I/O7 O WE OE CS N NC I A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N • • • ADDRESS E • • • 1,048,576-BIT MEMORY ARRAY DECODER 8 OR O F 8 I/O CONTROL 8 CONTROL LOGIC 3484 drw 01 AUGUST 2000 1 ©2000 Integrated Device Technology, Inc. DSC-3484/05 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Pin Configuration A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 1 32 2 31 3 30 4 29 28 5 6 SO32-3 27 26 7 25 8 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 Absolute Maximum Ratings(1) Symbol VTERM TA TBIAS TSTG PT IOUT (2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –0.5 to +4.1 0 to +70 –55 to +125 –55 to +125 (2) Unit V o o C C C o SOJ Top View Truth Table(1,2) CS L L L H VHC (3) OE L X H X X WE H L H X X DATAOUT DATAIN High-Z NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VDD –0.2V. 3. Other inputs ≥VHC or ≤VLC. Capacitance Symbol CIN CI/O (TA = +25°C, f = 1.0MHz, SOJ package) Parameter(1) Input Capacitance I/O Capacitance O N NC I A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N 3484 drw 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed VDD + 0.5V. E 0.5 50 W mA 3484 tbl 02 I/O Function Read Data Write Data Recommended Operating Temperature and Supply Voltage Grade Temperature GND 0V VDD See Below See Below 3484 tb l 02a Output Disabled Commercial Industrial 0°C to +70°C High-Z Deselected – Standby (I SB) –40°C to +85°C 0V High-Z Deselected – Standby (ISB1 ) 3484 tbl 01 Recommended DC Operating Conditions Symbol VDD Parameter Min. 3.0 0 Typ. 3.3 0 Max. 3.6 0 Unit V V V V 3484 tbl 04 Conditions VIN = 3dV VOUT = 3dV NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. OR O F Max. 8 8 Unit pF Supply Voltage Ground GND VIH VIL pF Input High Voltage Input Low Voltage 2.0 –0.3(1) ____ ____ VDD +0.3 0.8 3484 tbl 03 NOTE: 1. VIL (min.) = –1V for pulse width less than 5ns, once per cycle. DC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) IDT71V124 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VDD = M ax., VIN = GND to VDD VDD = M ax., CS = VIH, VOUT = GND to VDD IOL = 8mA, VDD = M in. IOH = –8mA, VDD = M in. Min. ___ ___ ___ Max. 5 5 0.4 ___ Unit µA µA V V 3484 tbl 05 2.4 6.42 2 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics(1) (VDD = 3.3V ± 10%, VLC = 0.2V, VHC = VDD – 0.2V) 71V124S15 Symbol ICC ISB Parameter Dynamic Operating Current CS < VIL, Outputs Open, VDD = M ax., f = f MAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VDD = M ax., f = f MAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VDD = M ax., f = 0(2) VIN < VLC or VIN > VHC Com'l. 100 35 5 Ind. 120 40 7 71V124S20 Com'l. 95 30 5 Ind. 115 35 7 Unit mA mA mA ISB1 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load DATA OUT 30pF O N NC I A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N GND to 3.0V 3ns 1.5V 1.5V See Figure 1 and 2 3484 tbl 07 E 3484 tbl 06 3.3V 3.3V 298Ω 216Ω OR O F 3484 drw 03 298Ω DATAOUT 5pF* 216Ω 3484 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 6.42 3 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics Symbol READ CYCLE tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tPU(1) tPD(1) WRITE CYCLE tWC tAW tCW tAS tWP tWR tDW tDH tOW(1) tWHZ(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Parameter (VDD = 3.3V ± 10%, Commercial and Industrial Ranges) 71V124S15 Min. Max. 71V124S20 Min. Max. Unit 15 ____ ____ 20 ____ ____ ns ns ns ns ns ns ns ns ns ns ns 15 15 ____ 20 20 ____ ____ ____ 3 0 Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time Write Cycle Time Address Valid to End of Write Chip Select to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Output Active from End of Write O IN N A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N ____ 0 0 C 7 7 ____ E 3 0 8 ____ 8 0 ____ 5 0 7 4 ____ 4 0 ____ 0 ____ ____ ____ 15 ____ 20 15 ____ ____ 20 ____ ____ ns ns ns ns ns ns ns ns ns ns 3484 tbl 08 12 15 15 0 12 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 12 0 15 0 9 0 4 0 Write Enable to Output in High-Z NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. OR O F 8 0 ____ ____ 3 0 ____ ____ 5 8 6.42 4 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges (1) Timing Waveform of Read Cycle No. 1 tRC ADDRESS tAA OE tOE CS tOLZ (5) (5) (3) tACS tCLZ DATAOUT VCC SUPPLY ICC CURRENT ISB Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS DATAOUT PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. O IN N A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N tPU tPD HIGH IMPEDANCE C tCHZ DATAOUT VALID E (5) tOHZ (5) 3484 drw 05 tAA tOH tOH DATAOUT VALID 3484 drw 06 OR O F 6.42 5 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWR tAS WE tWP (2) DATAOUT DATAIN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS CS WE O IN N A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N tWHZ (5) tOW (3) HIGH IMPEDANCE tDW tDH C (5) E tCHZ (5) (3) DATAIN VALID 3484 drw 07 tAW tAS tCW tWR (3) DATAIN OR O F tDW DATAIN VALID tDH 3484 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Ordering Information IDT 71V124 Device Type S Power XX Speed X Package X Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Y 400-mil SOJ (SO32-3) O N NC I A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N 15 20 Speed in nanoseconds E 3484 drw 09 OR O F 6.42 7 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 11/1/99 Pg. 2 Pg. 2 Pg. 4 Pg. 4 Pg. 6 Pg. 8 08/30/00 Updated to new format Expressed commercial and industrial temperature ranges on DC Electrical table Added Recommended Operating Temperature and Supply Voltage table Expressed commercial and industrial ranges on AC Electrical table Revised footnotes and notes on AC Electrical table Revised footnotes on Write Cycle No. 1 diagram Added datasheet document history Part in obsolescence; order part 71V124SA. See PDN# S-0004 O N NC I A T CE 4S NS R S 12 IG AEVS P L 71 DE O ER W SD E BR N OR O F E CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: sramhelp@idt.com 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc.