IDT71V547S100PF

128K X 36, 3.3V Synchronous IDT71V547 SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Features 128K x 36 memory configuration, flow-through outputs Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized signal eliminates the need to control OE OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) BW Three chip enables for simple depth expansion Single 3.3V power supply (±5%) Packaged in a JEDEC standard 100-pin TQFP package The IDT71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V547 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst in progress is stopped. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip was deselected or write initiated. The IDT71V547 has an on-chip burst counter. In the burst mode, the IDT71V547 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V547 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density. x x x x x x x x x x Description The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBT TM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle, its associated data cycle occurs, be it read or write. Pin Description Summary A0 - A16 CE1, CE2, CE2 OE R/W CEN BW 1, BW 2, BW 3, BW 4 CLK ADV/ LD LBO I/O0 - I/O31, I/OP1 I/OP4 VDD VSS Address Inputs Three Chip Enables Output Enable Read/Write Signal Clock Enable Individual Byte Write Selects Clock Advance Burst Address / Load New Address Linear / Interleaved Burst Order Data Input/Output 3.3V Power Ground Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Static Synchronous Static Static 3822 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. DECEMBER 1999 DSC-3822/03 1 ©1999 Integrated Device Technology, Inc. IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol A0 - A16 Pin Function Address Inputs I/O I Active N/A Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD Low, CEN Low and true chip enables. ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high. R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN m ust be sampled low at rising edge of clock. Synchronous byte write enables. Enable 9-bit byte has its own active low byte write enable. On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW 1 - BW 4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW 1 - BW 4 can all be tied low if always doing write to the entire 36-bit word. Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V547. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. Synchronout active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. This is the clock input to the IDT71V547. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static DC input. Asynchronous output enable. OE m ust be low to read data from the 71V547. When OE is high the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. 3.3V power supply input. Ground pin. 3822 tbl 02 ADV/LD Address/Load I N/A R/W Read/Write I N/A CEN Clock Enable I LOW BW 1 - BW 4 Individual Byte Write Enables I LOW CE1, CE2 Chip Enables I LOW CE2 CLK I/O0 - I/O31 I/OP1 - I/OP4 LBO Chip Enable Clock Data Input/Output Linear Burst Order Output Enable I I I/O I HIGH N/A N/A LOW OE I LOW VDD VSS Power Supply Ground N/A N/A N/A N/A NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 2 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram LBO Address A [0:16] C E 1, CE2 C E 2 R/W C EN ADV/LD BW x D Clk D Q Control D Q 128K x 36 BIT MEMORY ARRAY Address Input Register DI DO Q Control Logic Mux Clock Sel OE Gate , Data I/O [0:31], I/O P[1:4] 3822 drw 01 Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Temperature 0OC to +70OC -40OC to +85OC VSS 0V 0V VDD 3.3V±5% 3.3V±5% 3822 tbl 03 Recommended DC Operating Conditions Symbol VDD VSS VIH VIH VIL Parameter Supply Voltage Ground Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. 3.135 0 2.0 2.0 -0.5 (1) Typ. 3.3 0 ____ ____ ____ Max. 3.465 0 4.6 VDD+0.3 0.8 (2) Unit V V V V V 3822 tbl 04 NOTES: 1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. 3 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDD VSS I/O18 I/O19 I/O20 I/O21 VSS VDD I/O22 I/O23 VSS(1) VDD VDD VSS I/O24 I/O25 VDD VSS I/O26 I/O27 I/O28 I/O29 VSS VDD I/O30 I/O31 I/OP4 BW 2 BW 1 CE 2 VDD VSS CLK R/W C EN OE ADV/LD NC(2) NC(2) A8 A9 Pin Configuration A6 A7 CE1 CE2 BW 4 BW 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 PK100-1 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/OP2 I/O15 I/O14 VDD VSS I/O13 I/O12 I/O11 I/O10 VSS VDD I/O9 I/O8 VSS VSS VDD VSS I/O7 I/O6 VDD VSS I/O5 I/O4 I/O3 I/O2 VSS VDD I/O1 I/O0 I/OP1 LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 Top View TQFP 3822 drw 02 NOTES: 1. Pin 14 does not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively. Absolute Maximum Ratings(1) Symbol VTERM(2) VTERM TA TBIAS TSTG PT IOUT (3) Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +4.6 -0.5 to VDD+0.5 0 to +70 -55 to +125 -55 to +125 2.0 50 Unit V V o (TA = +25°C, f = 1.0MHz, TQFP package) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 5 7 Unit pF pF 3822 tbl 06 Capacitance C C C NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. o o W mA 3822 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD and Input terminals only. 3. I/O terminals. 4 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) CEN L L L L L L H R/W L H X X X X X Chip(5) Enable Select Select X X Deselect X X ADV/LD L L H H L H X BW x Valid X Valid X X X X ADDRESS USED External External Internal Internal X X X PREVIOUIS CYCLE X X LOAD WRITE/ BURST WRITE LOAD READ/ BURST READ X DESELECT / NOOP X CURRENT CYCLE LOAD WRITE LOAD READ BURST WRITE (Advance Burst Counter)(2) BURST READ (Advance Burst Counter)(2) DESELECT or STOP (3) NOOP SUSPEND (4) I/O (1 cycle later) D(7) Q(7) D(7) Q(7) HiZ HiZ Previous Value 3822 tbl 07 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state one cycle after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if either one of thechip enable is false. 6. Device Outputs are ensured to be in High-Z during device power-up. 7. Q - data read from the device, D - data written to the device. Partial Truth Table for Writes(1) Operation READ WRITE ALL BYTES WRITE BYTE 1 (I/O [0:7], I/O P1) (2) (2) R/ W H L L L L L L BW 1 X L L H H H H BW 2 X L H L H H H BW 3 X L H H L H H BW 4 X L H H H L H 3822 tbl 08 WRITE BYTE 2 (I/O [8:15], I/OP2) WRITE BYTE 3 (I/O [16:23], I/OP3)(2) WRITE BYTE 4 (I/O [24:31], I/OP4) NO WRITE NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. (2) 5 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 A1 First Address Second Address Third Address Fourth Address (1) Sequence 2 A1 0 0 1 1 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 1 0 0 A0 1 0 1 0 3822 tbl 09 A0 0 1 0 1 0 0 1 1 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=VSS) Sequence 1 A1 First Address Second Address Third Address Fourth Address (1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 1 1 0 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 0 0 1 A0 1 0 1 0 3822 tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram(1) CYCLE CLOCK ADDRESS (A0 - A16) (2) A29 A30 A31 A32 A33 A34 A35 A36 A37 n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 (2) CONTROL (R/W , ADV/LD , BW x) (2) DATA I/O [0:31], I/O P[1:4] C29 C30 C31 C32 C33 C34 C35 C36 C37 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 D/Q36 ., NOTE: 1. This assumes CEN, CE1, CE2 and CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. 3822 drw 03 6 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 n+16 n+17 n+18 n+19 Address A0 X A1 X X A2 X X A3 X A4 X X A5 A6 A7 X A8 X A9 R/W H X H X X H X X L X L X X L H L X H X L ADV/LD L H L L H L H L L H L L H L L L H L H L CE(1) L X L H X L X H L X L H X L L L X L X L CEN L L L L L L L L L L L L L L L L L L L L BW x X X X X X X X X L L L X X L X L L X X L OE X L L L X X L L X X X X X X X L X X L L I/O D1 Q0 Q0+1 Q1 Z Z Q2 Q2+1 Z D3 D3+1 D4 Z Z D5 Q6 D7 D7+1 Q8 Q8+1 Load read Burst read Load read Deselect or STOP NOOP Load read Burst read Deselect or STOP Load write Burst write Load write Deselect or STOP NOOP Load write Load read Load write Burst write Load read Burst read Load write 3822 tbl 11 Comments NOTE: 1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 2. H = High; L = Low; X = Don't Care; Z = High Impedence. 7 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation(1) Cycle n n+1 Address A0 X R/ W H X ADV/LD L X CE(2) L X CEN L X BW x X X OE X L I/O X Q0 Comments Address and Control meet setup Co ntents of Address A0 Read Out 3822 tbl 12 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Burst Read Operation(1) Cycle n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 Address A0 X X X X A1 X A2 R/ W H X X X X H X H ADV/ LD L H H H H L H L CE(2) L X X X X L X L CEN L L L L L L L L BW x X X X X X X X X OE X L L L L L L L I/O X Q0 Q 0+1 Q 0+2 Q 0+3 Q0 Q1 Q 1+1 Comments A ddres s and C ontrol m eet setup A ddress A 0 R ead O ut, Inc. C ount A ddress A 0+1 R ead O ut, Inc. C ount A ddress A 0+2 R ead O ut, Inc. C ount A ddress A 0+3 R ead O ut, Load A 1 A ddress A 0 R ead O ut, Inc. C ount A ddress A 1 R ead O ut, Inc. C ount A ddress A 1+1 R ead O ut, Load A 2 3822 tbl 13 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Write Operation(1) Cycle n n+1 Address A0 X R/ W L X ADV/LD L X CE(2) L X CEN L L BW x L X OE X X I/O X D0 Comments Address and Control meet setup Write to Address A0 3822 tbl 14 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Burst Write Operation(1) Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X X X X A1 X A2 R/ W L X X X X L X L ADV/LD L H H H H L H L CE(2) L X X X X L X L CEN L L L L L L L L BW x L L L L L L L L OE X X X X X X X X I/O X D0 D0+1 D0+2 D0+3 D0 D1 D1+1 Comments Address and Control meet setup Address A0 Write, Inc. Count Address A0+1 Write, Inc. Count Address A0+2 Write, Inc. Count Address A0+3 Write, Load A1 Address A0 Write, Inc. Count Address A1 Write, Inc. Count Address A1+1 Write, Load A2 3822 tbl 15 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 8 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation With Clock Enable Used(1) Cycle n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 Address A0 X A1 X X A2 A3 A4 R/ W H X H X X H H H ADV/ LD L X L X X L L L CE(2) L X L X X L L L CEN L H L H H L L L BW x X X X X X X X X OE X X L L L L L L I/O X X Q0 Q0 Q0 Q1 Q2 Q3 Comments A ddres s and C ontrol m eet setup C lock n+ 1 Ignored A ddre ss A 0 R ead out, Load A 1 C lock Ignore d. D ata Q 0 is on the bus C lock Ignore d. D ata Q 0 is on the bus A ddre ss A 1 R ead out, Load A 2 A ddre ss A 2 R ead out, Load A 3 A ddre ss A 3 R ead out, Load A 4 3822 tbl 16 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Write Operation With Clock Enable Used(1) Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X A1 X X A2 A3 A4 R/W L X L X X L L L ADV/LD L X L X X L L L CE(2) L X L X X L L L CEN L H L H H L L L BW x L X L X X L L L OE X X X X X X X X I/O X X D0 X X D1 D2 D3 Comments Address and Control meet setup Clock n+1 Ignored Write data D0, Load A1 Clock Ignored Clock Ignored Write data D1, Load A2 Write data D2, Load A3 Write data D3, Load A4 3822 tbl 17 NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 9 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation with Chip Enable Used(1) Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 Address X X A0 X A1 X X A2 X X R/ W X X H X H X X H X X ADV/LD L L L L L L L L L L CE(1) H H L H L H H L H H CEN L L L L L L L L L L BW x X X X X X X X X X X OE X X X L X L X X L X I/O(3) ? Z Z Q0 Z Q1 Z Z Q2 Z Deselected Deselected Address A0 and Control meet setup Address A0 read out. Deselected Address A1 and Control meet setup Address A1 Read out. Deselected Deselected Address A2 and Control meet setup Address A2 read out. Deselected Deselected 3822 tbl 18 Comments NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 3. Device outputs are ensured to be in High-Z during device power-up. Write Operation with Chip Enable Used(1) Cycle n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 n+ 8 n+ 9 Address X X A0 X A1 X X A2 X X R/ W X X L X L X X L X X ADV/ LD L L L L L L L L L L CE(1 ) H H L H L H H L H H CEN L L L L L L L L L L BW x X X L X L X X L X X OE X X X X X X X X X X I/O ? Z Z D0 Z D1 Z Z D2 Z D eselected D eselected Address A 0 and Control m eet setup Addres s D0 W rite In. D eselected Address A 1 and Control m eet setup Addres s D1 W rite In. D eselected D eselected Address A 2 and Control m eet setup Addres s D2 W rite In. D eselected D eselected 3822 tbl 19 Comments NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 10 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +/-5%) Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage Current LBO Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage (1) Test Conditions VDD = Max., VIN = 0V to VDD VDD = Max., VIN = 0V to VDD CE > VIH o r OE > VIH, VOUT = 0V toVDD, VDD = Max. IOL = 5mA, VDD = Min. IOH = -5mA, VDD = Min. Min. ___ Max. 5 30 5 0.4 ___ Unit µA µA µA V V 3822 tbl 20 ___ ___ ___ 2.4 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD–0.2V, VLD = 0.2V) S80 Symbol IDD ISB1 ISB2 ISB3 Parameter Operating Power Supply Current Test Conditions Device Selected, Outputs Open, ADV/ LD = X, VDD = Max., VIN > VIH o r < VIL, f = fMAX(2) Com'l 250 40 100 40 Ind 260 45 110 45 S85 Com'l 225 40 95 40 Ind 235 45 105 45 S90 Com'l 225 40 95 40 Ind 235 45 105 45 S100 Com'l 200 40 90 40 Ind 210 45 100 45 Unit mA mA mA mA 3822 tbl 21 CMOS Standby Power Device Deselected, Outputs Open, Supply Current VDD = Max., VIN > VHD o r < VLD, f = 0(2) Clock Running Power Supply Current Idle Power Supply Current Device Deselected, Outputs Open, VDD = Max., VIN > VHD o r < VLD, f = fMAX(2) Device Selected, Outputs Open, CEN > VIH VDD = Max., VIN > VHD o r < VLD, f = fMAX(2) NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. AC Test Loads +1.5V 50Ω AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3V 2ns 1.5V 1.5V See Figure 1 3822 tbl 22 I/O Z0 = 50Ω 3822 drw 04 Figure 1. AC Test Load , 6 5 4 ∆tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 3822 drw 05 . 11 6.42 Figure 2. Lumped Capacitive Load, Typical Derating IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) 71V547S80 Symbol Clock Parameters tCYC tCH tCL (2) 71V547S85 Min. Max. 71V547S90 Min. Max. 71V547S100 Min. Max. Unit Parameter Min. Max. Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width 10.5 3 3 ____ 11 3.9 3.9 ____ 12 4 4 ____ 15 5 5 ____ ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ (2) Output Parameters tCD tCDC tCLZ (3,4,5) (3,4,5) Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time (3,4) (3.4) ____ 8 ____ ____ ____ 8.5 ____ ____ ____ 9 ____ ____ ____ 10 ____ ____ ns ns ns ns ns ns ns 2 4 ____ 2 4 ____ 2 4 ____ 2 4 ____ tCHZ tOE tOLZ 5 5 ____ 5 5 ____ 5 5 ____ 5 5 ____ ____ ____ ____ ____ Output Enable Low to Data Active Output Enable High to Data High-Z 0 ____ 0 ____ 0 ____ 0 ____ tOHZ 5 5 5 5 Setup Times tSE tSA tSD tSW tSADV tSC tSB Hold Times tHE tHA tHD tHW tHADV tHC tHB Clock Enable Hold Time Address Hold Time Data in Hold Time Read/Write (R/W) Hold Time Advance/Load (ADV/ LD) Hold Time Chip Enable/Select Hold Time Byte Write Enable (BWx) Hold Time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ____ Clock Enable Setup Time Address Setup Time Data in Setup Time Read/Write (R/W) Setup Time Advance/Load (ADV/ LD) Setup Time Chip Enable/Select Setup Time Byte Write Enable (BWx) Setup Time 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ____ 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ____ 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ____ 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ____ ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ____ 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ____ 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ____ ns ns ns ns ns ns ns 3822 tbl 23 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ NOTES: 1. Measured as HIGH above 2.0V and LOW below 0.8V. 2. Transition is measured ±200mV from steady-state. 3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 4. To avoid bus contention, the output buffers are designed such that t CHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than t CHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). . 12 tCYC tCH tSE tHE tCL CLK CEN tHADV tSADV ADV/LD tSW tHW R/W tSA tHA IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs ADDRESS tSC tHC A1 A2 Timing Waveform of Read Cycle(1, 2, 3, 4) 13 6.42 tCD tCDC tCD C E 1, C E 2(2) BW 1 - BW 4 OE (C EN high, eliminates current L-H clock edge) (Burst Wraps around to initial state) tCHZ tCLZ DATA Out Q(A1) Q(A2) Q(A2+1) Q(A2+2) Burst Read Q(A2+3) Q(A2+3) tCDC Q(A2) Read Read 3822 drw 06 Commercial and Industrial Temperature Ranges NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address and control are loaded into the SRAM. , tCYC CLK tSE tHE tCH tCL CEN tHADV tSADV ADV/LD tSW tHW R/W tSA tHA IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs ADDRESS tSC tHC A1 A2 C E 1, C E 2(2) tSB tHB Timing Waveform of Write Cycles(1,2,3,4,5) 14 B(A2) B(A2+1) B(A2+2) B(A2+3) B(A2) tSD tHD tHD tSD (CEN high, eliminates current L-H clock edge) (Burst Wraps around to initial state) BW 1 - BW 4 B(A1) OE DATA In D(A1) D(A2) D(A2+1) D(A2+2) Burst Write D(A2+3) D(A2) Write Write 3822 drw 07 Commercial and Industrial Temperature Ranges NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. . tCYC CLK tSE tHE tCH tCL CEN tHADV tSADV ADV/LD tSW tHW R/W tSA tHA ADDRESS A6 tSC tHC IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs A1 A2 A3 A4 A5 A7 A8 A9 CE 1, CE 2(2) tSB tHB B(A2) B(A4) B(A5) B(A8) Timing Waveform of Combined Read and Write Cycles(1,2,3) 15 6.42 tSD tHD D(A2) D(A4) D(A5) BW 1 - BW 4 OE D(A8) DATA In Write tCHZ tCLZ tCDC Write Write Write tCD DATA Out Q(A1) Read Q(A3) Q(A6) Read Q(A7) Read Read Commercial and Industrial Temperature Ranges 3822 drw 08 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. , tCYC CLK tSE tHE tCH tCL CEN tSADV tHADV ADV/LD tSW tHW R/W tSA tHA IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs ADDRESS A3 tSC tHC A1 A2 A4 A5 CE 1, CE 2(2) tSB tHB B(A2) Timing Waveform of CEN Operation(1,2,3,4) 16 tSD tHD D(A2) tCD tCHZ tCDC BW 1 - BW 4 OE DATA In tCD tCDC DATA Out Q(A1) Q(A1) Q(A3) Q(A4) tCLZ Commercial and Industrial Temperature Ranges NOTES: 3822 drw 09 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. , tCYC CLK tSE tHE tCH tCL C EN tHADV tSADV ADV/LD tSW tHW R/W tSA tHA IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs ADDRESS A3 A4 tSC tHC A1 A2 A5 Timing Waveform of CS Operation(1,2,3,4) 17 6.42 tSB tHB B(A3) tSD tHD D(A3) tCHZ tCDC CE 1, C E2(2) BW 1 - BW 4 OE DATA In tCD DATA Out Q(A1) Q(A2) Q(A4) Q(A4) tCLZ 3822 drw 10 . Commercial and Industrial Temperature Ranges NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation(1) OE tOE tOHZ tOLZ DATA Out Q Q 3822 drw 11 . NOTE: 1. A read operation is assumed to be in progress. Ordering Information IDT 71V547 Device Type S Power XX Speed PF Package X Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 80 85 90 100 Plastic Thin Quad Flatpack, 100 pin (PK100-1) Access time (tCD) in tenths of nanoseconds PART NUMBER 71V547S80PF 71V547S85PF 71V547S90PF 71V547S100PF tCD PARAMETER 8 ns 8.5 ns 9 ns 10 ns SPEED IN MEGAHERTZ 95 MHz 90 MHz 83 MHz 66 MHz CLOCK CYCLE TIME 10.5 ns 11 ns 12 ns 15 ns 3822 drw 12 18 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 6/15/99 9/13/99 12/31/99 Pg. 11 Pg. 19 Pp. 3, 11, 12, 18 Updated to new format Corrected ISB3 conditions Added Datasheet Document History Added Industrial Temperature range offerings CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: sramhelp@idt.com 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 19 6.42