IDT72V73273

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS IDT72V73273 FEATURES: • • • • • • • • • • • • • • • • • • • Up to 64 serial input and output streams Maximum 32,768 x 32,768 channel non-blocking switching Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s Rate matching capability: rate selectable on both RX and TX in eight groups of 8 streams Optional Output Enable Indication Pins for external driver High-Z control Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode for frame integrity applications Enhanced Block programming capabilities TX/RX Internal Bypass Automatic identification of ST-BUS and GCI serial streams Per-stream frame delay offset programming Per-channel High-Impedance output control Per-channel processor mode to allow microprocessor writes to TX streams Bit Error Rate Testing (BERT) for testing Direct microprocessor access to all internal memories Selectable Synchronous and Asynchronous microprocessor bus timing modes IEEE-1149.1 (JTAG) Test Port Available in 208-pin (28mm x 28mm) Plastic Quad Flatpack (PQFP) and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA) Operating Temperature Range -40°C to +85°C DESCRIPTION: The IDT72V73273 has a non-blocking switch capacity of 32,768 x 32,768 channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per stream control, and a variety of operating modes the IDT72V73273 is designed for the TDM time slot interchange function in either voice or data applications. Some of the main features of the IDT72V73273 are LOW power 3.3 Volt operation, automatic ST-BUS® /GCI sensing, memory block programming, simple microprocessor interface , JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode, BER testing, bypass mode, and advanced block programming. FUNCTIONAL BLOCK DIAGRAM VCC GND RESET ODE RX0-7 RX8-15 RX16-23 RX24-31 RX32-39 RX40-47 RX48-55 RX56-63 TX0-TX7 Data Memory MUX TX8-15/OEI0-7 TX16-23 Receive Serial Data Streams Internal Registers Connection Memory Transmit Serial Data Streams TX24-31/OEI16-23 TX32-39 TX40-47/OEI32-39 TX48-55 TX56-63/OEI48-55 Timing Unit Microprocessor Interface JTAG Port C32i F32i S/A DS CS R/W A0-A15 BEL DTA/ D0-D15 BEH TMS TDI TCK TDO TRST 6140 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. OCTOBER 2003 DSC-6140/3 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATIONS D1 D0 RX63 RX62 RX61 RX60 RX59 RX58 RX57 RX56 TX63/OEI55 TX62/OEI54 TX61/OEI53 TX60/OEI52 VCC GND TX59/OEI51 TX58/OEI50 TX57/OEI49 TX56/OEI48 VCC GND TX55 TX54 TX53 TX52 VCC GND TX51 TX50 TX49 TX48 RX55 RX54 RX53 RX52 RX51 RX50 RX49 RX48 RX47 RX46 RX45 RX44 RX43 RX42 RX41 RX40 TX47/OEI39 TX46/OEI38 TX45/OEI37 TX44/OEI36 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 GND C32i F32i Vcc S/A(1) TMS TDI TDO TCK TRST DS CS R/W VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BEL DTA/BEH D15 D14 D13 D12 VCC GND D11 D10 D9 D8 VCC GND D7 D6 D5 D4 VCC GND D3 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 • RESET ODE RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 TX0 TX1 TX2 TX3 VCC GND TX4 TX5 TX6 TX7 VCC GND TX8/OEI0 TX9/OEI1 TX10/OEI2 TX11/OEI3 VCC GND TX12/OEI4 TX13/OEI5 TX14/OEI6 TX15/OEI7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 TX16 TX17 TX18 TX19 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PIN 1 VCC GND TX20 TX21 TX22 TX23 VCC GND TX24/OEI16 TX25/OEI17 TX26/OEI18 TX27/OEI19 VCC GND TX28/OEI20 TX29/OEI21 TX30/OEI22 TX31/OEI23 RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 RX32 RX33 RX34 RX35 RX36 RX37 RX38 RX39 TX32 TX33 TX34 TX35 GND VCC TX36 TX37 TX38 TX39 GND VCC TX40/OEI32 TX41/OEI33 TX42/OEI34 TX43/OEI35 GND VCC 6140 drw02 NOTES: 1. S/A should be tied directly to VCC or GND for proper operation. PQFP: 0.50mm pitch, (28mm x 28mm) (DR208-1 order code: DR) TOP VIEW 2 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER A C32i RESET ODE RX1 RX4 TX0 TX4 TX7 TX12/ OEI4 TX11/ OEI3 TX10/ OEI2 VCC TX15/ OEI7 TX14/ OEI6 TX13/ OEI5 VCC RX11 RX15 RX20 TX16 TX18 TX19 B F32i Vcc RX0 RX2 RX5 TX1 TX5 TX8/ OEI0 TX9/ OEI1 VCC RX10 RX14 RX19 RX23 TX17 TX20 C S/A(1) TMS TDI RX3 RX6 TX2 TX6 RX9 RX13 RX18 RX22 TX22 TX21 D TDO TCK TRST DS RX7 TX3 VCC RX8 RX12 RX17 RX21 TX24/ OEI16 TX26/ OEI18 TX29/ OEI21 RX25 TX23 E CS R/W A0 A1 RX16 TX27/ OEI19 TX30/ OEI22 RX26 TX25/ OEI17 TX28/ OEI20 RX24 F A2 A3 A4 A5 TX31/ OEI23 GND GND GND GND VCC G A6 A7 A8 VCC H A9 A10 A11 VCC GND GND GND GND VCC RX29 RX28 RX27 J A14 A13 A12 VCC GND GND GND GND VCC RX30 RX31 RX32 K D15 DTA/ BEH D13 A15 VCC GND GND GND GND VCC RX33 RX34 RX35 L D12 D14 BEL RX36 RX37 RX38 RX39 M D8 D9 D10 D11 TX32 TX33 TX34 TX35 N D5 D6 D7 RX56 TX60/ OEI52 TX61/ OEI53 TX62/ OEI54 TX63/ OEI55 TX56/ OEI48 TX57/ OEI49 TX58/ OEI50 TX59/ OEI51 VCC VCC VCC VCC RX51 RX47 TX36 TX37 TX38 TX39 P D3 D4 RX60 RX57 TX53 TX50 TX49 RX54 RX50 RX46 RX43 TX40/ OEI32 RX40 TX41/ OE33 TX46/ OEI38 TX45/ OEI37 TX42/ OEI34 TX43/ OEI35 TX44/ OEI36 R D2 RX63 RX61 RX58 TX54 TX51 TX48 RX53 RX49 RX45 RX42 T D1 D0 RX62 RX59 TX55 TX52 RX55 RX52 RX48 RX44 RX41 TX47/ OEI39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6140 drw03 NOTES: 1. S/A should be tied directly to Vcc or GND for proper operation. PBGA: 1mm pitch, 17mm x 17mm (BB208-1 order code: BB) TOP VIEW 3 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL NAME I/O PQFP PIN NO. A0-A15 BEL C32i CS D0-15 DS DTA/BEH Address 0-15 Byte Enable LOW Clock Chip Select Data Bus 0-15 Data Strobe Data Transfer Acknowledgment Active LOW Output /Byte Enable HIGH I I I I I/O I I/O *See PQFP Table Below 31 2 12 *See PQFP Table Below 11 32 PBGA PIN NO. *See PBGA Table Below L4 A1 E1 *See PBGA Table Below D4 K2 These address lines access all internal memories. In synchronous mode, this input will enable the lower byte (D0-7) on to the data bus. Serial clock for shifting data in/out on the serial data streams. This input accepts a 32.768MHz clock. Active LOW input used by a microprocessor to activate the microprocessor port of the device. These pins are the data bus of the microprocessor port. This active LOW input works in conjunction with CS to enable the read and write operations. This active LOW input sets the data bus lines (D0-D15). In asynchronous mode this pin indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then High-Z allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is High-Z. When the device is in synchronous bus mode, this pin acts as an input and will enable the upper byte (D8-15) on to the data bus. This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications. Ground. This is the output enable control for the TX serial outputs. When ODE input is LOW and the OSB bit of the CR register is LOW, all TX outputs are in a HighImpedance state. If this input is HIGH, the TX output drivers are enabled. However, each channel may still be put into a High-Impedance state by using the per channel control bits in the Connection Memory HIGH. Serial data Input Stream. These streams may have data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the selection in Receive Data Rate Selection Register (RDRSR). This input (active LOW) puts the device in its reset state that clears the device internal counters, registers and brings TX0-63 and microport data outputs to a High-Impedance state. The RESET pin must be held LOW for a minimum of 20ns to reset the device. This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. This input will select between asynchronous microprocessor bus timing and synchronous microprocessor bus timing. In synchronous mode, DTA/BEH acts as the BEH input and is used in conjunction with BEL to output data on the data bus. In asynchronous bus mode, BEL is tied LOW and DTA/BEH acts as the DTA, data bus acknowledgment output. Provides the clock to the JTAG test logic. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held i in High-Impedance state when JTAG scan is not enabled. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. Asynchronously initializes the JTAG TAP controller by putting it in the TestLogic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the device DESCRIPTION F32i GND ODE Frame Pulse I 3 *See PQFP Table Below B1 *See PBGA Table Below A3 Output Drive Enable I 207 RX0-63 RX Input 0 to 63 I *See PQFP Table Below 208 *See PBGA Table Below A2 RESET Device Reset: I R/W S/ A Read/Write Synchronous/ Asynchronous Bus Mode I I 13 5 E2 C1 TCK TDI TDO TMS TRST Test Clock Test Serial Data In Test Serial Data Out Test Mode Select Test Reset I I O I I 9 7 8 6 10 D2 C3 D1 C2 D3 4 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION (CONTINUED) SYMBOL TX0-7 TX16-23 TX32-39 TX48-55 NAME TX Output I/O O PQFP PIN NO. *See PQFP Table Below PBGA PIN NO. *See PBGA Serial Data Output Stream. These streams may have data rates of 2.048Mb/s, Table Below 4.096Mb/s, 8.192Mb/s,16.384Mb/s, or 32.768Mb/s depending upon the selection in Transmit Data Rate Selection Register (TDRSR). *See PBGA When output streams are selected via TDRSR, these pins are the TX output Table Below streams. When output enable indication function is selected, these pins reflect the active or High-Impedance status for the corresponding TX output stream. *See PBGA +3.3 Volt Power Supply.is in the normal functional mode. Table Below DESCRIPTION TX8-15/OEI0-7 TX Output /Output Enable TX24-31/OEI16-23 Indication TX40-47/OEI32-39 TX56-63/OEI48-55 VCC O *See PQFP Table Below *See PQFP Table Below PQFP PIN NUMBER TABLE SYMBOL NAME I/O DESCRIPTION A0-A15 D0-D15 GND RX0-63 Address A0-A15 Data Bus 0-15 Ground RX Input 0 to 63 I I/O I 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30. 54, 53, 52, 51, 48, 47, 46, 45, 42, 41, 40, 39, 36, 35, 34, 33. 1, 38, 44, 50, 68, 74, 80, 106, 112, 118, 143, 149, 155, 181, 187, 193. 206, 205 , 204 , 203 , 202 , 201 , 200 , 199 , 198 , 175 , 174 , 173 , 172 , 171 , 170 , 169 , 168 , 167 ,166 , 165 , 164 , 163 , 162 , 161 , 138 , 137 , 136 , 135 , 134 , 133 , 132 , 131 , 130 ,129 , 128 , 127 , 126 , 125 , 124 , 123 , 100 , 99, 98 , 97 , 96 , 95 , 94 , 93 , 92 , 91 , 90 , 89 , 88 , 87 , 86 , 85, 62 , 61 , 60 , 59, 58 , 57 , 56 , 55 . 198, 197, 196, 195, 192, 191, 190, 189. 160, 159, 158, 157, 154, 153, 152, TX23=151. 122, 121, 120, 119, 116, 115, 114, 113. 84, 83, 82, 81, 78, 77, 76, 75. 186, 185, 184, 183, 180, 179,178, 177. 148, 147, 146, 145, 142, 141, 140, 139. 110, 109, 108, 107, 104, 103, 102, 101. 72, 71, 70, 69, 66, 65, 64, 63. 4, 14, 37, 43, 49, 67, 73, 79, 105, 111, 117, 144, 150, 156, 182, 188, 194. TX0-7 TX16-23 TX32-39 TX48-55 TX8-15/OEI0-7 TX24-31/OEI16-23 TX40-47/OEI32-39 TX56-63/OEI48-55 Vcc TX Output O TX Output/Output O PBGA PIN NUMBER TABLE SYMBOL NAME I/O DESCRIPTION A0-A15 D0-D15 GND RX0-63 Address A0-A15 Data Bus 0-15 Ground RX Input 0 to 63 I I/O I E3, E4, F1, F2, F3, F4, G1, G2, G3, H1, H2, H3, J3, J2, J1, K3. T2, T1, R1, P1, P2, N1, N2, N3, M1, M2, M3, M4, L1, L2, L3, K1. G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10. B3, A4 , B4 , C4 , A5 , B5 , C5 , D5 , D11 , C11 , B11 , A11 , D12 , C12 , B12 , A12 , E13 , D13 , C13 , B13 , A13 , D14 , C14 , B14 , G16 , G15, G14 , H16 , H15 , H14 , J14 , J15 , J16 , K14 , K15 , K16 , L13, L14 , L15 , L16 , R14 , T13, R13 , P13 , T12 , R12 , P12 , N12 , T11 , R11 , P11 , N11 , T10 , R10 , P10 , T9, N4 , P4 , R4 , T4, P3 , R3 , T3 , R2 . A6, B6, ,C6 D6, A7, B7, C7, A8. A14, B15, A15, A16, B16, C16, C15, D16. M13, M14, M15, M16, N13, N14, N15, N16. R9, P9, P8, R8, T8, P7, R7, T7. B8, C8, C9, B9, A9, C10, B10, A10. D15, E16, E15, E14, F16, F15, F14, F13. P14, P15, P16, R16, T16, T15, R15, T14. N6, P6, R6, T6, N5, P5, R5, T5. B2, D7, D8, D9, D10, G4, G13, H4, H13, J4, J13, K4, K13, N7, N8, N9, N10. 5 TX0-7 TX16-23 TX32-39 TX48-55 TX8-15/OEI0-7 TX24-31/OEI16-23 TX40-47/OEI32-39 TX56-63/OEI48-55 Vcc TX Output O TX Output/Output O IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED): The IDT72V73273 is capable of switching up to 32,768 x 32,768 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per-channel basis. The 64 serial input streams (RX) of the IDT72V73273 can be run at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s allowing 32, 64, 128, 256 or 512 channels per 125µs frame. The data rates on the output streams can independently be programmed to run at any of these data rates. With two main operating modes, Processor Mode and Connection Mode, the IDT72V73273 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor via Connection Memory. As control and status information is critical in data transmission, the Processor Mode is especially useful when there are multiple devices sharing the input and output streams. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V73273 has a Frame Offset feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +7.5 clock cycles. The IDT72V73273 also provides a JTAG test access port, memory block programming, Group Block Programming, RX/TX internal bypass, a simple microprocessor interface and automatic ST-BUS /GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. MOD2-0 bits are set to 0-0-1 accordingly, that particular channel will be in Constant Delay Mode. Finally, if the MOD2-0 bits are set to 0-0-0, that particular channel will be in Variable Delay Mode. SERIAL DATA INTERFACE TIMING The master clock frequency of the IDT72V73273 is 32.768MHz, C32i. For 32.768Mb/s data rates, this results in a single-bit per clock. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s this will result in two, four, eight, and sixteen clocks per bit, respectively. The IDT72V73273 provides two different interface timing modes, ST-BUS or GCI. The IDT72V73273 automatically detects the polarity of an input frame pulse and identifies it as either ST-BUS or GCI. For 32.768Mb/s, in ST-BUS Mode, data is clocked out on a falling edge and is clocked in on the subsequent rising-edge. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s however there is not the typical associated clock since the IDT72V73273 accepts only a 32.768MHz clock. As a result there will be 2, 4, 8, and 16 clock between the 32.768Mb/s transmit edge and the subsequently transmit edges. Although in this is the case, the IDT72V73273 will appropriately transmit and sample on the proper edge as if the respective clock were present. See ST-BUS Timing for detail. For 32.768Mb/s, in GCI Mode, data is clocked out on a rising edge and is clocked in on the subsequent falling-edge. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s however, again there is not the typical associated clock since the IDT72V73273 accepts only a 32.768MHz clock. As a result there will 2, 4, 8, and 16 clocks between the 32.768Mb/s transmit edge and the other transmit edges. Although this is the case, the IDT72V73273 will appropriately transmit and sample on the proper edge as if the respective clock were present. See GCI Bus Timing for detail. FUNCTIONAL DESCRIPTION DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8 KHz frame pulse (F32i) is used to mark the 125µs frame boundaries and to sequentially address the input channels in Data Memory. Data output on the TX streams may come from either the serial input streams (Data Memory) or from the Connection Memory via the microprocessor or in the case that RX input data is to be output, the addresses in Connection Memory are used to specify a stream and channel of the input. The Connection Memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor Mode, the microprocessor writes data to the Connection Memory locations corresponding to the stream and channel that is to be output. The lower half (8 least significant bits) of the Connection Memory LOW is output every frame until the microprocessor changes the data or mode of the channels. By using this Processor Mode capability, the microprocessor can access input and output time-slots on a per-channel basis. The three least significant bits of the Connection Memory HIGH are used to control per-channel mode of the output streams. The MOD2-0 bits are used to select Processor Mode, Constant or Variable Delay Mode, Bit Error Rate, and the High-Impedance state of output drivers. If the MOD2-0 bits are set to 1-1-1 accordingly, only that particular output channel (8 bits) will be in the HighImpedance state. If the MOD2-0 bits are set to 1-0-0 accordingly, that particular channel will be in Processor Mode. If the MOD2-0 bits are set to 1-0-1 a Bit Error Rate Test pattern will be transmitted for that time slot. See BERT section. If the DELAY THROUGH THE IDT72V73273 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the MOD bits of the Connection Memory. VARIABLE DELAY MODE (MOD2-0 = 0-0-0) In this mode, mostly for voice applications where minimum throughput delay is desired, delay is dependent on the combination of source and destination channels. The minimum delay achievable is a 3 channel periods of the slower data rate . CONSTANT DELAY MODE (MOD2-0 = 0-0-1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V73273, the minimum throughput delay achievable in Constant Delay mode will be one frame plus one channel. See Table 14. 6 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE MICROPROCESSOR INTERFACE The IDT72V73273’s microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 16-bit address bus and a 16-bit data bus all memories can be accessed. Using the TSI microprocessor interface, reads and writes are mapped into Data and Connection memories. By allowing the internal memories to be randomly accessed, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 1 shows the mapping of the addresses into internal memory blocks. In order to minimize the amount of memory mapped space however, the Memory Select (MS1-0) bits in the Control Register must be written to first to select between the Connection Memory HIGH, the Connection Memory LOW, or Data Memory. Effectively, the Memory Select bits act as an internal mux to select between the Data Memory, Connection Memory HIGH, and Connection Memory LOW. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V73273. The most significant bit of the address select between the registers and internal memories. See Table 1 for mappings. As explained in the initialization sections, after system power-up, the TDRSR and RDRSR, should be programmed immediately to establish the desired switching configuration. The data in the Control Register consists of the Software Reset, RX/TX Bypass, Output Enable Polarity, All Output Enable, Full Block Programming, Block Programming Data, Begin Block Programming Enable, Reset Connection Memory LOW in Block Programming, Output Standby, and Memory Select. SOFTWARE RESET The Software Reset serves the same function as the hardware reset. As with the hard reset, the Software Reset must also be set HIGH for 20ns before bringing the Software Reset LOW again for normal operation. Once the Software Reset is LOW, internal registers and other memories may be read or written. During Software Reset, the microprocessor port is still able to read from all internal memories. The only write operation allowed during a Software Reset is to the Software Reset bit in the Control Register to complete the Software Reset. CONNECTION MEMORY CONTROL If the ODE pin and the Output Standby bit are LOW, all output channels will be in three-state. See Table 2 for detail. If MOD2-0 of the Connection Memory HIGH is 1-0-0 accordingly, the output channel will be in Processor Mode. In this case the lower eight bits of the Connection Memory LOW are output each frame until the MOD2-0 bits are changed. If MOD2-0 of the Connection Memory HIGH are 0-0-1 accordingly, the channel will be in Constant Delay Mode and bits 14-0 are used to address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are 0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are 1-1-1, the channel will be in High-Impedance mode and that channel will be in three-state. RX/TX INTERNAL BYPASS When the Bypass bit of control registers is 1, all RX streams will be “shorted” to TX in effect bypassing all internal circuitry of the TSI. This effectively sets the TSI to a 1-to-1 switch mode with minimal I/O delay. A zero can be written to allow normal operation. The intention of this mode is to minimize the delay from the RX input to the TX output making the TSI “invisible”. INITIALIZATION OF THE IDT72V73273 After power up, the state of the Connection Memory is unknown. As such, the outputs should be put in High-Impedance by holding the ODE pin LOW. While the ODE is LOW, the microprocessor can initialize the device by using the Block Programming feature and program the active paths via the microprocessor bus. Once the device is configured, the ODE pin (or Output Standby bit depending on initialization) can be switched to enable the TSI switch. 7 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE TABLE 1 — ADDRESS MAPPING A15 1 A14 A13 A12 A11 A10 A9 A8 CH8 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W Location Hex Value STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Internal 0x8000memory 0xFFFF (CM, DM (read only)(1) Control TDRSR0 TDRSR1 RDRSR0 RDRSR1 BPSA BPEA BIS BER FOR0 FOR1 FOR2 FOR3 FOR4 FOR5 FOR6 FOR7 FOR8 FOR9 FOR10 FOR11 FOR12 FOR13 FOR14 FOR15 0x00XX Register 0x02XX 0x04XX 0x06XX 0x08XX 0x0AXX 0x0CXX 0x0EXX 0x10XX 0x20XX 0x22XX 0x24XX 0x26XX 0x28XX 0x2AXX 0x2CXX 0x2EXX 0x30XX 0x32XX 0x34XX 0x36XX 0x38XX 0x3AXX 0x3CXX 0x3EXX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NOTE: 1) Select Connection Memory High, Connection Memory Low, or Data Memory by setting the MS1-0 bits in the Control Register. TABLE 2  OUTPUT HIGH-IMPEDANCE CONTROL MOD2-0 BITS IN CONNECTION MEMORY HIGH 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 NOTE: X = Don't Care. OE X BIT OF TDRSR CONTROL REGISTER 1 1 1 1 1 0 ODE PIN OSB BIT IN OUTPUT DRIVER STATUS CONTROL REGISTER Per Channel High-Impedance All TX in High-Impedance Enable Enable Enable Group x of OEx is in High-Impedance X 0 0 1 1 X X 0 1 0 1 X 8 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE TABLE 3  CONTROL REGISTER (CR) BITS Reset Value: 15 SRS 14 BYP 0000H 13 OEPOL 12 AOE 11 PRST 10 CBER 9 SBER 8 FBP 7 BPD2 6 BPD1 5 BPD0 4 BPE 3 RCML 2 OSB 1 MS1 0 MS0 BIT 15 14 NAME SRS (Software Reset) BYP (RX/TX Bypass) DESCRIPTION A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation. When the Bypass bit is 1, all RX streams will be “shorted” to TX -- in effect bypassing all internal circuitry of the TSI. This effectively sets the TSI to a 1-to-1 switch mode with almost only a few nanoseconds of delay. A zero can be written to allow normal operation. The intention of this mode is to minimize the delay from the RX input to the TX output making the TSI “invisible”. Any offset values in the FOR register will be required. When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes High-Impedance state. When 0, a one denotes High-Impedance and a zero denotes an active state. OEI mode is entered on a per-group basis in the DRSR. When 1, all output stream pin (TXn) become OEI to allow for a two-chip solution for a larger switching matrix with OEI pins. When in AOE the DRS must be set to the corresponding data rates of the other device. When HIGH, the PRBS transmitter output will be initialized. A low to high transition of this bit clears the BER register (BERR). A low to high transition in this bit starts the bit error rate test. The bit error test result is kept in the BER register (BERR). When 1, this bit overrides the BPSA and BPEA registers and programs the full Connection Memory space. When 0, the BPSA and BPEA determine the Connection Memory space to be programmed. 13 OEPOL (Output Enable Polarity) AOE (All Output Enable) PRST (PRBS Reset) CBER (Clear Bit Error Rate) SBER (Start Bit Error Rate) FBP (Full Block Programming) 12 11 10 9 8 7-5 BPD2-0 These bits carry the value to be loaded into the Connection Memory block whenever the Connection Memory block programming (Block Programming Data) feature is activated. After the BPE bit is set to 1 from 0, the contents of the bits BPD2-0 are loaded into bit 2, 1 and 0 (MOD2-0) of the Connection Memory HIGH. BPE (Begin Block Programming Enable) A zero to one transition of this bit enables the Connection Memory block programming feature delimited by the BPSA and BPEA registers as well as for a full back program. Once the BPE bit is set HIGH, the device will program the Connection Memory block as fast as than if the user manually programmed each Connection Memory location through the microprocessor. After the programming function has finished, the BPE bit returns to zero to indicate the operation has completed. When the BPE = 1, the BPE bit can be set to 0 to abort block programming. When RCML =1, all bits 14-0 in Connection Memory LOW will be reset to zero during block programming; when RCML=0, bits 14-0 in Connection Memory LOW will retain their original values during block programming. ` When ODE = 0 and OSB = 0, the output drivers of transmit serial streams are in High-Impedance mode. When either ODE = 1 or OSB = 1, the output serial stream drivers function normally. These two bits decide which memory to be accessed via microprocessor port. 00 -- Connection Memory LOW 01 -- Connection Memory HIGH 10 -- Data Memory 11 -- Reserved 4 3 RCML (Reset Connection Memory LOW in Block Programming) OSB (Output Standby) MS1-0 (Memory Select) 2 1-0 9 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE MEMORY BLOCK PROGRAMMING The IDT72V73273 provides users with the capability of initializing the entire Connection Memory block in two frames. To set bits 2,1 and 0 of every Connection Memory HIGH location, set the Full Block Program to 1, write the desired pattern in to the Block Programming Data Bits (BPD2-0), and enable the Block Program Enable bit. All of the block programming control can be found in the Control Register. The block programming mode is enabled by setting the Block Program Enable bit of the Control Register HIGH. When the Block Programming Enable bit of the Control Register is set to HIGH, the Block Programming data will be loaded into the bits 2,1 and 0 of every Connection Memory HIGH location regardless of the selected data rate for the group. The Connection Memory LOW bits will be loaded with zeros when the Reset Connection Memory LOW(RCML) bit is enabled and is otherwise left untouched. When the memory block programming is complete, the device resets the Block Programming Enable and the BPD2-0 bits to zero. The IDT72V73273 also incorporates a feature termed Group Block Programming. Group Block Programming, allows subsections of the Connection Memory to be block programmed as if the microprocessor were accessing the Connection Memory HIGH locations back-to-back fashion. This results in one Connection Memory High location being programmed for each 32i clock cycle. By having the TSI perform this function it allows the controlling microprocessor more time to perform other functions. Also, the TSI can be more efficient in programming the locations since one CMH location is programmed every 32i clock cycle. The Group Block Programming function programs "Channel n" for all streams deliniated by the group before going to "Channel n+1". A C-code representation is shown below. The Group Block Programming feature is composed of the Block Programming Start Address(BPSA), the Block Programming End Address(BPEA), and the BPE and BPD bits in the Control Register. The BPSA contains a start address for the block programming and BPEA contains an end address. The block programming will start at the start address and program until the end address even if the end address is “less” than the start address. In other words there is no mechanism to prevent a start address that is larger than the end address. If this occurs, the inverse CM locations in the given group are programmed resulting in a “wrap around” effect. This “wrap around” effect is independent for both the stream and channel addresses. This is illustrated in the Group Block Programming diagram see Figure 1 Group Block Programming. Users must not initiate a block program too close (ahead) of the present transmit locations. If this is done the TSI may simultaneously access the CM location that is being modified and unpredictable data on TX outputs may occur. Users should take care when using the group block programming feature. Users must not initiate a block program too close (ahead) of the present transmit location. If this is done the TSI may simultaneously access the CM location that is being modified and unpredictable data on TX outputs may occur. It should be noted however, in order to enable the Group Block Programming the Full Block Program (FBP) must be 0. 10 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE TABLE 4  BLOCK PROGRAMMING STARTING ADDRESS (BPSA) REGISTER Reset Value: 15 0 14 G2 0000H 13 G1 12 G0 11 STA2 10 STA1 9 STA0 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 BIT 15 14-12 NAME Unused G2-0 (Group Address bits 2-0) STA2-0 (Stream Address bits 2-0) CHA8-0 (Channel Address bits 8-0) DESCRIPTION Must be zero for normal operation. These bits are used to select which group will be block programmed 11-9 These bits are used to select starting stream number for block programming. 8-0 These bits are used to select starting channel number for block programming. TABLE 5  BLOCK PROGRAMMING ENDING ADDRESS (BPEA) REGISTER Reset Value: 15 1 14 1 FFFFH 13 1 12 1 11 STA2 10 STA1 9 STA0 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 BIT 15-12 11-9 NAME Unused STA2-0 (Stream Address bits 2-0) CHA8-0 (Channel Address bits 8-0) DESCRIPTION Must be one for normal operation. These bits are used to select ending stream number for burst programming. 8-0 These bits are used to select starting channel number for burst programming. 11 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE CONNECTION MEMORY Channels CONNECTION MEMORY Channels 0,0 X X 255 0,0 X X 255 X Stream 2 X X X Stream 2 X Streams X X X Streams X X X X X X X X X X X Stream 4 X Stream 4 7 Channel 20 7 X Channel 123 BPSA = St2, Ch20 BPEA = St4, Ch 123 Channel 20 X Channel 123 BPSA = St4, Ch123 BPEA = St2, Ch20 0,0 X Channels X 255 0,0 X Channels X 255 X X X Stream 2 X Stream 2 X Streams X X X Streams X X X Stream 4 X X X X X X X X X Stream 4 7 Channel 20 7 X Channel 123 BPSA = ST4, CH20 BPEA = ST2, CH123 6140 drw04 Channel 20 X Channel 123 BPSA = ST2, CH123 BPEA = ST4, CH20 6140 drw04 NOTE: The group number is defined by the stream address in the BPSA. Figure 1. Group Block Programming 12 IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS INDUSTRIAL TEMPERATURE RANGE int ST, CH for (CH = StartChannel; CH