6ED003L06-F

Data sheet, Rev. 2.1, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Power Management & Drives Never stop thinking 6ED003L06-F Integrated 3 Phase Gate Driver 6ED003L06-F Revision History: Previous Version: Page 11 9 2009-07 2.0 Subjects (major changes since last revision) VIT Hys changed Corrected RthJA Fig3 Fig13 Rev. 2.1 Edition 2006-01 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 7/28/09. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Datasheet 2 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Table of Contents: 1 1.1 1.2 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 3 3.1 3.2 3.3 3.4 3.5 3.6 4 5 5.1 5.2 Overview ........................................................................................................................................4 Features ........................................................................................................................................ 4 Description ................................................................................................................................... 4 Pin Configuration and Description..............................................................................................5 Description ................................................................................................................................... 5 /HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 2, 3, 4, 5, 6, 7)................. 5 EN (Gate driver enable, Pin 10)................................................................................................... 6 /FAULT (Fault feedback, Pin 8) ................................................................................................... 6 ITRIP and RCIN (Over-current detection function, Pin 9, 11) .................................................. 6 VCC, VSS and COM (Low side supply, Pin 1, 12,13) ................................................................ 6 VB1,2,3 and VS1,2,3 (High side supplies, Pin 18, 20, 22, 24, 26, 28)....................................... 7 LO1,2,3 and HO1,2,3 (Low and High side outputs, Pin 14, 15, 16, 19, 23, 27)........................ 7 Electrical parameters....................................................................................................................9 Absolute Maximum Ratings ........................................................................................................ 9 Required Operation Conditions................................................................................................ 10 Operating Range ........................................................................................................................ 10 Static Logic function Table ....................................................................................................... 11 Static Parameters ....................................................................................................................... 11 Dynamic Parameters.................................................................................................................. 13 Timing Diagrams .........................................................................................................................14 Package........................................................................................................................................17 Package Drawing ....................................................................................................................... 17 Reference PCB for thermal resistance .................................................................................... 18 Datasheet 3 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 1 Overview 1.1 Features • Thin-film-SOI-technology • Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology • Maximum blocking voltage +600V • Power supply of the high side drivers via boot strap • Separate control circuits for all six drivers • CMOS and LSTTL compatible input (negative logic) • Signal interlocking of every phase to prevent cross-conduction • Detection of over-current and under-voltage supply • 'shut down' of all switches during error conditions • externally programmable delay for fault clear after over current detection 1.2 Description The device 6ED003L06-F is a full bridge driver to control power devices like MOS-transistors or IGBTs in 3phase systems with a maximum blocking voltage of +600V. Based on the used SOI-technology there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch up may occur at all temperature and voltage conditions. Figure 1: Typical Application The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down to 3.3V logic. The device includes an under-voltage detection unit with hysterese characteristic and an over-current detection. The over-current level is adjusted by choosing the resistor value and the threshold 5V / 3.3V VCC HIN1,2,3 LIN1,2,3 FAULT RRCIN EN CRCIN RCIN ITRIP VSS LO1,2,3 COM VCC HIN1,2,3 LIN1,2,3 FAULT EN VB1,2,3 HO1,2,3 To Load VS1,2,3 DC-Bus PG-DSO28-17 RNTC VSS level at pin ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut-down off all six switches. An error signal is provided at the FAULT open drain output pin. The blocking time after overcurrent can be adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore, the resistor RRCIN is optional. The minimum output current can be given with 120mA for pull-up and 250mA for pull down. Because of system safety reasons a 380ns interlocking time has been realised. The function of input EN can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1). There are parasitic diode structures between pins VCC and VBx due to the monolithic setup of the IC, but external bootstrap diodes are still mandatory. Datasheet 4 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 2 Pin Configuration and Description Figure 2: Pin Configuration of 6ED003L06-F Table 1: Pin Description Symbol VCC VSS /HIN1,2,3 /LIN1,2,3 /FAULT EN ITRIP RCIN COM VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 nc Description Low side power supply Logic ground High side logic input (negative logic) Low side logic input (negative logic) Indicates over-current and under-voltage (negative logic, open-drain output) Enable I/O functionality (positive logic) Analog input for over-current shutdown, activates FAULT and RCIN to VSS external RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR) Low side gate driver reference High side positive power supply High side gate driver output High side negative power supply Low side gate driver output Not Connected 2.1.1 /HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 2, 3, 4, 5, 6, 7) These pins are active low and they are responsible for HO1,2,3 and LO1,2,3 out-of-phase 5 Rev. 2, Dec 2008 2.1 Description Datasheet 6ED003L06-F Integrated 3 Phase Gate Driver commutation. The schmitt-trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. • Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the supply voltage condition returns in the normal operation range (please refer to VCC pin description for more details). • Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and RCIN input is released (please refer to ITRIP pin). ≈ 50Ω Figure 3: Input pin structure An internal pull-up resistor of about 75 kΩ is prebiases the input during supply start-up and a zener clamp is provided for pin protection purposes. Input schmitt-trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 4 and Figure 7. Figure 5: /Fault pin structure 2.1.4 ITRIP and RCIN (Over-current detection function, Pin 9, 11) 6ED003L06-F provides an over-current detection function by connecting the ITRIP input with the motor current feedback. The ITRIP comparator threshold (typ 0.46V) is referenced to VSS ground. A input noise filter (typ: tITRIPMIN = 210 ns) prevents the driver to detect false over-current events. Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 6.0V, the fault condition releases and the driver returns operational following /HIN and /LIN inputs. Please refer to AN-GateDriver-6ED003L06-1 for details on setting RCIN time constant. 2.1.5 VCC, VSS and COM (Low side supply, Pin 1, 12,13) VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is referenced to COM ground.COM ground is floating respect to VSS ground with a recommended range of operation of +/-2.5V. A back-to-back zener structure protects grounds from noise spikes. The under-voltage circuit enables the device to operate at power on when a typical supply voltage VCCUV+ = 12 V is present. 6 Rev. 2, Dec 2008 Figure 4: Input filter timing diagram It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1us. The 6ED003L06-F provides additionally an antishoot through prevention capability which avoids the simultaneous on-state of two gate drivers of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please refer to the application note AN-Gatedrive6ED003L06-1 for a detailed description. A minimum deadtime insertion of typ 380ns is also provided, in order to reduce cross-conduction of the external power switches. 2.1.2 EN (Gate driver enable, Pin 10) The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW logic level. The internal structure of the pin is the same as Figure 3 made exception of the switching levels of the Schmitt-Trigger, which are here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. 2.1.3 /FAULT (Fault feedback, Pin 8) /Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 3). The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur: Datasheet 6ED003L06-F Integrated 3 Phase Gate Driver The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 10.4 V. This prevents the external power switches from critically low gate voltage levels during on-state and therefore from excessive power dissipation. 2.1.6 VB1,2,3 and VS1,2,3 (High side supplies, Pin 18, 20, 22, 24, 26, 28) VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to VCC. Under-voltage detection operates with a rising supply threshold of typical VBSUV+ = 12 V and a falling threshold of VCCUV- = 10.4 V. Please refer to Figure 11 of the datasheet for device operating area as a function of the supply voltage. Details on bootstrap supply section and transient immunity can be found in application note ANGateDriver-6ED003L06-1. 2.1.7 LO1,2,3 and HO1,2,3 (Low and High side outputs, Pin 14, 15, 16, 19, 23, 27) Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs (/LIN1,2,3), while high side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs (/HIN1,2,3). In particular, after an under-voltage condition of the VBS supply, a falling /HIN edge is necessary to turn-on the respective high side output, while after a undervoltage condition of the VCC supply, the low side outputs switch to the state of their respective inputs. Datasheet 7 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver BIAS NETWORK / VDD2 HIN1 INPUT NOISE FILTER DEADTIME & SHOOT-THROUGH PREVENTION BIAS NETWORK - VB1 LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR UVDETECT GateDrive HO1 VB1 LIN1 INPUT NOISE FILTER VS1 HIN2 INPUT NOISE FILTER DEADTIME & SHOOT-THROUGH PREVENTION BIAS NETWORK - VB2 LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR UVDETECT GateDrive VB2 HO2 VS2 LIN2 INPUT NOISE FILTER HIN3 INPUT NOISE FILTER DEADTIME & SHOOT-THROUGH PREVENTION BIAS NETWORK / VB3 LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR UVDETECT GateDrive VB3 HO3 LIN3 INPUT NOISE FILTER >1 VS3 EN INPUT NOISE FILTER UVDETECT DELAY VSS / COM LEVELSHIFTER VSS / COM LEVELSHIFTER VSS / COM LEVELSHIFTER GateDrive V CC LO1 ITRIP INPUT NOISE FILTER DELAY VDD2 IRCIN GateDrive LO2 RCIN SET DOMINANT LATCH R S Q DELAY GateDrive LO3 COM FAULT >1 VSS Figure 6: Block diagram Datasheet 8 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 3 Electrical parameters 3.1 Absolute Maximum Ratings All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C) Symbol VS Definition High side offset voltage(Note 1) High side offset voltage (tp500ns external dead time>500ns PWin>1µs MTOFF - 90 150 PM 12 100 Note 1 : Because of internal signal processing and safety aspects the output HO at short turn off pulses shows the behaviour according to figure 4. For proper work of the driver the input pulses must not fall below the recommended input width tIN of 1µs. The short signal range is not subject to production test and is not guaranteed. Datasheet 13 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 4 Timing Diagrams tFILIN HIN LIN tFILIN LIN on off on off high LO tFILIN1 toff,HINx HIN toff,HINx < tFILIN1 high HO b) HIN toff,HINx toFILIN1 < toff,HINx < tFILIN2 HO c) HIN toff,HINx toff,HINx > tFILIN2 HO tFILIN2 HO LO low a) Figure 7: Timing of short pulse suppression Figure 8: Timing of internal deadtime Datasheet 14 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Figure 9: Enable delay time definition Figure 10: Input to output propagation delay times and switching times definition Figure 11: Operating Areas Datasheet 15 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Figure 12: ITRIP-timing Datasheet 16 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 5 Package 5.1 Package Drawing 0.2 -0.1 2.65 MAX. 0.35 x 45˚ 2.45 -0.2 1.27 0.35 +0.15 2) 0.1 0.2 28x 15 0.4 +0.8 10.3 ±0.3 28 1 Index Marking 1) 2) 18.1 -0.4 1) 14 Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.05 max. per side Footprint for Reflow soldering L e = 1.27 A = 9.73 L = 1.67 B = 0.65 B A HLG05506 Datasheet e 17 8˚ MAX. 7.6 -0.2 1) 0.23 +0.09 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 5.2 Reference PCB for thermal resistance Figure 13: PCB Reference layout Dimensions Material Metal (Copper) 80.0 × 80.0 × 1.5 mm³ FR4 70µm λtherm [W/m⋅K] 0.3 388 Datasheet 18 Rev. 2, Dec 2008