BTS7740G

TrilithIC Data Sheet 1 1.1 • • • • • • • • • • • • • • • Overview Features BTS 7740 G Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications Low RDS ON: 110 mτ high-side switch, 100 mτ lowside switch (typical values @ 25 C) Maximum peak current: typ. 8 A @ 25 C= Very low quiescent current: typ. 5 ←A @ 25 C= Small outline, enhanced power P-DSO-package Full short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Internal clamp diodes Isolated sources for external current sensing Under-voltage detection with hysteresis PWM frequencies up to 1 kHz Ordering Code Q67007-A9374 P-DSO-28-14 Type BTS 7740 G 1.2 Description Package P-DSO-28-14 The BTS 7740 G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 7740 G can be used in H-bridge- as well as in any other configuration. Both the double high-side and the two low-side switches of the BTS 7740 G are manufactured in SMART SIPMOS® technology which combines low RDS ON vertical DMOS power stages with CMOS control circuitry. The high-side switch is fully protected and contains the control and diagnosis circuitry. Also the low-side switches are fully protected, the equivalent standard product is the BSP 77. In contrast to the BTS 7750 G, which consists of lower ohmic chips in the same package, the BTS 7740 G offers a lower price for applications, which do not need the high current capability of the BTS 7750 G or BTS 7750 GP. Data Sheet 1 2001-02-01 BTS 7740 G 1.3 Pin Configuration (top view) DL1 1 IL1 2 DL1 3 LS-Leadframe N.C. 4 DHVS 5 GND 6 IH1 7 HS-Leadframe ST 8 IH2 9 DHVS 10 N.C. 11 LS-Leadframe DL2 12 IL2 13 DL2 14 28 DL1 27 SL1 26 SL1 25 DL1 24 DHVS 23 SH1 22 SH1 21 SH2 20 SH2 19 DHVS 18 DL2 17 SL2 16 SL2 15 DL2 Figure 1 Data Sheet 2 2001-02-01 BTS 7740 G 1.4 Pin No. Pin Definitions and Functions Symbol DL1 IL1 N.C. DHVS GND IH1 ST IH2 N.C. DL2 IL2 SL2 SH2 SH1 SL1 Function Drain of low-side switch1, leadframe 1 1) Analog input of low-side switch1 not connected Drain of high-side switches and power supply voltage, leadframe 2 1) Ground Digital input of high-side switch1 Status of high-side switches; open Drain output Digital input of high-side switch2 not connected Drain of low-side switch2, leadframe 3 1) Analog input of low-side switch2 Source of low-side switch2 Source of high-side switch2 Source of high-side switch1 Source of low-side switch1 1, 3, 25, 28 2 4 5, 10, 19, 24 6 7 8 9 11 12, 14, 15, 18 13 16,17 20,21 22,23 26,27 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Pins written in bold type need power wiring. Data Sheet 3 2001-02-01 BTS 7740 G 1.5 Functional Block Diagram DHVS 5,10,19,24 8 ST Diagnosis Biasing and Protection IH1 7 IH2 GND 9 Driver IN OUT 00LL 01LH 10HL 11HH RO1 RO2 20,21 12,14,15,18 SH2 DL2 6 22, 23 SH1 DL1 Protection 1,3,25,28 2 IL1 Gate Driver Protection 13 IL2 Gate Driver 26, 27 16, 17 SL1 SL2 Figure 2 Block Diagram Data Sheet 4 2001-02-01 BTS 7740 G 1.6 Circuit Description Input Circuit The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs IL1 and IL2 are connected to the internal gate-driving units of the N-channel vertical power-MOS-FETs. Output Stages The output stages consist of an low RDS ON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against – output short circuit to ground – output short circuit to the supply voltage, and – overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-VoltageDrop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. The fully protected low-side switches have no status output. Overtemperature Protection The high-side and the low-side switches also incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors. In the case of the highside switches, the status output is set to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF. Data Sheet 5 2001-02-01 BTS 7740 G Status Flag The status flag output is an open drain output with Zener-diode which requires a pull-up resistor, c.f. the application circuit on page 14. Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST to low. A open load detection is not available. Freewheeling condition does not cause an error. 2 Flag Truthtable and Diagnosis (valid only for the High-Side-Switches) IH1 0 0 1 1 0 1 X X 0 X 1 X IH2 0 1 0 1 X X 0 1 0 1 X X SH1 L L H H L L X X L L L L SH2 L H L H X X L L L L L L ST Remarks 1 1 1 1 1 0 1 0 1 0 0 1 stand-by mode switch2 active switch1 active both switches active detected detected detected detected not detected Inputs Normal operation; identical with functional truth table Outputs Overtemperature high-side switch1 Overtemperature high-side switch2 Overtemperature both high-side switches Undervoltage Inputs: 0 = Logic LOW 1 = Logic HIGH X = don’t care Outputs: Z = Output in tristate condition L = Output in sink condition H = Output in source condition X = Voltage level undefined Status: 1 = No error 0 = Error Data Sheet 6 2001-02-01 BTS 7740 G 3 3.1 Electrical Characteristics Absolute Maximum Ratings – 40 C < Tj < 150 C Symbol Limit Values min. max. Unit Remarks Parameter High-Side-Switches (Pins DHVS, IH1,2 and SH1,2) Supply voltage Supply voltage for full short circuit protection HS-drain current* HS-input current HS-input voltage Note: * single pulse Status Output ST Status pull up voltage Status Output current VS VS(SCP) IS IIH VIH – 0.3 42 28 V V A mA V – –7 –5 – 10 ** 5 16 TA = 25°C; tP < 100 ms Pin IH1 and IH2 Pin IH1 and IH2 ** internally limited VST IST – 0.3 –5 5.4 5 V mA Pin ST Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2) Drain-Source-Clamp voltage VDSL Supply voltage for short circuit protection LS-drain current* LS-input voltage Note: * single pulse Temperatures Junction temperature Storage temperature 42 – 30 20 –7 – 0.3 ** 10 V V V A V VDSL(SCP) IDL VIL VIL = 0 V; ID  1 mA VIL = 5 V VIL = 10 V TA = 25°C; tP < 100 ms – ** internally limited Tj Tstg – 40 – 55 150 150 C C – – Data Sheet 7 2001-02-01 BTS 7740 G 3.1 Absolute Maximum Ratings (cont’d) – 40 C < Tj < 150 C Symbol Limit Values min. max. Unit Remarks Parameter Thermal Resistances (one HS-LS-Path active) LS-junction case HS-junction case Junction ambient Rthja = Tj(HS)/(P(HS)+P(LS)) RthjC L RthjC H Rthja – – – 20 20 60 K/W measured to pin 3 or 12 K/W measured to pin 19 K/W device soldered to reference PCB with 6 cm2 cooling area ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/ ESD assn. standard S5.1 - 1993) Input LS-Switch Input HS-Switch Status HS-Switch Output LS and HS-Switch VESD VESD VESD VESD – – – – 2 1 2 8 kV kV kV kV all other pins connected to Ground Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.2 Operating Range – 40 C < Tj < 150 C Symbol Limit Values min. Supply voltage Input voltages Input voltages Output current Junction temperature max. V V V mA C After VS rising above VUVON – – – – Unit Remarks Parameter VS VIH VIL IST Tj VUVOFF 42 – 0.3 – 0.3 0 – 40 15 10 2 150 Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet 8 2001-02-01 BTS 7740 G 3.3 Electrical Characteristics ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. Current Consumption HS-switch Quiescent current typ. max. Unit Test Condition IS – – 5 – 1 2 – – 8 12 2 4 6 10 ←A ←A mA mA ←A mA IH1 = IH2 = 0 V Tj = 25 C IH1 = IH2 = 0 V IH1 or IH2 = 5 V VS = 12 V IH1 and IH2 = 5 V VS = 12 V Supply current IS – – Leakage current of highside switch Leakage current through logic GND in free wheeling condition ISH LK ILKCL = IFH + ISH – – VIH = VSH = 0 V IFH = 3 A Current Consumption LS-switch Input current IIL – – 8 160 2 30 300 10 ←A ←A ←A VIL = 5 V; normal operation VIL = 5 V; VIL = 0 V failure mode Leakage current of lowside IDL LK switch – Under Voltage Lockout (UVLO) HS-switch VUVON Switch-OFF voltage VUVOFF Switch ON/OFF hysteresis VUVHY Switch-ON voltage – 1.8 – – – 1 4.5 3.2 – V V V VS increasing VS decreasing VUVON – VUVOFF Data Sheet 9 2001-02-01 BTS 7740 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. Output stages Inverse diode of high-side switch; Forward-voltage Inverse diode of lowside switch; Forward-voltage Static drain-source on-resistance of highside switch Static drain-source on-resistance of lowside switch Static path on-resistance typ. max. Unit Test Condition VFH VFL RDS ON H – – – 0.8 0.8 110 1.2 1.2 140 V V mτ IFH = 3 A IFL = 3 A ISH = 1 A Tj = 25 C ISL = 1 A; VGL = 5 V Tj = 25 C RDS ON H + RDS ON L ISH = 1 A; RDS ON L – 100 120 mτ RDS ON – – 500 mτ Short Circuit of highside switch to GND Initial peak SC current ISCP H 8 7 5 9.5 8 6 11 9.5 7.5 A A A Tj = – 40 °C Tj = + 25 °C Tj = + 150 °C Short Circuit of highside switch to VS Output pull-down-resistor RO 12 22 50 kτ VDSL = 3 V Short Circuit of lowside switch to VS Initial peak SC current ISCP L 12 10 7 17 15 10 22 20 15 A A A Tj = – 40 C Tj = 25 C Tj = 150 C Data Sheet 10 2001-02-01 BTS 7740 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. Thermal Shutdown Thermal shutdown junction Tj SD temperature Thermal switch-on junction Tj SO temperature Temperature hysteresis αT 155 150 – 180 170 10 190 180 – C C C – – αT = TjSD – TjSO typ. max. Unit Test Condition Status Flag Output ST of highside switch Low output voltage Leakage current Zener-limit-voltage VST L IST LK VST Z – – 5.4 0.2 – 0.6 10 – V ←A V IST = 1.6 mA VST = 5 V IST = 1.6 mA Switching times of highside switch Turn-ON-time; to 90% VSH Turn-OFF-time; to 10% VSH tON tOFF – – – – 85 80 – – 180 180 1.1 1.5 ←s ←s RLoad = 12 τ VS = 12 V RLoad = 12 τ VS = 12 V Slew rate on 10 to 30% VSH dV/dtON Slew rate off 70 to 40% VSH -dV/ V/←s RLoad = 12 τ VS = 12 V V/←s RLoad = 12 τ VS = 12 V dtOFF Note: switching times are guaranteed by design Data Sheet 11 2001-02-01 BTS 7740 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. Switching times of lowside switch Turn-ON-time 70 to 50% VSHVIL = 0 to 10 V Turn-OFF-time; to 10% VSL typ. max. Unit Test Condition tON tOFF – – 70 40 – – 170 150 1.0 1.0 ←s ←s RLoad = 12 τ VS = 12 V RLoad = 12 τ VS = 12 V Slew rate on 70 to 50% VSH -dV/dtON – VIL = 0 to 10 V Slew rate off 50 to 70% VSH dV/dtOFF – VIL = 0 to 10 V V/←s RLoad = 12 τ VS = 12 V V/←s RLoad = 12 τ VS = 12 V Note: switching times are guaranteed by design Control Inputs of highside switches GH 1, 2 H-input voltage L-input voltage Input voltage hysterese H-input current L-input current Input series resistance Zener limit voltage Control Inputs GL1, 2 Gate-threshold-voltage VIH High VIH Low VIH HY IIH High IIH Low RI VIH Z – 1 – 15 5 2.7 5.4 – – 0.3 30 – 4 – 2.5 – – 60 20 5.5 – V V V ←A ←A kτ V – – – VIH = 5 V VIH = 0.4 V – IIH = 1.6 mA VIL th 0.9 1.7 2.2 V IDL = 2 mA Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Data Sheet 12 2001-02-01 BTS 7740 G IS VS=12V CS 470nF CL 100µF IFH1,2 DHVS IST LK IST ST 8 5,10,19,24 VDSH2 -VFH2 Diagnosis Biasing and Protection VDSH1 -VFH1 VST VSTL VSTZ IIH1 IH1 7 Gate Driver RO1 RO2 20,21 12,14,15,18 IIH1 VIH1 VIH2 SH2 DL2 ISH2 IDL2 IDL LK 2 VUVON VUVOFF IH2 GND IGND ILKCL 9 Gate Driver 6 22,23 SH1 DL1 ISH1 IDL1 IDL LK 1 Protection IIL1 IL1 2 1,3,25,28 Gate Driver Protection VIL1 VIL th 1 VIL2 VIL th 2 26,27 IIL2 IL2 13 Gate Driver 16,17 VDSL1 -VFL1 VDSL2 -VFL2 SL1 ISCP L 1 ISL1 SL2 ISCP L 2 ISL2 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during LeakageCond. ISH1,2 ISCP H IDL LK Data Sheet 13 2001-02-01 BTS 7740 G Watchdog Reset Q TLE 4278G D CD 47nF I VS=12V RQ 100 kτ CQ 22µF D01 Z39 CS 10µF WD R VCC DHVS 5,10,19,24 RS 10 kτ ST 8 Diagnosis Biasing and Protection IH1 7 Gate Driver RO1 RO2 20,21 12,14,15,18 SH2 DL2 IH2 GND µP 9 Gate Driver 6 22,23 SH1 DL1 M Protection IL1 1,3,25,28 2 Gate Driver Protection IL2 13 Gate Driver 26,27 16,17 GND SL1 SL2 In case of VDSL