SPP21N50C3

SPP21N50C3 SPI21N50C3, SPA21N50C3 Cool MOS™ Power Transistor Feature • New revolutionary high voltage technology • Worldwide best RDS(on) in TO 220 • Ultra low gate charge • Periodic avalanche rated • Extreme dv/dt rated • Ultra low effective capacitances • Improved transconductance 1 2 3 VDS @ Tjmax RDS(on) ID PG-TO220FP P G-TO262 560 0.19 21 PG-TO220 V Ω A Type SPP21N50C3 SPI21N50C3 SPA21N50C3 Package PG-TO220 PG-TO262 PG-TO220FP Ordering Code Q67040-S4565 Q67040-S4564 SP000216364 Marking 21N50C3 21N50C3 21N50C3 Maximum Ratings Parameter Continuous drain current TC = 25 °C TC = 100 °C Symbol SPP_I ID 21 13.1 ID puls EAS EAR IAR VGS VGS Ptot Tj , Tstg dv/dt Page 1 Value SPA Unit A 211) 13.11) 63 690 1 21 ±20 ±30 34.5 15 W °C V/ns A V A mJ Pulsed drain current, tp limited by Tjmax Avalanche energy, single pulse ID=10A, VDD=50V 63 690 1 21 ±20 ±30 208 Avalanche energy, repetitive tAR limited by Tjmax2) ID=21A, VDD=50V Avalanche current, repetitive tAR limited by Tjmax Gate source voltage Gate source voltage AC (f >1Hz) Power dissipation, TC = 25°C Operating and storage temperature Reverse diode dv/dt Rev. 3.0 7) -55...+150 2007-08-30 SPP21N50C3 SPI21N50C3, SPA21N50C3 Maximum Ratings Parameter Drain Source voltage slope VDS = 400 V, ID = 21 A, Tj = 125 °C Symbol dv/dt Value 50 Unit V/ns Thermal Characteristics Parameter Thermal resistance, junction - case Thermal resistance, junction - case, FullPAK Thermal resistance, junction - ambient, leaded Thermal resistance, junction - ambient, FullPAK SMD version, device on PCB: @ min. footprint @ 6 cm 2 cooling area 3) Soldering temperature, wavesoldering 1.6 mm (0.063 in.) from case for 10s 4) Electrical Characteristics, at Tj=25°C unless otherwise specified Parameter Symbol Conditions min. Drain-source breakdown voltage V(BR)DSS VGS=0V, ID=0.25mA Drain-Source avalanche breakdown voltage Gate threshold voltage Zero gate voltage drain current VGS(th) I DSS ID=1000µA, VGS=VDS VDS=500V, V GS=0V, Tj=25°C Tj=150°C Symbol min. RthJC RthJC_FP RthJA RthJA_FP RthJA Tsold - Values typ. 35 max. 0.6 3.6 62 80 62 260 Unit K/W °C Values typ. 600 3 0.1 0.16 0.54 0.53 max. 3.9 500 2.1 - Unit V V(BR)DS VGS=0V, ID=21A µA 1 100 100 0.19 nA Ω Gate-source leakage current I GSS VGS=20V, V DS=0V VGS=10V, ID=13.1A Tj=25°C Tj=150°C Drain-source on-state resistance RDS(on) Gate input resistance RG f=1MHz, open drain Rev. 3.0 Page 2 2007-08-30 SPP21N50C3 SPI21N50C3, SPA21N50C3 Electrical Characteristics Parameter Transconductance Input capacitance Output capacitance Reverse transfer capacitance energy related Effective output capacitance,6) Co(tr) time related Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Qgs Qgd Qg VDD=380V, ID=21A, VGS=0 to 10V VDD=380V, ID=21A Symbol gfs Ciss Coss Crss Conditions min. VDS≥2*ID*R DS(on)max, ID=13.1A VGS=0V, VDS=25V, f=1MHz Values typ. 18 2400 1200 30 87 181 10 5 67 4.5 max. - Unit S pF Effective output capacitance,5) Co(er) VGS=0V, VDS=400V td(on) tr td(off) tf VDD=380V, VGS=0/10V, ID=21A, RG =3.6Ω - ns - 10 50 95 5 - nC V(plateau) VDD=380V, ID=21A V 1Limited only by maximum temperature 2Repetitve avalanche causes additional power losses that can be calculated as P =E *f. AR AV 3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 4Soldering temperature for TO-263: 220°C, reflow 5C 6C o(er) o(tr) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 7I