250688-002

Mobile Intel Pentium 4 Processor-M Datasheet June 2003 Order Number: 250686-007 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers, and Intel's customers should not rely on any Intelprovided information as either an endorsement or recommendation of any particular system design characteristics. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com Copyright © Intel Corporation 2000-2003. Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners. 2 Mobile Intel Pentium 4 Processor-M Datasheet Contents 1. Introduction......................................................................................................................... 9 1.1 1.2 2. 2.1 2.2 2.3 Terminology......................................................................................................... 11 References .......................................................................................................... 11 System Bus and GTLREF ................................................................................... 13 Power and Ground Pins ...................................................................................... 13 Decoupling Guidelines ........................................................................................ 13 2.3.1 VCC Decoupling ..................................................................................... 14 2.3.2 System Bus AGTL+ Decoupling............................................................. 14 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................14 Voltage Identification and Power Sequencing..................................................... 15 2.4.1 Enhanced Intel® SpeedStep® Technology............................................ 16 2.4.2 Phase Lock Loop (PLL) Power and Filter............................................... 17 2.4.3 Catastrophic Thermal Protection............................................................ 18 Signal Terminations, Unused Pins and TESTHI[10:0] ........................................ 18 System Bus Signal Groups ................................................................................. 20 Asynchronous GTL+ Signals............................................................................... 22 Test Access Port (TAP) Connection.................................................................... 22 System Bus Frequency Select Signals (BSEL[1:0])............................................ 22 Maximum Ratings................................................................................................ 23 Processor DC Specifications............................................................................... 23 AGTL+ System Bus Specifications ..................................................................... 34 System Bus AC Specifications ............................................................................ 35 Processor AC Timing Waveforms ....................................................................... 40 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines ...........................................................................................................51 System Bus Signal Quality Specifications and Measurement Guidelines........... 52 System Bus Signal Quality Specifications and Measurement Guidelines........... 55 3.3.1 Overshoot/Undershoot Guidelines ......................................................... 55 3.3.2 Overshoot/Undershoot Magnitude ......................................................... 55 3.3.3 Overshoot/Undershoot Pulse Duration................................................... 55 3.3.4 Activity Factor......................................................................................... 56 3.3.5 Reading Overshoot/Undershoot Specification Tables............................ 56 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications .. 57 Processor Pin-Out ............................................................................................... 64 Mobile Intel Pentium 4 Processor-M Pin Assignments........................................ 67 Alphabetical Signals Reference .......................................................................... 81 Thermal Specifications ........................................................................................ 90 Electrical Specifications.................................................................................................... 13 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3. 3.1 3.2 3.3 System Bus Signal Quality Specifications........................................................................ 51 4. 5. Package Mechanical Specifications ................................................................................. 61 4.1 5.1 5.2 Pin Listing and Signal Definitions ..................................................................................... 67 6. Thermal Specifications and Design Considerations......................................................... 89 6.1 Mobile Intel Pentium 4 Processor-M Datasheet 3 Mobile Intel Pentium 4 Processor-M 6.1.1 6.1.2 7. 7.1 7.2 Thermal Diode........................................................................................ 90 Thermal Monitor ..................................................................................... 91 Configuration and Low Power Features........................................................................... 93 Power-On Configuration Options ........................................................................ 93 Clock Control and Low Power States.................................................................. 93 7.2.1 Normal State .......................................................................................... 93 7.2.2 AutoHALT Powerdown State ................................................................. 93 7.2.3 Stop-Grant State .................................................................................... 94 7.2.4 HALT/Grant Snoop State ....................................................................... 95 7.2.5 Sleep State............................................................................................. 95 7.2.6 Deep Sleep State ................................................................................... 95 7.2.7 Deeper Sleep State ................................................................................ 96 Enhanced Intel SpeedStep Technology .............................................................. 96 Logic Analyzer Interface (LAI) ............................................................................ 97 8.1.1 Mechanical Considerations .................................................................... 97 8.1.2 Electrical Considerations........................................................................ 97 7.3 8. 8.1 Debug Tools Specifications .............................................................................................. 97 4 Mobile Intel Pentium 4 Processor-M Datasheet Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VCCVID Pin Voltage and Current Requirements ................................................ 15 Typical VCCIOPLL, VCCA and VSSA Power Distribution .................................. 17 Phase Lock Loop (PLL) Filter Requirements ..................................................... 18 Illustration of VCC Static and Transient Tolerances (VID = 1.30 V).................... 26 Illustration of VCC Static and Transient Tolerances (VID = 1.20 V).................... 28 Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V) ................................................................................................. 29 ITPCLKOUT[1:0] Output Buffer Diagram ............................................................ 34 AC Test Circuit .................................................................................................... 41 TCK Clock Waveform.......................................................................................... 41 Differential Clock Waveform................................................................................ 42 Differential Clock Crosspoint Specification.......................................................... 43 System Bus Common Clock Valid Delay Timings............................................... 43 System Bus Reset and Configuration Timings....................................................44 Source Synchronous 2X (Address) Timings ....................................................... 44 Source Synchronous 4X Timings ........................................................................ 45 Power Up Sequence ........................................................................................... 46 Power Down Sequence....................................................................................... 46 Test Reset Timings ............................................................................................. 47 THERMTRIP# to Vcc Timing............................................................................... 47 FERR#/PBE# Valid Delay Timing ....................................................................... 47 TAP Valid Delay Timing ...................................................................................... 48 ITPCLKOUT Valid Delay Timing ......................................................................... 48 Stop Grant/Sleep/Deep Sleep Timing .................................................................49 Enhanced Intel SpeedStep Technology/Deep Sleep Timing .............................. 50 BCLK Signal Integrity Waveform......................................................................... 52 Low-to-High System Bus Receiver Ringback Tolerance..................................... 53 High-to-Low System Bus Receiver Ringback Tolerance..................................... 53 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................................................................................................................. 54 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................................................................................................................. 54 Maximum Acceptable Overshoot/Undershoot Waveform ................................... 59 Micro-FCPGA Package Top and Bottom Isometric Views .................................. 61 Micro-FCPGA Package Top and Side View........................................................ 62 Micro-FCPGA Package - Bottom View................................................................ 64 The Coordinates of the Processor Pins as Viewed From the Top of the Package. ............................................................................................................. 65 Clock Control States............................................................................................ 94 Mobile Intel Pentium 4 Processor-M Datasheet 5 Mobile Intel Pentium 4 Processor-M Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 References.......................................................................................................... 11 Core Frequency to System Bus Multipliers ......................................................... 14 Voltage Identification Definition........................................................................... 16 System Bus Pin Groups ...................................................................................... 21 BSEL[1:0] Frequency Table for BCLK[1:0] ......................................................... 22 Processor DC Absolute Maximum Ratings ......................................................... 23 Voltage and Current Specifications..................................................................... 24 IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)........................................................................... 25 IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode) ................................................................................... 27 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%) ..................................... 28 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%) .......................................................... 29 System Bus Differential BCLK Specifications ..................................................... 30 AGTL+ Signal Group DC Specifications ............................................................. 31 Asynchronous GTL+ Signal Group DC Specifications ........................................ 32 PWRGOOD and TAP Signal Group DC Specifications ...................................... 33 ITPCLKOUT[1:0] DC Specifications.................................................................... 33 BSEL [1:0] and VID[4:0] DC Specifications......................................................... 34 AGTL+ Bus Voltage Definitions........................................................................... 35 System Bus Differential Clock Specifications...................................................... 36 System Bus Common Clock AC Specifications .................................................. 36 System Bus Source Synch AC Specifications AGTL+ Signal Group .................. 37 Miscellaneous Signals AC Specifications ........................................................... 38 System Bus AC Specifications (Reset Conditions) ............................................. 38 TAP Signals AC Specifications ........................................................................... 39 ITPCLKOUT[1:0] AC Specifications .................................................................... 39 Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications ...................................................................................................... 40 BCLK Signal Quality Specifications .................................................................... 51 Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups.... 52 Ringback Specifications for PWRGOOD Input and TAP Signal Groups............. 53 Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 57 Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 58 Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 58 Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/Undershoot Tolerance ....................................................................... 59 Micro-FCPGA Package Dimensions ................................................................... 63 Pin Listing by Pin Name ...................................................................................... 68 Pin Listing by Pin Number ................................................................................... 74 Signal Description ............................................................................................... 81 Power Specifications for the Mobile Intel Pentium 4 Processor-M...................... 89 Thermal Diode Interface...................................................................................... 90 6 Mobile Intel Pentium 4 Processor-M Datasheet 40 41 Thermal Diode Specifications.............................................................................. 90 Power-On Configuration Option Pins .................................................................. 93 Mobile Intel Pentium 4 Processor-M Datasheet 7 Mobile Intel Pentium 4 Processor-M Revision History Date March 2002 April 2002 Revision 001 002 Initial release of the Datasheet Updates include: • • • • • June 2002 003 Added new processor speeds: 1.4 GHz, 1.5 GHz, & 1.8 GHz Added PROCHOT# signal in Table 21 Updated signal description for PROCHOT# in Table 37 and Section 6.1.2 Updated the description of the Enhanced Intel Speedstep Technology in sections 2.4.1 and 7.3 Updated PWRGOOD signal in Table 3, Section 2.7, Table 14, Table 21, Table 28, Table 35, Figure 28, and FIgure 29 Added specifications for new processor speeds: 1.90 GHz and 2 GHz Added die length and die width for processors based on B0-step shrink process in Table 33 Added 2.2 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Corrected STPCLK#/SLP# timing relationship in Section 7.2.3 to match parameter T75. Added 2.4 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Clarified DBI[3:0]# and THERMTRIP# descriptions in Table 37. Clarified thermal solution requirements in Section 6. Added 2.5 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Added 2.6 GHz Mobile Intel Pentium 4 Processor-M specifications. Updated note 5 in Table 22. Updated THERMTRIP# description in Table 37. Description Updates include: • • September 2002 004 Updates include: • • • January 2003 005 Updates include: • • • • April 2003 006 Updates include: • • June 2003 007 Updates include: • • • 8 Mobile Intel Pentium 4 Processor-M Datasheet Introduction 1. Introduction The Mobile Intel Pentium 4 Processor-M is the first Intel mobile processor with the Intel NetBurstTM micro-architecture. The Mobile Intel Pentium 4 Processor-M utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA32 software. In this document the Mobile Intel Pentium 4 Processor-M will be referred to as the “Mobile Intel Pentium 4 Processor-M” or simply “the processor.” The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid execution engine, a 400-MHz system bus, and an execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor-M allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main execution path, thereby increasing performance. Additional features within the Intel NetBurst micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2 (L2) cache. A new floating point and multi media unit has been implemented which provides superior performance for multi-media and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep have been incorporated. The processor includes an address bus powerdown capability which removes power from the address and data pins when the system bus is not in use. This feature is always enabled on the processor. The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Mobile Intel Pentium 4 Processor-M’s 400-MHz Intel NetBurst micro-architecture system bus utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 Processor. This system bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst microarchitecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second. The processor, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system. Mobile Intel Pentium 4 Processor-M Datasheet 9 Introduction The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology. The Mobile Intel Pentium 4 Processor-M is available at the following core frequencies: • 2.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.2 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.0 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.9 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.8 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.7 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 1.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) 10 Mobile Intel Pentium 4 Processor-M Datasheet Introduction 1.1 Terminology A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). “System Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The system bus is a multiprocessing interface to processors, memory, and I/O. Commonly used terms are explained here for clarification: • Processor — For this document, the term processor shall mean the Mobile Intel Pentium 4 Processor-M in the 478-pin package. • Keep out zone — The area on or near the processor that system design can not utilize. • Intel 845MP/845MZ chipsets — Mobile chipsets that will support the Mobile Intel Pentium 4 Processor-M. • Processor core — Mobile Intel Pentium 4 Processor-M core die with integrated L2 cache. • Micro-FCPGA package — Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch. 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Mobile Intel Pentium Platform Design Guide    4 Processor-M and Intel 845MP/845MZ Chipset Order Number 250688-002 Intel Architecture Software Developer's Manual Volume I: Basic Architecture Volume II: Instruction Set Reference Volume III: System Programming Guide 245470 245471 245472 Mobile Intel Pentium 4 Processor-M Datasheet 11 Introduction This page intentionally left blank. 12 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications 2. 2.1 Electrical Specifications System Bus and GTLREF Most Mobile Intel Pentium 4 Processor-M system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Mobile Intel Pentium 4 Processor-M AGTL+ signals is VCC, which is the operating voltage of the processor core. Previous generations of Intel mobile processors utilize a fixed termination voltage known as VCCT. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for Mobile Intel Pentium 4 Processor-M. Because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Design guidelines for the Mobile Intel Pentium 4 Processor-M system bus will be detailed in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/ 845MZ Chipset Platform Design Guide. The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). Intel’s 845MP/845MZ chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. However, some AGTL+ signals do not include on-die termination and must be terminated on the system board. For more information, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. 2.2 Power and Ground Pins For clean on-chip power distribution, the Mobile Intel Pentium 4 Processor-M have 85 VCC (power) and 181 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied with the voltage determined by the VID (Voltage ID) pins and the loadline specifications (see Figure 4 to Figure 6). 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations and/or Mobile Intel Pentium 4 Processor-M Datasheet 13 Electrical Specifications affect the long term reliability of the processor. For further information and design guidelines, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. 2.3.2 System Bus AGTL+ Decoupling The Mobile Intel Pentium 4 Processor-M integrates signal termination on the die and incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Mobile Intel Pentium 4 Processor-M core frequency is a multiple of the BCLK[1:0] frequency. Refer to Table 2 for the Mobile Intel Pentium 4 Processor-M supported ratios. Table 2. Core Frequency to System Bus Multipliers Core Frequency 800 MHz 1.2 GHz 1.4 GHz 1.5 GHz 1.6 GHz 1.7 GHz 1.8 GHz 1.9 GHz 2.0 GHz 2.2 GHz 2.4 GHz 2.5 GHz 2.6 GHz NOTES: 1. Ratio is used for debug purposes only. Multiplication of System Core Frequency to System Bus Frequency 1/8 1/12 1/14 1/15 1/16 1/17 1/18 1/19 1/20 1/22 1/24 1/25 1/26 Notes2 1 14 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications 2. Listed frequencies are not necessarily committed production frequencies. The Mobile Intel Pentium 4 Processor-M uses a differential clocking implementation. For more information on Mobile Intel Pentium 4 Processor-M clocking. 2.4 Voltage Identification and Power Sequencing The voltage set by the VID pins is the nominal/typical voltage setting for the processor. A minimum voltage is provided in Table 7 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies. The Mobile Intel Pentium 4 Processor-M uses five voltage identification pins, VID[4:0], to support automatic selection of power supply voltages. The VID pins for the Mobile Intel Pentium 4 Processor-M are open drain outputs driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A “1” in this table refers to a high-voltage level and a “0” refers to low-voltage level. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. Refer to the Figure 16 for timing details of the power up sequence. Also refer to Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for implementation details. Mobile Intel Pentium 4 Processor-M’s Voltage Identification circuit requires an independent 1.2-V supply. This voltage must be routed to the processor VCCVID pin. Figure 1 shows the voltage and current requirements of the VCCVID pin. Figure 1. VCCVID Pin Voltage and Current Requirements 1.2V+10% 1.2V-5% 1V 150mA to 300mA 80mA 30mA 1mA 70nS 5nS Mobile Intel Pentium 4 Processor-M Datasheet 15 Electrical Specifications Table 3. Voltage Identification Definition Processor Pins VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0.600 0.625 0.650 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 VCC_ 2.4.1 Enhanced Intel® SpeedStep® Technology The Mobile Intel Pentium 4 Processor-M, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Enhanced Intel SpeedStep technology allows the processor to switch between two core frequencies automatically based on CPU demand, without having to reset the processor or change the system bus frequency. The processor operates in two modes, the Maximum Performance mode or the Battery Optimized mode. Each frequency and voltage pair identifies the operating mode. The processor drives the VID[4:0] pins with the correct VID for the current operating mode. After reset, the processor will start in Battery Optimized mode. Any RESET# assertion will force the Mobile Intel Pentium 4 Processor-M Datasheet 16 Electrical Specifications processor to the Battery Optimized mode. INIT# assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of the processor. Some electrical and thermal specifications are for a specific voltage and frequency. The Mobile Intel Pentium 4 Processor-M featuring Enhanced Intel SpeedStep technology will meet the electrical and thermal specifications specific to the current operating mode, and it is not guaranteed to meet the electrical and thermal specifications specific to the opposite operating mode. The timing specifications must be met when performing an operating mode transition. 2.4.2 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Mobile Intel Pentium 4 Processor-M silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCCVID. A typical filter topology is shown in Figure 2. The AC low-pass requirements, with input at VCCVID and output measured across the capacitor (CA or CIO in Figure 2), is as follows: • • • • < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3. For recommendations on implementing the filter refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution V CCVID L VCCA CA PLL Processor Core VSSA C IO VCCIOPLL L Mobile Intel Pentium 4 Processor-M Datasheet 17 Electrical Specifications . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC passband 1 Hz fpeak 1 MHz 66 MHz fcore high frequency band NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.4.3 Catastrophic Thermal Protection The Mobile Intel Pentium 4 Processor-M supports the THERMTRIP# signal for catastrophic thermal protection. Alternatively an external thermal sensor can be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 135°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. Refer to Section 5.2 for more details on THERMTRIP#. 2.5 Signal Terminations, Unused Pins and TESTHI[10:0] All NC pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Mobile Intel Pentium 4 Processor-M. See Section 5.2 for a pin listing of the processor and the location of all NC pins. 18 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Mobile Intel Pentium 4 Processor-M to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for the appropriate resistor values. Unused outputs can be left unconnected, however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals that don’t have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (RTT). See Table 18. The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched resistor has a resistance value within + 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required. The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A matched resistor should be used for each group: 1. TESTHI[1:0] 2. TESTHI[5:2] 3. TESTHI[10:8] Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to VCC using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1-kΩ resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This implementation is strongly discouraged for system boards that do not implement an onboard debug port. As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI[0] may also be tied directly to processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged for system boards that do not implement an onboard debug port. Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing. Pullup/down resistor requirements for the VID[4:0] and BSEL[1:0] signals are included in the signal descriptions in Section 5. Mobile Intel Pentium 4 Processor-M Datasheet 19 Electrical Specifications 2.6 System Bus Signal Groups In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous. 20 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications Table 4. System Bus Pin Groups Signal Group AGTL+ Common Clock Input Type Common clock Synchronous Signals1 BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# AGTL+ Common Clock I/O Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Source Synchronous A[35:17]# 5 5 Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# AGTL+ Strobes Asynchronous GTL+ Input4,5 Asynchronous GTL+ Output4 TAP Input4 TAP Output4 System Bus Clock Common Clock Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK N/A ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPSLP#, GHI#, IGNNE#, INIT#5, LINT0/INTR, LINT1/NMI, SMI#5, SLP#, STPCLK# FERR#/PBE#, IERR#2, THERMTRIP#, PROCHOT# TCK, TDI, TMS, TRST# TDO BCLK[1:0], ITP_CLK[1:0]3 VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA, GTLREF[3:0], COMP[1:0], NC, TESTHI[5:0], TESTHI[10:8], ITPCLKOUT[1:0], PWRGOOD, THERMDA, THERMDC, SKTOCC#, VCC_SENSE, VSS_SENSE, BSEL[1:0], DBR#3 Power/Other N/A NOTES: 1. Refer to Section 5.2 for signal descriptions. 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements. 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must   be terminated on the system board. Refer to Section 2.5 and the Mobile Intel Pentium 4 Processor-M and  Intel 845MP/845MZ Chipset Platform Design Guide for termination requirements and further details. 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details. Mobile Intel Pentium 4 Processor-M Datasheet 21 Electrical Specifications 2.7 Asynchronous GTL+ Signals Mobile Intel Pentium 4 Processor-M does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Section 2.11 and Section 2.13 for the DC and AC specifications for the Asynchronous GTL+ signal groups. 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Mobile Intel Pentium 4 Processor-M be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required, with each driving a different voltage level. 2.9 System Bus Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] are output signals used to select the frequency of the processor input clock (BCLK[1:0]). Table 5 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Mobile Intel Pentium 4 Processor-M currently operates at a 400-MHz system bus frequency (selected by a 100-MHz BCLK[1:0] frequency). Individual processors will only operate at their specified system bus frequency. For more information about these pins refer to Section 5.2 and the appropriate platform design guidelines. Table 5. BSEL[1:0] Frequency Table for BCLK[1:0] BSEL1 L L H H BSEL0 L H L H Function 100 MHz RESERVED RESERVED RESERVED 22 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications 2.10 Maximum Ratings Table 6 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from Electro Static Discharge (ESD), one should always take precautions to avoid high static voltages or electric fields. Table 6. Processor DC Absolute Maximum Ratings Symbol TSTORAGE VCC VinAGTL+ VinAsynch_GTL+ IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Asynch GTL+ buffer DC input voltage with respect to VSS Max VID pin current Min –40 -0.3 -0.1 Max 85 1.75 1.75 Unit °C V V Notes 2 1 -0.1 1.75 5 V mA NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year. 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5 for the pin signal definitions and signal pin assignments. Most of the signals on the processor system bus are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 13. Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for these signal groups are listed in Table 14 and Table 15. Table 7 through Table 17 list the DC specifications for the Mobile Intel Pentium 4 Processor-M and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Unless specified otherwise, all specifications for the Mobile Intel Pentium 4 Processor-M are at TJ = 100°C. Care should be taken to read all notes associated with each parameter. Mobile Intel Pentium 4 Processor-M Datasheet 23 Electrical Specifications Table 7. Voltage and Current Specifications Symbol VCC Parameter VCC for core logic Maximum Performance Mode Battery Optimized Mode VID supply voltage Transient Deeper Sleep voltage Static Deeper Sleep voltage Current for VCC at core frequency 2.60 GHz & 1.3 V 2.50 GHz & 1.3 V 2.40 GHz & 1.3 V 2.20 GHz & 1.3 V 2.00 GHz & 1.3 V 1.90 GHz & 1.3 V 1.80 GHz & 1.3 V 1.70 GHz & 1.3 V 1.60 GHz & 1.3 V 1.50 GHz & 1.3 V 1.40 GHz & 1.3 V 1.20 GHz & 1.2 V Current for VID supply ICC Stop-Grant and ICCSleep at 1.3 V (for > 2.0 GHz) 1.3 V (for 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time) Tc= T37 (PWRGOOD inactive pulse width) Td= T36 (PWRGOOD to RESET# de-assertion time) Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. For more information on implementation refer to the Intel Mobile Northwood Processor and Intel 845MP Platform RDDP. Figure 17. Power Down Sequence Vcc PWRGOOD VCCVID VID_GOOD VID[4:0] Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. For more information on implementation refer to the Intel Mobile Northwood Processor and Intel 845MP Platform RDDP. 1. This timing diagram is not intended to show specific times. Instead a general ordering of events with respect to time should be observed. 2. When VCCVID is less than 1V, VID_GOOD must be low. 3. Vcc must be disabled before VID[4:0] becomes invalid. 4. VCCVID and Vcc regulator can be disabled simultaneously 46 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications Figure 18. Test Reset Timings TRST# 1.25V Tq Tq = T37 (TRST# Pulse Width) Width), V=GTLREF T38 (PROCHOT# Pulse PCB-773 Tq = T64 (TRST# Pulse Width), V=0.5*Vcc Figure 19. THERMTRIP# to Vcc Timing T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET# is active Figure 20. FERR#/PBE# Valid Delay Timing BCLK system bus STPCLK# Ta SG Ack FERR#/ PBE# FERR# undefined PBE# undefined FERR# Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion) Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE# signal is driven. FERR# is driven at all other times. Mobile Intel Pentium 4 Processor-M Datasheet 47 Electrical Specifications Figure 21. TAP Valid Delay Timing V TCK Tx Signal Ts Th V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.5 * Vcc Figure 22. ITPCLKOUT Valid Delay Timing Tx BCLK ITPCLKOUT T65 = Tx = BCLK input to ITPCLKOUT output delay 48 Mobile Intel Pentium 4 Processor-M Datasheet Electrical Specifications Figure 23. Stop Grant/Sleep/Deep Sleep Timing Normal BCLK[1:0] Stop Grant Sleep Deep Sleep Sleep Stop Grant Normal DPSLP# Tv STPCLK# Ty CPU bus stpgnt Tt SLP# Tu Compatibility Signals Changing Frozen Tz Changing V0011-02 Tw Tx Tt = T70 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay) Tu = T71 (Input Signals Stable to SLP# assertion requirement) Tv = T72 (SLP# to DPSLP# assertion) Tw = T73 (Deep Sleep PLL lock latency) Tx = T74 (SLP# Hold Time) Ty = T75 (STPCLK# Hold Time) Tz = T76 (Input Signal Hold Time) Mobile Intel Pentium 4 Processor-M Datasheet 49 Electrical Specifications Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing BCLK[1:0] SLP# TX DPSLP# TS GHI# GHI# stable Th VID[4:0] previous VID next VID V0036-04 TS = T71 (GHI# Input Setup to SLP# Assertion) Th = T76 (GHI# Input signal Hold Time from SLP# De-assertion) TX = T77 (VID[4:0] Output Valid Delay from DPSLP# Assertion) 50 Mobile Intel Pentium 4 Processor-M Datasheet System Bus Signal Quality Specifications 3. System Bus Signal Quality Specifications Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is important that the designer work to achieve a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation and for interpreting results for signal quality measurements of actual designs. 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines Table 27 describes the signal quality specifications at the processor pads for the processor system bus clock (BCLK) signals. Figure 25 describes the signal quality waveform for the system bus clock at the processor pads. Table 27. BCLK Signal Quality Specifications Parameter Min Max Unit Figure Notes1 BCLK[1:0] Overshoot BCLK[1:0] Undershoot BCLK[1:0] Ringback Margin BCLK[1:0] Threshold Region N/A N/A 0.20 N/A 0.30 0.30 N/A 0.10 V V V V 25 25 25 25 2 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. Mobile Intel Pentium 4 Processor-M Datasheet 51 System Bus Signal Quality Specifications Figure 25. BCLK Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 System Bus Signal Quality Specifications and Measurement Guidelines Various scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Table 28 and Table 29 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor core silicon (pads). Mobile Intel Pentium 4 Processor-M maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 30 through Table 33. Figure 26 shows the system bus ringback tolerance for low-to-high transitions and Figure 27 shows ringback tolerance for high-to-low transitions. Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes All Signals All Signals 0→ 1→ 1 0 GTLREF + 10% GTLREF - 10% V V 26 27 1,2,3,4,5,6,7 1,2,3,4,5,6,7 NOTES: 1. All signal integrity specifications are measured at the processor silicon (pads). 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns. 4. All values specified by design characterization. 5. Please see Section 3.3 for maximum allowable overshoot. 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported. 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise. 52 Mobile Intel Pentium 4 Processor-M Datasheet System Bus Signal Quality Specifications Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups Maximum Ringback (with Input Diodes Present) Notes Signal Group Transition Unit Figure TAP and PWRGOOD TAP and PWRGOOD 0→1 1→0 Vt+(max) TO Vt-(max) Vt-(min) TO Vt+(min) V V 28 29 1,2,3,4 1,2,3,4 NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 3. Please see Section 3.3 for maximum allowable overshoot. 4. Please see Section 2.11 for the DC specifications. Figure 26. Low-to-High System Bus Receiver Ringback Tolerance VCC +10% GTLREF GTLREF -10% GTLREF Noise Margin VSS Figure 27. High-to-Low System Bus Receiver Ringback Tolerance VCC +10% GTLREF GTLREF -10% GTLREF Noise Margin VSS Mobile Intel Pentium 4 Processor-M Datasheet 53 System Bus Signal Quality Specifications Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max) Allowable Ringback Vss Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0. Vss 54 Mobile Intel Pentium 4 Processor-M Datasheet System Bus Signal Quality Specifications 3.3 System Bus Signal Quality Specifications and Measurement Guidelines Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 30. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the Mobile Intel Pentium 4 Processor-M system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot. 3.3.1 3.3.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Mobile Intel Pentium 4 Processor-M both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 30 through Table 33. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.3.3 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (maximum overshoot = 1.700 V, maximum undershoot = -0.400 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Mobile Intel Pentium 4 Processor-M Datasheet 55 System Bus Signal Quality Specifications Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. 3.3.4 Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot (undershoot) waveform occurs every strobe cycle. The specifications provided in Table 30 through Table 33 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: Note: Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency. 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#. 3.3.5 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the Mobile Intel Pentium 4 Processor-M is not a simple single value. Instead, many factors are needed to determine what the over/undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above VCC) and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL+ signals operating in the 4x source synchronous domain, use Table 30. Finally, all other signals reside in the 100MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 33. 2. Determine the magnitude of the overshoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur?) 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. 56 Mobile Intel Pentium 4 Processor-M Datasheet System Bus Signal Quality Specifications The above procedure is similar for undershoot after the undershoot waveform has been converted to look like an overshoot. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. Ensure no signal ever exceeds VCC or -0.25 V OR 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 30 through Table 33. NOTES: 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded. 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC. 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS. 4. Ringback below VCC can not be subtracted from overshoots/undershoots. 5. Lesser undershoot does not allocate longer or larger overshoot. 6. OEM's are strongly encouraged to follow Intel provided layout guidelines. 7. All values specified by design characterization. Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 -0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 0.11 0.24 0.53 1.19 5.00 5.00 5.00 5.00 1.05 2.40 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns. Mobile Intel Pentium 4 Processor-M Datasheet 57 System Bus Signal Quality Specifications Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 -0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 0.21 0.48 1.05 2.38 10.00 10.00 10.00 10.00 2.10 4.80 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns. Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 -0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 0.42 0.96 2.10 4.76 20.00 20.00 20.00 20.00 4.20 9.60 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00 NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns. 58 Mobile Intel Pentium 4 Processor-M Datasheet System Bus Signal Quality Specifications Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 -0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 1.26 2.88 6.30 14.28 60.00 60.00 60.00 60.00 12.6 28.8 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00 NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns. Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform Maximum Absolute Overshoot VMAX VCC Time-dependent Overshoot GTLREF VOL VSS VMIN Maximum Absolute Undershoot Time-dependent Undershoot Mobile Intel Pentium 4 Processor-M Datasheet 59 System Bus Signal Quality Specifications This page intentionally left blank. 60 Mobile Intel Pentium 4 Processor-M Datasheet Package Mechanical Specifications 4. Package Mechanical Specifications The Mobile Intel Pentium 4 Processor-M is packaged in a 478 pin Micro-FCPGA package. Different views of the package are shown in Figure 31 through Figure 33. Package dimensions are shown in Table 34. Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA DIE LABEL TOP VIEW BOTTOM VIEW Mobile Intel Pentium 4 Processor-M Datasheet 61 Package Mechanical Specifications Figure 32. Micro-FCPGA Package Top and Side View 7 (K1) 8 places 5 (K) 4 places SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 0.286 A 1.25 MAX (A3) D1 35 (D) Ø 0.32 (B) 478 places E1 35 (E) A2 PIN A1 CORNER 2.03 ± 0.08 (A1) All dimensions in millimeters. Values shown are for reference only. 62 Mobile Intel Pentium 4 Processor-M Datasheet Package Mechanical Specifications Table 34. Micro-FCPGA Package Dimensions Symbol Param eter A A1 A2 A3 B D E Overall height, top of die to package seating plane O verall height, top of die to PCB surface, including socket(1) Pin length Die height Pin-side capacitor height P in diameter P ackage substrate length P ackage substrate width 0.28 34.9 34.9 Min 1.81 4.69 1.95 0.854 1.25 0.36 35.1 35.1 M ax 2.03 5.15 2.11 Unit mm mm mm mm mm mm mm mm D1 Die length 12.24 (B0 Step) 11.62 (B0 Step Shrink & C1/D1 Step) 11.93 (B0 Step) 11.34 (B0 Step Shrink & C1/D1 Step) 1.27 5 7 14 2.0 GHz) 1.3 V (for