41210

Intel® 41210 Serial to Parallel PCI Bridge Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PCI Express Specification, Revision 1.0a Support for single x8, single x4 or single x1 PCI Express operation. 64-bit addressing support 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets. 16-bit CRC on all link message information. Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s. Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s. PCI Local Bus Specification, Revision 2.3. PCI-to-PCI Bridge Specification, Revision 1.1. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant. On Die Termination (ODT) with 8.3KOhm pull-up to 3.3V for PCI signals. Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively. Programmable bus parking on either the last agent or always on the 41210 Bridge ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT) External PCI clock-feed support for asynchronous primary and secondary domain operation. 64-bit addressing for upstream and downstream transactions Downstream LOCK# support. No upstream LOCK# support. PCI fast Back-to-Back capable as target. Up to four active and four pending upstream memory read transactions Up to two downstream delayed (memory read, I/O read/write and configuration read/ write) transaction. Tunable inbound read prefetch algorithm for PCI MRM/MRL commands Device hiding support for secondary PCI devices. Secondary bus Private Memory support via Opaque memory region Local initialization via SMBus Secondary side initialization via Type 0 configuration cycles. Full peer-to-peer read/write capability between the two secondary PCI segments. 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Copyright © 2005, Intel Corporation 2 Contents Contents 1 Introduction .................................................................................................................................... 7 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 About This Document ........................................................................................................... 7 Product Overview ................................................................................................................. 7 On Die Termination (ODT).................................................................................................... 8 PCI Express Interface.........................................................................................................10 PCI Bus Interface (Two Instances) .....................................................................................10 PCI Bus Interface 64-Bit Extension (Two Interfaces) .........................................................12 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) ..............13 Interrupt Interface (Two Interfaces) ....................................................................................13 Reset Straps .......................................................................................................................13 SMBus Interface .................................................................................................................15 Miscellaneous Pins .............................................................................................................15 DC Voltage and Current Specifications ..............................................................................17 AC Specifications................................................................................................................25 Voltage Filter Specifications ...............................................................................................27 VCC15 and VCC33 Voltage Requirements ........................................................................27 Timing Specifications ..........................................................................................................28 41210 Bridge Power Consumption .....................................................................................36 Power Delivery Guidelines..................................................................................................37 Reference and Compensation Pins ....................................................................................37 Thermal Specifications .......................................................................................................38 Package Specification ........................................................................................................40 Ball Map ..............................................................................................................................42 Signal List, sorted by Ball Location.....................................................................................44 Signal List, sorted by Signal Name.....................................................................................48 Signal Description ......................................................................................................................... 8 Electrical and Thermal Characteristics .....................................................................................17 Package Specification and Ballout ............................................................................................40 Figures 1 2 3 4 5 6 7 8 9 10 Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22 Compliance Test/Measurement Load.........................................................................................23 Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23 Voltage Requirements VCC33 versus VCC15 ...........................................................................27 PCI Output Timing ......................................................................................................................31 PCI Input Timing .........................................................................................................................31 PCI-X 3.3V Clock Waveform ......................................................................................................33 41210 Bridge Reference and Compensation Circuit Implementations .......................................38 41210 Bridge Package Dimensions (Top View) .........................................................................40 41210 Bridge Package Dimensions (Side View) ........................................................................41 3 Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ODT Signals ................................................................................................................................. 9 PCI Express Interface Pins......................................................................................................... 10 PCI Interface Pins....................................................................................................................... 11 PCI Interface Pins: 64-Bit Extensions......................................................................................... 12 PCI Clock and Reset Pins .......................................................................................................... 13 Interrupt Interface Pins ............................................................................................................... 13 Reset Strap Pins......................................................................................................................... 14 SMBus Interface Pins ................................................................................................................. 15 Miscellaneous Pins ..................................................................................................................... 15 Intel® 41210 Bridge DC Voltage Specifications ......................................................................... 17 DC Characteristics Input Signal Association .............................................................................. 18 DC Input Characteristics............................................................................................................. 18 DC Characteristic Output Signal Association ............................................................................. 18 DC Output Characteristic............................................................................................................ 19 Differential Transmitter (TX) DC Output Specifications .............................................................. 19 Differential Receiver (RX) DC Input Specifications .................................................................... 21 DC Specifications for PCI and PCI-X 3.3 V Signaling ................................................................ 24 DC Specification for Input Clock Signals .................................................................................... 25 DC Specification for Output Clock Signals ................................................................................. 25 Conventional PCI 3.3V AC Characteristics ................................................................................ 25 PCI-X 3.3V AC Characteristics ................................................................................................... 26 Differential Transmitter (TX) AC Output Specifications .............................................................. 28 Differential Receiver (RX) AC Input Specifications..................................................................... 29 PCI Interface Timing................................................................................................................... 30 PCI-X 3.3V Signal Timing Parameters ....................................................................................... 31 PCI and PCI-X Clock Timings .................................................................................................... 33 41210 Bridge Clock Timings....................................................................................................... 35 41210 Bridge Maximum Voltage Plane Currents ....................................................................... 37 41210 Bridge Thermal Voltage Plane Currents .......................................................................... 37 41210 Bridge Thermal Specifications ......................................................................................... 39 Signal List, sorted by Ball Name................................................................................................. 44 Signal List, sorted by Signal Name............................................................................................. 48 4 Contents Revision History Date May 2005 April 2005 September 2004 June 2004 September 2003 Revision 005 004 003 002 001 Description Revised Table 1, Table 9, and Section 3.8 Revised Table 26 “PCI and PCI-X Clock Timings” on page 33 CLK Cycle Time parameters Revised first page PCI Express operation description; updated information in Table 2. Added Chapter 2. Removed original Sections 3.6 and 3.7. Updated VCC information to VCC15. Initial release 5 Order Number: 278875-005US May 2005 Datasheet — 41210 Bridge Introduction 1.1 About This Document 1 This document provides information on the Intel® 41210 Serial to Parallel PCI Bridge, including a functional overview, signal descriptions, mechanical data, package signal location and bus functional waveforms. 1.2 Product Overview The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge) integrates two PCI Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two PCI bus interfaces are compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. 7 41210 Bridge — Datasheet Signal Description 2 The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I: O: OD: I/O: I/OD: Input pin Output pin Open-drain Output pin Bidirectional Input/Output pin Bidirectional Input/Open-drain Output pin 2.1 On Die Termination (ODT) The 41210 Bridge incorporates on-die termination for most of the PCI interface signals. This eliminates the need for the system designer to incorporate external pull-up resistors in the design. The following signals have an on die termination of 8.33KOhm @40%: 8 Datasheet — 41210 Bridge Table 1. ODT Signals A_ACK64# A_AD[63:32] A_CBE#[7:4] A_DEVSEL# A_FRAME# A_GNT#[5:0] A_IRDY# A_PAR A_PAR64 A_PERR# A_LOCK# A_REQ#[5:0] A_REQ64# A_SERR# A_STOP# A_TRDY# A_INTA# A_INTB# A_INTC# A_INTD# TCK TDI TDO TMS B_ACK64# B_AD[63:32] B_CBE#[7:4] B_DEVSEL# B_FRAME# B_GNT#[5:0] B_IRDY# B_PAR B_PAR64 B_PERR# B_LOCK# B_REQ#[5:0] B_REQ64# B_SERR# B_STOP# B_TRDY# B_INTA# B_INTB# B_INTC# B_INTD# 9 41210 Bridge — Datasheet 2.2 Table 2. PCI Express Interface PCI Express Interface Pins Signal REFCLKp/ REFCLKn I/O I Description PCI Express Reference Clocks: 100 MHz differential clock pair. PCI Express Serial Data Transmit: PCI Express differential data transmit signals. PETp[7:0]/ PETn[7:0] O X8 Mode: All PETp[7:0]/ PETn[7:0] are used X4 Mode: Only PETp[3:0]/ PETn[3:0] are used x1 Mode: Either PETp[0]/ PETn[0] is used or PETp[7]/ PETn[7] is used PCI Express Serial Data Receive: PCI Express differential data receive signals. PERp[7:0]/ PERn[7:0] I X8 Mode: All PERp[7:0]/ PERn[7:0] are used X4 Mode: Only PERp[3:0]/ PERn[3:0] are used x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used PE_RCOMP[1:0] Total I 36 PCI Express Compensation Inputs: Analog signals. Connect to a 24.9Ω±1% pull-up resitor to 1.5V. A single resistor can be used for both signals. 2.3 PCI Bus Interface (Two Instances) Each interface is marked by either the letter “A” or “B” to signify the interface. Therefore, A_AD refers to the AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For pin names described in the following sections, an ‘X’ in the name indicates either A or B, for the PCI bus A and PCI bus B sides. For example, X_PAR signal would be called A_PAR on the PCI bus A and B_PAR on the PCI bus B. 10 Datasheet — 41210 Bridge Table 3. Signal PCI Interface Pins (Sheet 1 of 2) I/O Description PCI Address/Data: These signals are a multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on X_AD[31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data. No External pull-up resistors are required on the system board for these signals. Bus Command and Byte Enables: These signals are a multiplexed command field and byte enable field. During the address phase or phases of a transaction, the initiator drives the transaction type on C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address command and the second address phase carries the transaction type. For both read and write transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases. No External pull-up resistors are required on the system board for these signals. Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits regardless of the valid byte enables. It is generated for address and data phases. It is driven identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during the address phase for all 41210 Bridge initiated transactions and all data phases when the 41210 Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction. 41210 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of A_AD[31:0] B_AD[31:0] I/O A_C/BE#[3:0] B_C/BE#[3:0] I/O A_PAR B_PAR I/O PCI write transactions. No External pull-up resistors are required on the system board for these signals. Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41210 Bridge asserts DEVSEL# when a PCI master peripheral attempts an access an address destined for PCI Express. As an initiator, DEVSEL# indicates the response to a 41210 Bridge initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the 41210 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. A_FRAME# B_FRAME# Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data phase. No External pull-up resistors are required on the system board for these signals. A_IRDY# B_IRDY# I/O Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted. No External pull-up resistors are required on the system board for these signals. Target Ready: Indicates the ability of the target to complete the current data phase of the transaction. A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated from the leading edge of RST#. TRDY# remains tri-stated by the 41210 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. A_STOP# B_STOP# A_PERR# B_PERR# I/O Stop: Indicates that the target is requesting an initiator to stop the current transaction. No External pull-up resistors are required on the system board for these signals. Parity Error: Driven by an external PCI device when it receives data that has a parity error. Driven by I/O 41210 Bridge when, as a initiator it detects a parity error during a read transaction and as a target A_DEVSEL# B_DEVSEL# I/O I/O A_TRDY# B_TRDY# I/O during write transactions. No External pull-up resistors are required on the system board for these signals. System Error: The 41210 PCI Express. A_SERR# B_SERR# Bridge samples SERR# as an input and conditionally forwards it to the I No External pull-up resistors are required on the system board for these signals. 66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be used to generate appropriate clock (33 or 66 MHz) on the PCI Bus. Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground. A_M66EN B_M66EN I/OD 11 41210 Bridge — Datasheet Table 3. Signal A_PCIXCAP B_PCIXCAP A_LOCK# B_LOCK# Total PCI Interface Pins (Sheet 2 of 2) I/O I Description Bridge can switch into PCI-X mode. Use an approximately 8.2KΩ resistor to pull to VCC33. PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the 41210 O PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete. This signal is an output from the bridge when it is initiating exclusive transactions on PCI. LOCK# is ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream. No External pull-up resistors are required on the system board for these signals. 118 2.4 Table 4. Signal A_AD[63:32] B_AD[63:32] PCI Bus Interface 64-Bit Extension (Two Interfaces) PCI Interface Pins: 64-Bit Extensions I/O Description PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when REQ64# and ACK64# are both asserted. Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and byte enable field. For both reads and write transactions, the initiator will drive byte enables for the AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both asserted. PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/ BE#[7:4] for both address and data phases. PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41210 Bridge is the initiator, this signal is an output. When the 41210 Bridge is the target this signal is an input. PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same timing as DEVSEL#. I/O A_C/BE#[7:4] B_C/BE#[7:4] A_PAR64 B_PAR64 A_REQ64# B_REQ64# A_ACK64# B_ACK64# I/O I/O I/O I/O 78 Total 12 Datasheet — 41210 Bridge 2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) PCI Clock and Reset Pins I/O Description PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. X_CLK[6] must be connected to the respective X_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be disabled via the “Offset 43: PCLKC – PCI Clock Control” register and should be treated as no connects on the board. Table 5. Signal A_CLKO[6:0] B_CLKO[6:0] O Note: A_CLKIN B_CLKIN A_RST# B_RST# A_PME# B_PME# I O Registers are listed in the Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual. PCI Clock In: This signal is PCI clock feedback input. This pin should be connected to the corresponding X_CLKO[6] through a 22Ω±1% series resistor. PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus. PCI Power Management Event: PCI bus power management event signal. This is a shared open drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive signal that will be converted to a PME event on PCI Express. This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally. I Total 20 2.6 Interrupt Interface (Two Interfaces) This section lists the interrupt interface signals. There are two sets of interrupt signals for the standard INTA:INTD pci signals. Table 6. Signal A_INTA# A_INTB# A_INTC# A_INTD# B_INTA# B_INTB# B_INTC# B_INTD# Interrupt Interface Pins I/O Description I Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these interrupt lines. Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information on device numbering. Total 8 2.7 Reset Straps The following signals are used for static configuration. These signals are all sampled on the rising edge of PERST#. 13 41210 Bridge — Datasheet Table 7. Reset Strap Pins Signal I/O Description PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to run at 133 MHz when X_PCIXCAP is sampled high. When low, the PCI-X segment will only run at 100 MHz when X_PCIXCAP is sampled high. Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground. Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3 must be pulled high for normal operation. X_STRAP A_STRAP[6:0 ] B_STRAP[6:0 ] 0 1 2 3 4 5 6 Logic Level ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘0’ A_133EN B_133EN I I Use approximately an 8.2KΩ resistor to pull-up to VCC33 or pull-down to VSS A_TEST[2:1] B_TEST{2:1] I Internal Test Modes: These straps should be pulled high to VCC33. Use approximately an 8.2KΩ resistor to pull-up to VCC33. Configuration Retry: This pin, when sampled high sets the Configuration Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC. If no local initialization is needed, this pin should be pulled low to VSS. Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information. CFGRETRY I Total 19 14 Datasheet — 41210 Bridge 2.8 Table 8. SMBus Interface SMBus Interface Pins Signal SMBCLK SMBDAT I/O I/OD I/OD Description SMBus Clock: This signal should be pulled to 3.3V via an 8.2KOhm resistor. SMBus Data: This signal should be pulled to 3.3V via an 8.2KOhm resistor. SMBus Addressing Straps: These straps set the SMBus Address for 41210 Bridge. The address is determined as indicated below: Bit 7‘1’ Bit 6‘1’ SMBUS[5] SMBUS[3:1] Bit 5SMBUS[5] I Bit 4‘0’ Bit 3SMBUS[3] Bit 2SMBUS[2] Bit 1SMBUS[1] These signals (bits 5, 3:1) should be pulled up to 3.3V or down to ground. Sampled at the rising edge of PERST#. Total 6 2.9 Table 9. Miscellaneous Pins Miscellaneous Pins Signal I/O Description Configuration Reset: This signal is asserted low when ever the bridge goes through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This signal should be used to indicate when the local initialization methods should be executed. Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information. PERST# I PCI Express Fundamental Reset: When low, asynchronously resets the internal logic (including sticky bits). Reset In: When Asserted, this signal asynchronously resets the internal logic and asserts X_RST# output for both PCI interfaces. This signal should be pulled high for adapter card usage. TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable frequency is 0-16MHz If not utilizing JTAG, this signal can be left as a no connect. Test Data In: This is the serial data input to the JTAG BSCAN shift register chain and to the JTAG BSCAN control logic. This is latched in on the rising edge of TCK. If not utilizing JTAG, this signal can be left as a no connect. Test Data Output: This is the serial data output from the JTAG BSCAN logic If not utilizing JTAG, this signal can be left as a no connect. CFGRST# O RSTIN# I TCK I TDI I TDO O 15 41210 Bridge — Datasheet Signal TMS I/O I Description Test Mode Select: This signal controls the TAP controller state machine to move to different states and is sampled on the rising edge of TCK. If not utilizing JTAG, this signal can be left as a no connect. Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN logic. If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down resistor. Reserved: (8 pins) These input pins should be pulled low Use an approximately 8.2KΩ resistor to pull-down to ground. No Connect: (39 pins) These output pins should be left floating This signal requires an external pull-up, 8.2K ohm to 3.3V 57 TRST# I RESERVED[8:1] NC[19:18], NC[16:1] A_NC[10:1] B_NC[10:1] NC[17] I O O Total 16 Datasheet — 41210 Bridge Electrical and Thermal Characteristics 3 3.1 3.1.1 Table 10. DC Voltage and Current Specifications 41210 Bridge DC Specifications Intel® 41210 Bridge DC Voltage Specifications Symbol VCC15 VCC15 VCCAPE VCCAPCI[2:0] VCCBGPE VCCPE VCC33 Parameter Intel® 41210 Bridge Core PCI-X I/O Voltage Analog PCI Express Voltage Analog PCI Voltages Analog Bandgap Voltage PCI Express Interface Voltage PCI Bus Interface Voltage Min 1.425 1.425 1.455 1.455 2.425 1.46 3.0 1.5 1.5 1.5 1.5 2.5 1.5 3.3 Typ Max 1.575 1.575 1.545 1.545 2.575 1.55 3.6 V V 2 V V V 1 Unit Notes PTDP Thermal Design Power 10.2 W 1. Transient tolerance ±5 mV above 1 MHz at package pin under DC load conditions. 2. Transient tolerance ±10 mV above 1 MHz at package pin under DC load conditions. 17 41210 Bridge — Datasheet 3.1.2 Table 11. Input Characteristic Signal Association DC Characteristics Input Signal Association Symbol Signals Interrupt Signals: A_IRQ[15:0]#, B_IRQ[15:0]# PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR, A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#, B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_SERR#, B_SERR#, A_REQ[5:0]#, B_REQ[5:0]#, A_M66EN, B_M66EN, A_133EN, B_133EN, A_PCIXCAP, B_PCIXCAP, A_PAR64, B_PAR64, A_REQ64#, B_REQ64#, A_ACK64#, B_ACK64# Clock Signals (3.3 V Only): A_CLKI, B_CLKI Miscellaneous Signals: PERST# VIH2/VIL2 VIH3/VIL3 PCI Express Signals: REFCLK, REFCLK#, PETP[7:0], PETN[7:0], PE_RCOMP[1:0] SMB Signals: SMBDAT, SMBCLK VIH1/VIL1 3.1.3 Table 12. DC Input Characteristics DC Input Characteristics 3.3 V Signal Symbol VIL1 VIH1 Symbol VIL2 VIH2 VIL3 VIH3 Parameter Min Input Low Voltage Input High Voltage Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage -0.5 0.5 VCC33 Max 0.35 VCC33 VCC33 +0.5 Max N/A N/A 0.6 VCC33 + 0.5 V V V V V V Unit 3.1.4 Table 13. DC Characteristic Output Signal Association DC Characteristic Output Signal Association Symbol Signals PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR, A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#, B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_M66EN, B_M66EN, A_GNT[6:0]#, B_GNT[5:0]#, A_LOCK#, B_LOCK#, A_PAR64, B_PAR64, A_REQ64#, B_REQ64#, A_ACK64#, B_ACK64# PCI Clock Signals (3.3 V Only): A_CLKO[6:0], B_CLKO[6:0], A_RST#, B_RST# Miscellaneous Signals: RASERR# VOH2/VOL2 VOH3/VOL3 PCI Express Signals: PERP[7:0], PERN[7:0] SMBus Signals: SMBDAT, SMBCLK VOH1/VOL1 18 Datasheet — 41210 Bridge 3.1.5 Table 14. DC Output Characteristics DC Output Characteristic 3.3 V Signal Symbol Parameter Min VOL1 VOH1 Symbol VOL2 VOH2 VOL3 VOH3 Output Low Voltage Output High Voltage Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage 0.9VCC33 Max N/A N/A 0.4 N/A V V V V IOL4=14 mA Open Drain Max 0.1VCC33 V V Unit (5 V) Iout = 6 mA (3.3 V) Iout = 1500 uA (5 V) Iout = -2 mA (3.3 V) Iout = -500 uA Notes Unit Notes 3.1.6 3.1.6.1 PCI Express Interface DC Specifications Differential Transmitter (TX) DC Output Specifications Table 15 defines the DC specifications of parameters for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 15. Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2) Symbol VTX-DIFFp-p Parameter Differential Peak to Peak Output Voltage De-Emphasized Differential Output Voltage (Ratio) Min 0.80 Nom Max 1.2 Units V Comments VTX-DIFFp-p = 2*|VTX-D+-VTX-D-| See Note 1. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition See Note 1. AC Peak Common Mode Output Voltage VTX-CM-ACp = CM-DC 20 mV |VTX-D+ + vTX-D-| / 2 – vTX|VTX-D+ + VTX-D-| VTX-DE-RATIO -3.0 -3.5 -4.0 dB VTX-CM-ACp vTX-CM-DC = DC(avg) of / 2 during L0 See Note 1. VTX-CM-DCACTIVE-IDLEDELTA Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle |VTX-CM-DC [during L0] – VTX-CM-IdleDC[during electrical idle]|