82562EX

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Networking Silicon 317520-002 Revision 2.2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. 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Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © Intel Corporation, 2008 *Third-party brands and names are the property of their respective owners. ii 82562EZ(EX)/82547GI(EI) Dual Footprint Revision History Revision 0.25 0.75 Revision Date Jul 2002 Sep 2002 Description Initial publication of preliminary design guide information. Published revised design guide information: • Added information on EEPROM settings • Added design checklist • Revised reference design schematic • Revised Ball Number to signal mapping Table to conform to changes in 82547EI datasheet rev 0.75 1.0 Oct 2002 Published revised design guide information: • Added layout checklist • Updated LAN disable circuit • Removed EEPROM information due to publication of separate guides 1.5 Sep 2003 Published revised design guide information: • Added 82547GI coverage • Removed Confidential status • Updated schematics, removed redundant caps • Revised LAN disable circuit 1.6 Nov 2004 Added crystal start-up information. Information includes: • New crystal parameters • Crystal selection guidelines • Crystal validation methods • Crystal testing methods Changed signal name FL_SO to the correct signal name FLSH_SO. Added 82562EX applicability. Added new values for TX and RX terminations (next to LAN silicon). New values are now 110 Ω for both TX and RX terminations. Added new starting values for RBIAS100 and RBIAS10. New starting values are now 649 Ω for RBIAS100 and 619 Ω for RBIAS10. Updated reference schematics to reflect new Tx and Rx termination values, new LAN disable circuit, and RBIAS100/RBIAS10 values. Removed excess capacitors and changed pins F12 and H12 to no connects. Added a 1K Ω resistor to pin A13 output. 1.7 Jan 2005 • Changed text in the Catalyst EEPROM revision H table note from “Revision H or higher not supported” to “Revision H is not supported”. • Removed the Design and Layout Checklists. These checklists are now separate Microsoft* Excel spreadsheets. 1.8 Jan 2005 Updated reference schematics to reflect current differential pair termination resistor values for the 82547GI/EI. Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/ EX PLC Device” to reflect current resistor and RBIAS values. Updated section 4.3.1 “Termination Resistors for Designs Based on 8257GI(EI) Gigabit Ethernet Controller” to reflect current resistor values. 1.9 2.0 2.1 2.2 June 2006 Feb 2007 June 2007 Jan 2008 Updated reference schematics for signals EE_MODE and JTAG_TRST# (changed resistor values from 1 K Ω to 100 Ω). Updated sections 3.1.3, 3.1.1.8, and Table 5 in section 3.1.1 (changed max ESR rate from 20 Ω to 10 Ω for the 82547GI/EI). Updated reference schematics: sheets 4 and 6. Added Table 6; approved crystals for the 82547GI(EI). iii 82562EZ(EX)/82547GI(EI) Dual Footprint Note: This page is intentionally left blank. iv 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Contents 1.0 1.1 1.2 1.3 2.0 2.1 2.2 Introduction......................................................................................................................... 1 Scope............................................................................................................................................ 1 Reference Documents .................................................................................................................. 2 Product Codes .............................................................................................................................. 2 System Data Port Interfaces .............................................................................................. 3 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ................................................. 3 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ............................................... 4 2.2.1 Generation/Distribution of Reference Voltages ............................................................... 4 2.2.2 CSA Port Resistive Compensation .................................................................................. 5 Ethernet Component Design Guidelines ............................................................................ 7 General Design Considerations for Ethernet Controllers.............................................................. 7 3.1.1 Crystal Selection Parameters .......................................................................................... 7 3.1.2 Reference Crystal ..........................................................................................................10 3.1.3 Reference Crystal Selection ..........................................................................................11 3.1.4 Circuit Board ..................................................................................................................11 3.1.5 Temperature Changes...................................................................................................11 3.1.6 Integrated Magnetics Module ........................................................................................12 Designing with the 82562EZ(EX) Platform LAN Connect Device...............................................12 3.2.1 82562EZ/EX PLC Device LAN Disable Guidelines .......................................................12 3.2.2 Serial EEPROM for 82562EZ(EX) Implementations......................................................13 3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device........................................................14 3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations ..............................................14 3.2.5 82562EZ(EX) Device Test Capability ............................................................................14 Designing with the 82547GI(EI) Gigabit Ethernet Controller ......................................................14 3.3.1 82547GI(EI) Ethernet Controller LAN Disable Guidelines .............................................14 3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations .......................................15 3.3.3 EEPROM Map Information ............................................................................................17 3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications .........................................17 3.3.5 Power Supplies for the 82547GI(EI) Device ..................................................................17 3.3.6 82547GI(EI) Controller Power Supply Filtering..............................................................18 3.3.7 82547GI(EI) Controller Power Management and Wake Up...........................................18 3.3.8 82547GI(EI) Device Test Capability ..............................................................................19 Ethernet Component Layout Guidelines ..........................................................................21 General Layout Considerations for Ethernet Controllers ............................................................21 4.1.1 Guidelines for Component Placement ...........................................................................21 4.1.2 Crystals..........................................................................................................................22 4.1.3 Board Stack Up Recommendations...............................................................................22 4.1.4 Differential Pair Trace Routing.......................................................................................23 4.1.5 Signal Trace Geometry..................................................................................................24 4.1.6 Trace Length and Symmetry .........................................................................................24 4.1.7 Impedance Discontinuities.............................................................................................25 4.1.8 Reducing Circuit Inductance..........................................................................................25 4.1.9 Signal Isolation ..............................................................................................................25 4.1.10 Power and Ground Planes.............................................................................................25 3.0 3.1 3.2 3.3 4.0 4.1 v 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 4.2 4.3 4.4 4.5 5.0 6.0 7.0 A B 4.1.11 Traces for Decoupling Capacitors ................................................................................. 26 4.1.12 Ground Planes Under the Magnetics Module................................................................ 26 4.1.13 Special Considerations for Non-Integrated Magnetics Modules and RJ-45 Connectors................................................................... 28 Layout for the 82562EZ(EX) Platform LAN Connect Device ...................................................... 29 4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC Device...................... 29 4.2.2 Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device....................... 29 Layout for the 82547GI(EI) Gigabit Ethernet Controller ............................................................. 30 4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller 30 4.3.2 Light Emitting Diodes for Designs Based on 82547GI(EI) Controller ............................ 30 Physical Layer Conformance Testing ......................................................................................... 30 Troubleshooting Common Physical Layout Issues..................................................................... 31 Design and Layout Checklists.......................................................................................... 33 Ball Number to Signal Mapping with Population Options................................................. 35 Dual Footprint Reference Schematic ............................................................................... 43 Measuring LAN Reference Frequency Using a Frequency Counter................................ 51 GigConf.exe Register Settings for 82547GI(EI) Devices ................................................. 57 Figures 1 2 3 4 5 6 5 6 7 8 9 10 11 12 ICH5 Platform LAN Connect Sections .......................................................................................... 3 CSA Port Locally Generated Reference Divider Circuits.............................................................. 4 CSA port CI_RCOMP Circuits ...................................................................................................... 5 Crystal Circuit ............................................................................................................................... 9 LAN Disable Circuitry ................................................................................................................. 13 82547GI(EI) LAN Disable Circuitry ............................................................................................. 15 General Placement Distances .................................................................................................... 22 Trace Routing ............................................................................................................................. 23 Ground Plane Separation ........................................................................................................... 26 Ideal Ground Split Implementation ............................................................................................. 27 Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics ................. 28 82562EZ(EX) PLC Device Differential Signal Termination......................................................... 29 Indirect Probing Setup ................................................................................................................ 52 Direct Probing Method ................................................................................................................ 55 vi 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LAN Component Connections/Features ....................................................................................... 1 Product Ordering Codes ............................................................................................................... 2 CSA Port Reference Circuit Specifications................................................................................... 4 CSA Port CI_RCOMP Resistor Values......................................................................................... 5 Crystal Parameters ....................................................................................................................... 7 82547GI(EI) Recommended Crystals...........................................................................................8 82562EZ(EX) Memory Layout (128 Byte EEPROM) ..................................................................13 82562EZ(EX) Memory Layout (512 Byte EEPROM) ..................................................................14 82562EZ(EX) Recommended Magnetics Modules.....................................................................14 Microwire 64 x 16 Serial EEPROMs ...........................................................................................16 SPI Serial EEPROMs for 82547GI(EI) Controller .......................................................................16 82547GI(EI) EEPROM Memory Layout......................................................................................17 82547GI(EI) Recommended Magnetics Modules.......................................................................17 Ball Number to Signal Mapping ..................................................................................................35 vii 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Note: This page intentionally left blank. viii 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 1.0 Introduction Intel currently supports several footprint compatible Ethernet options depending upon the target application. The term “footprint compatible” means that the silicon devices are all manufactured in a 15 mm x 15 mm, 196-ball grid array package with the same ball pattern. Many of the critical signal pin locations are identical, allowing designers to create a single LAN on Motherboard (LOM) design that accommodates all devices. This is a flexible, cost-effective, multipurpose design technique that allowing maximized value while matching performance needs. Note: Since some of the signal pins have different usages, the term “pin-compatible” is not applicable. Available LAN components with the same footprint include the 82547GI(EI) Gigabit Ethernet Controller and the 82562EZ(EX) Platform LAN Connect components. The LAN component used on a specific platform depends on the end user’s need for connection speed and manageability. As the requirements change, footprint compatibility makes it possible to re-focus the platform without the need to redesign a new a motherboard. Table 1. LAN Component Connections/Features LAN Component Intel 82547GI(EI) ® Interface CSA Connection Gigabit Ethernet (1000BASE-T) with Alert Standard Format (ASF) alerting 10/100 Ethernet with ASF alerting Basic 10/100 Ethernet Features Gigabit Ethernet, ASF 2.0 alerting Ethernet 10/100 connection, ASF 1.0 alerting Ethernet 10/100 connection Intel® 82562EX (196 BGA) LCI Intel® 82562EZ (196 BGA) LCI 1.1 Scope This application note contains Ethernet design guidelines applicable to LOM designs based on the Intel® 865 Chipset and Intel® 875 Chipset. The document identifies similarities and differences between the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller. Section 2 describes the port interfaces specific to each device. Section 3 explains what you need to know to hook up an Ethernet device to the system. Section 4 describes board layout techniques applicable to these devices. Section 5 provides a reference to the design and layout checklists. 1 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Section 6 compares pin names and numbers between the two components. Section 7 concludes with a reference design schematic of the full dual footprint configuration. Note: It is assumed that the reader is acquainted with high-speed design and board layout techniques. Additional documents may be referred to for further information. 1.2 Reference Documents • 82547GI(EI) Gigabit Ethernet Controller Datasheet. Intel Corporation. • 82562EZ 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet. Intel Corporation. • 82562ET/EM Platform LAN Connect Printed Circuit Board Design Guide. Intel Corporation. • 82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map and Programming Information. Intel Corporation. • ICH2 Integrated LAN Controller Function Disable and Power Control. Intel Corporation. • PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group. • IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published separately. • I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation. • I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation. Programming information can be obtained through your local Intel representative. 1.3 Product Codes Table 2 lists the product ordering codes for the 82562EZ(EX)and 82547GI(EI). Table 2. Product Ordering Codes Device 82562EZ 82562EX 82547GI 82547EI Product Code GD82562EZ GD82562EX GD82547GI GD82547EI Product Code (Lead Free) LU82562EZ LU82562EX LU82547GI LU82547EI 2 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 2.0 System Data Port Interfaces The 82562EZ(EX) Platform LAN Connect Device and the 82547GI(EI) Gigabit Ethernet controller employ different system interfaces, as illustrated in Figure 1. GMCH Intel® 82547GI(EI) CSA Magnetics Module LCI Intel® 82562EZ(EX) Connector Intel® ICH5 Figure 1. ICH5 Platform LAN Connect Sections 2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device The 82562EZ(EX) Platform LAN Connect device uses the LAN Connect Interface (LCI) to connect to the I/O Control Hub 5 (ICH5). LCI is a point-to-point interface optimized to support one device. Line termination mechanisms are not specified for the LCI. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing. For details about how to connect the LCI interface between the 82562EZ(EX) Platform LAN Connect device and ICH5, please refer to the 82562ET/EM Platform LAN Connect Printed Circuit Board (PCB) Design Guide, the Intel® 865 Chipset design guide, or the Intel® 875 Chipset design guide. 3 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller The 82547GI(EI) Gigabit Ethernet Controller uses the Communications Streaming Architecture (CSA) port to connect to the Memory Control Hub (MCH). CSA is a point-to-point interface supporting one device. CSA has a theoretical bandwidth of 266 MB/s, sufficient to support Gigabit Ethernet speeds. The connection to the MCH places the Ethernet controller close to system memory for minimum latency. The CSA interface uses IGTL buffers to achieve very high data speeds while controlling transmission line characteristics. For details on connecting the CSA interface between the 82547GI(EI) Gigabit Ethernet Controller and the MCH, please refer to the Intel® 865 Chipset design guide, or the Intel® 875 Chipset design guide. 2.2.1 Generation/Distribution of Reference Voltages The 11-bit CSA port on the 82547GI(EI) controller has a dedicated CI_VREF pin to sample the reference voltage. The nominal CSA port reference voltage is 0.35 V ± 3%. In addition to the reference voltage, a reference swing voltage, CI_SWING must be supplied to control buffer voltage swing characteristics. The nominal CSA port reference voltage swing must be 0.8 V ± 3%. Table 3. CSA Port Reference Circuit Specifications Reference Voltage Specification (V) 0.350 ± 3% Reference Swing Voltage Specification (V) 0.8 ± 3% 1.2 V Voltage Divider Circuit Recommended Resistor Values (Ω) R1 = 523 ± 1% R2 = 665 ± 1% R3 = 604 ± 1% 1.2V 0.8 V R3 CI_SWING C1 R2 C2 Intel® 82547GI(EI) CI_VREF C1 R1 C2 0.35 V Figure 2. CSA Port Locally Generated Reference Divider Circuits 4 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide The values of R1, R2 and R3 must be rated at ±1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification. A 0.1 µF capacitor (C1 in Figure 2) should be placed within 0.5 inches to each resistor divider, and a 0.01 µF bypass capacitor (C2 in Figure 2) should be placed within 0.25 inches of reference voltage pins. If the length of the trace from the voltage divider to the pin is greater than 1 inch, place more than one 0.01 µF capacitor near the reference voltage pin. The trace length from the voltage divider circuit to the CI_REF pins must be no longer than 3.5 inches. Both the voltage reference and voltage swing reference signals should be routed at least 10mils wide and spaced at least 20 mils from all other signals. 2.2.2 CSA Port Resistive Compensation The CSA port uses a resistive compensation signal (CI_RCOMP) to compensate buffer characteristics for temperature, voltage, and process. Table 4. CSA Port CI_RCOMP Resistor Values Component Intel 82547GI(EI) ® Trace Impedance 60 Ω ± 15% RCOMP Resistor Value R1 = 30.1 Ω ± 1% RCOMP Resistor Tied To VCC1.2 1.2V R1 CI_RCOMP Intel® 82547GI(EI) Figure 3. CSA port CI_RCOMP Circuits 5 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Note: This page intentionally left blank. 6 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 3.0 Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. The main design elements are the 82562EZ(EX) Platform LAN Connect device or the 82547GI(EI) Gigabit Ethernet Controller, an integrated magnetics module with RJ-45 connector, and a crystal clock source. 3.1 General Design Considerations for Ethernet Controllers These recommendations apply to all designs, 10/100 or 10/100/1000 Mb/s. Follow good engineering practices with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless the data sheet, design guide or reference schematic indicates otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect. These devices may have special test modes that could be entered inadvertently. 3.1.1 Crystal Selection Parameters Quartz crystals are generally considered to be the mainstay of frequency control components due to their low cost and ease of implementation. They are available from numerous vendors in many package types and with various specification options. All crystals used with Intel® Ethernet controllers are described as “AT-cut”, which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. Table 5 lists the crystal electrical parameters and provides suggested values for typical designs. The parameters listed are described in the following subsections. Table 5. Crystal Parameters Parameter Vibration Mode Nominal Frequency Frequency Tolerance Fundamental 25,000 MHz at 25° C (required) • ±30 ppm recommended; ±50 ppm across the entire operating temperature range as required by IEEE specifications • ±30 ppm required for the 82547GI(EI) Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Equivalent Series Resistance Drive Level Aging • ±50 ppm at 0° C to 70° C • ±30 ppm at 0° C to 70° C required for the 82547GI(EI) Parallel • 16 pF to 20 pF • 18 pF required for the 82547GI(EI) 6 pF maximum • 50 Ω maximum • 10 Ω maximum required for the 82547GI(EI) 0.5 mW maximum ±5 ppm per year maximum Suggested Value 7 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide .Table 6 lists the approved crystals for use with the 83547GI(EI) B1 steppings. Table 6. 82547GI(EI) Recommended Crystals Manufacturer Raltron (