GD82551QM

82551QM Fast Ethernet Multifunction PCI/CardBus Controller Networking Silicon - 82551QM Datasheet Product Features        Enhanced IP Protocol Support — TCP, UDP, IPv4 Checksum Offload — Received Checksum Verification Quality of Service (QoS) — Multiple Priority Transmit Queues Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — 32-bit PCI/CardBus master interface — Modem interface for combination solutions — Integrated power management functions — Thin BGA 15mm2 package PHY detects polarity, MDI-X, and cable lengths. Auto MDI/MDI-X crossover at all speeds XOR tree mode support Wired for Reduced Total Cost of Ownership (TCO) — Wired for Management support — Integrated Alert Standard Format — ACPI and PCI Power Management standards compliance — Wake on “interesting” packets and link status change support — Magic Packet* support — Remote power up support High Performance Networking Functions — Early release — 8255x controller family chained memory structure    — Improved dynamic transmit chaining with multiple priorities transmit queues — Full pin compatibility with the 82559 and 82550 controllers — Backward compatible software to the 8255x controller family (IPSec not supported) — Full Duplex support at 10 and 100 Mbps — IEEE 802.3u Auto-Negotiation support — 3 KB transmit and receive FIFOs — Fast back-to-back transmission support with minimum interframe spacing — IEEE 802.3x 100BASE-TX Flow Control support — Adaptive Technology Low Power Features — Advanced Power Management capabilities — Low power 3.3 V device — Efficient dynamic standby mode — Deep power down support — Clock Run protocol support 82551QM Enhancements — Improved Bit Error Rate performance — Integrated UNDI ROM support — HWI support — Deep power-down state power reduction Lead-free1 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUXXXXX. 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at VOUT > 0.1VCC 0.18VCC > VOUT > 0 VOUT = 0.18VCC -3 < VIN  -1 VCC + 4 > VIN  VCC + 1 -44 -17.1(VCC - VOUT) Eqn A -32VCC 95 VOUT/0.023 Eqn B 38VCC -25 + (VIN + 1)/0.015 25 + (VIN - VCC -1)/ 0.015 1 1 4 4 mA mA mA mA mA mA mA mA mA mA V/ns V/ns 1 1 2 2 1 1 2 2 3, 4 3 IOL(AC) ICL ICH slewRP slewFP Low Clamp Current High Clamp Current PCI Output Rise 0.4 V to 2.4 V Slew Rate PCI Output Fall Slew Rate 2.4 V to 0.4 V NOTES: 1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain outputs. 2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided. To facilitate component testing, a maximum current test point is defined for each side of the output driver. Equation A. Equation B. IOH = (98/VCC)*(Vout - VCC)*(Vout + 0.4VCC), for VCC > Vout > 0.7VCC IOL = (256/VCC)*(Vout)*(VCC - Vout), for 0 < Vout < 0.18VCC 3. This parameter is also applicable to CardBus environment. 4. Do not test. Guranteed by design. Datasheet 93 82551QM — Networking Silicon Table 73. AC Specifications for CardBus Signaling Symbol Parameter Condition Min Max Units Notes tRCB tFCB CardBus Output 0.2VCC to 0.6VCC Rise Time CardBus Output 0.6VCC to 0.2VCC Fall Time 0.25 0.25 1.0 1.0 V/ns V/ns 12.4 12.4.1 12.4.1.1 Timing Specifications Clocks Specifications PCI/CardBus Clock Specifications The 82551QM uses the PCI Clock signal directly. Figure 23 shows the clock waveform and required measurement points for the PCI Clock signal. Table 74 summarizes the PCI Clock specifications. Figure 23. PCI/CardBus Clock Waveform 0.6V CC 0.475VCC 0.4V CC 0.325V CC 0.2V CC 0.4V CC p-to-p (minimum) T_high T_cyc T_low Table 74. PCI/CardBus Clock Specifications Symbol Parameter Min Max Units Notes T1 T2 T3 T4 Tcyc Thigh Tlow Tslew CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate 30 11 11 1 4 ns ns ns V/ns 1 2 NOTES: 1. The 82551QM will work with any PCI clock frequency up to 33 MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 23. 94 Datasheet Networking Silicon — 82551QM 12.4.1.2 X1 Specifications X1 serves as a signal input from an external crystal or oscillator. Table 75 defines the 82551QM requirements from this signal. Table 75. X1 Clock Specifications Symbol Parameter Min Typical Max Units Notes T8 T9 Tx1_dc Tx1_pr X1 Duty Cycle X1 Period 40% 40 60% ns ±30PPM 12.4.2 12.4.2.1 Timing Parameters Measurement and Test Conditions Figure 24, Figure 25, and Table 76 define the conditions under which timing measurements are done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test conditions. Figure 24. Output Timing Measurement Conditions V_th CLK V_test V_tl T_val OUTPUT DELAY V_step Tri-State OUTPUT V_test V_test T_on T_off Datasheet 95 82551QM — Networking Silicon Figure 25. Input Timing Measurement Conditions V_th CLK T_su V_test V_tl T_h V_th INPUT V_tl V_test inputs valid V_test V_max Table 76. Measure and Test Condition Parameters Symbol PCI Level CardBus Level Units Notes Vth Vtl Vtest Vstep (rising edge) 0.6VCC 0.2VCC 0.4VCC 0.285VCC 0.6VCC 0.2VCC 0.4VCC 0.325VCC 0.475VCC 0.475VCC 0.325VCC 0.4VCC 1 V V V V V V V V V/ns Min Delay Max Delay Min Delay Max Delay Vstep (falling edge) Vmax Input Signal Edge Rate 0.615VCC 0.4VCC 1 NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for testing input timing. 96 Datasheet Networking Silicon — 82551QM 12.4.2.2 PCI/CardBus Timings Table 77. PCI/CardBus Timing Parameters Symbol Parameter Min Max Units Notes PCI CLK to Signal Valid Delay T14 T15 T16 T17 T18 T19 T20 T21 tval tval(ptp) ton toff tsu tsu(ptp) th trst CardBus CLK to Signal Valid Delay PCI CLK to Signal Valid Delay (pointto-point) Float to Active Delay Active to Float Delay Input Setup Time to CLK PCI Input Setup Time to CLK (point-topoint) Input Hold Time from CLK Reset Active Time After Power Stable PCI Reset Active Time After CLK Stable T22 Trst-clk CardBus Reset Active Time After CLK Stable Reset Active to Output Float Delay 2 2 2 2 11 18 12 ns ns ns ns 1, 2, 3 1, 7 1, 2, 3 1 1 3, 4 3, 4 5 5 5 5 5, 6 28 7 10 0 1 100 100 40 ns ns ns ns ms clocks clocks ns T23 Trst-off NOTES: 1. Timing measurement conditions are illustrated in Figure 24. 2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section 4.2.3.2. 3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times and input setup times than bussed signals. All other signals are bussed. 4. Timing measurement conditions are illustrated in Figure 25. 5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal. 6. All PCI and CardBus interface output drivers are floated when RST# is active. 7. CardBus minimum times are specified with a 0 pF equivalent load. Maximum times are specified with a 30 pF equivalent load. Actual test loads may vary but must be correlated to these loads. 12.4.2.3 Flash/Modem Interface Timings The 82551QM is designed to support up to 150 ns of Flash access time. The VPP signal in the Flash implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled only by the FLWE# pin. Table 78 provides the timing parameters for the Flash interface signals. The timing parameters are illustrated in Figure 26 and Figure 27. Modem is supported through the Flash interface when the following conditions apply: • FLA6:0, FLD7:0, FLCS#, FLOE#, and FLWE# have the same functions for Flash and modem. Datasheet 97 82551QM — Networking Silicon • FLA8 acts as IOCHRDY asynchronous input in modem mode. Table 78. Flash Timing Parameters Symbol Parameter Min Max Units Notes T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 tflrwc tflacc tflce tfloe tfldf tflas tflah tflcs tflch tflds tfldh tflwp tflwph tMioha tMiohi Flash Read/Write Cycle Time FLA to Read FLD Setup Time FLCS# to Read FLD Setup Time FLOE# Active to Read FLD Setup Time FLOE# Inactive to FLD Driven Delay Time FLA Setup Time before FLWE# FLA Hold Time after FLWE# FLCS# Hold Time before FLWE# FLCS# Hold Time after FLWE# FLD Setup Time FLD Hold Time Write Pulse Width Write Pulse Width High IOCHRDY Hold Time after FLWE# or FLOE# Active IOCHRDY Hold Time after FLWE# or FLOE# Inactive 150 150 150 120 50 5 200 30 30 150 10 120 25 25 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, Flash tAVAV = 150 ns 1, Flash tAVQV = 150 ns 1, Flash tELQV = 150 ns 1, Flash tGLQV = 55 ns 1, Flash tGHQZ = 35 ns 2, Flash tAVWL = 0 ns 2, Flash tWLAX = 60 ns 2, Flash tELWL = 20 ns 2, Flash tWHEH = 0 ns 2, Flash tDVWH = 50 ns 2, Flash tWHDX = 10 ns 2, Flash tWLWH = 60 ns 2, Flash tWHWL = 20 ns NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings. 98 Datasheet Networking Silicon — 82551QM Figure 26. Flash/Modem Timings for a Read Cycle FLADDR Address Stable T35 FLCS# T37 FLOE# T38 T36 T39 FLDATA-R T49 Data In T48 IOCHRDY Figure 27. Flash/Modem Timings for a Write Cycle T35 FLADDR Address Stable T40 T41 FLCS# T42 T46 T43 FLWE# T47 T44 T45 FLDATA-W T49 Data Out T48 IOCHRDY Datasheet 99 82551QM — Networking Silicon 12.4.2.4 EEPROM Interface Timings The 82551QM is designed to support a standard 64x16 or 256x16 serial EEPROM. Table 79 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 28. Table 79. EEPROM Timing Parameters Symbol Parameter Min Max Units Notes T51 T52 T53 T54 T55 tECSS tECSH tEDIS tEDIH tECS Delay from EECS High to EESK High Delay from EESK Low to EECS Low Setup Time of EEDI to EESK Hold Time of EEDI after EESK EECS Low Time 300 30 300 300 750 ns ns ns ns ns EEPROM tcss = 50 ns EEPROM tcsh = 0 ns EEPROM tdis = 150 ns EEPROM tdih = 150 ms EEPROM tcs = 250 ns Figure 28. EEPROM Timings EECS T51 T52 FLA15/EESK T53 T54 FLA13/EEDI 100 Datasheet Networking Silicon — 82551QM 12.4.2.5 PHY Timings Table 80. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Symbol Parameter Condition Min Typ Max Units T56 T57 Tnlp_wid Tnlp_per NLP Width NLP Period 10 Mbps 10 Mbps 8 100 24 ns ms Figure 29. 10BASE-T Normal Link Pulse (NLP) Timings T57 T56 Normal Link Pulse Table 81. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Symbol Parameter Min Typ Max Units T58 T59 T60 T61 T62 T63 Tflp_wid Tflp_clk_clk Tflp_clk_dat FLP Width (clock/data) Clock Pulse to Clock Pulse Period Clock Pulse to Data Pulse Period 111 55.5 17 100 125 62.5 139 69.5 33 2 8 24 ns µs µs Tflp_bur_num Number of Pulses in one burst Tflp_bur_wid Tflp_bur_per FLP Burst Width FLP Burst Period ms ms Figure 30. Auto-Negotiation Fast Link Pulse (FLP) Timings T59 T60 T58 Fast Link Pulse Clock Pulse T62 FLP Bursts Data Pulse Clock Pulse T63 Datasheet 101 82551QM — Networking Silicon Table 82. 100Base-TX Transmitter AC Specification Symbol Parameter Condition Min Typ Max Units T64 Tjit TDP/TDN Differential Output Peak Jitter HLS Data 1400 ps 12.4.2.6 SMB Interface Timings Table 83. Flash Timing Parameters Symbol Parameter Min Max Units Notes fsmb T84 T85 tdhs tdsus SMB Operating Frequency Data Hold Time Data Setup Time 300 250 1 MHz ns ns 102 Datasheet Networking Silicon — 82551QM 13.0 13.1 82551QM Test Port Functionality Introduction The 82551QM’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 13.2 Test Function Description The 82551QM TAP mode supports two tests that can be used in board level design. These tests help verify basic functionality as well as test the integrity of solder connection on the board. The tests are described in the following subsections. 13.2.1 Tristate The tristate command sets all 82551QM input and output pins into a tristate (high-Z) mode (all internal pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin combination and resetting the device: TEST = 1 TEXEC = 0 TCK = 0 TI = 1 Datasheet 103 82551QM — Networking Silicon 13.2.2 XOR Tree The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82551QM to be validated at board test. The XOR Tree was chosen for its speed advantages. Modern automated test equipment can perform a complete peripheral scan without support at the board level. This command connects all outputs of the input buffers in the device periphery into a XOR Tree scheme. All the output drivers of the output buffers, except the Test Port Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of the tree. There are two separate chains and associated outputs for speed. Any hard strapped pins will prevent the tester from scanning correctly. This mode is entered by placing the test pins in the following combination: TEST = 1 TEXEC = 1 TCK = 0 TI = 1 ISOLATE# = 1 Note: ISOLATE# must be driven high in order to enter test mode and must be kept high throughout the entire test. There are two XOR Tree chains with two separate outputs assigned to FLOE# (Chain 1) and FLWE# (Chain 2). Table 84. XOR Tree Chains Chain Order (XOR Tree Output) Chain 1 (FLOE#) Chain 2 (FLWE#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RST# IDSEL REQ# AD[23] SERR# AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] C/BE#[2] FRAME# IRDY# TRDY# CLK DEVSEL# INTA# STOP# GNT# PERR# LILED# ACTLED# SPDLED# ALTRST# CLK_RUN# AD[31] AD[30] AD[29] AD[28] AD[27] PME# AD[26] AD[25] C/BE#[3] AD[24] FLD0 104 Datasheet Networking Silicon — 82551QM Table 84. XOR Tree Chains Chain Order (XOR Tree Output) Chain 1 (FLOE#) Chain 2 (FLWE#) 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 37 39 40 41 42 43 44 45 46 PAR AD[16] C/BE#[1] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] C/BE#[0] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] EECS FLD1 FLD2 FLD3 FLD4 FLD5 FLD6 FLD7 FLA0 FLA1 FLA2 FLA3 FLA4 FLA5 FLA6 FLA7 FLA8 FLA9 FLA10 FLA11 FLA12 FLA13/EEDI FLA14/EEDO FLA15/EESK FLA16 FLCS# Datasheet 105 82551QM — Networking Silicon Note: This page is intentionally left blank. 106 Datasheet Networking Silicon — 82551QM 14.0 14.1 Package and Pinout Information Package Information The 82551QM is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 31. More information on Intel® device packaging is available in the Intel Packaging Handbook. Figure 31. Dimension Diagram for the 196-pin BGA 1.56 +/-0.19 0.85 30 o 0.40 +/-0.10 0.32 +/-0.04 Seating Plate Note: All dimensions are in millimeters. Substrate change from 0.36 mm to 0.32 mm Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Datasheet 107 82551QM — Networking Silicon Figure 32. 196 PBGA Package Pad Detail Detail Area 0.45 Solder Resist Opening 0.60 Metal Diameter As illustrated in Figure 32, the 82551QM package uses solder mask defined pads. The copper area is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50 mm. 108 Datasheet Networking Silicon — 82551QM 14.2 14.2.1 Pinout Information Pin Assignments Table 85. Pin Assignments Pin Name Pin Name Pin Name A1 A4 A7 A10 A13 B1 B4 B7 B10 B13 C1 C4 C7 C10 C13 D1 D4 D7 D10 D13 E1 E4 E7 E10 E13 F1 F4 F7 F10 F13 G1 G4 G7 NC IDSEL VCC SMBCLK TEST AD[22] AD[24] VSSPP SMB_ALERT#/ LAN_PWR_ GOOD RBIAS100 AD[21] C/BE#[3] AD[29] VSSPT TDP AD[18] VSS VSS NC TEXEC VCC VSS VSS VSS RDP IRDY# VSS VSS VSS FLD1 CLK NC VSS A2 A5 A8 A11 A14 B2 B5 B8 B11 B14 C2 C5 C8 C11 C14 D2 D5 D8 D11 D14 E2 E5 E8 E11 E14 F2 F5 F8 F11 F14 G2 G5 G8 SERR# AD[25] AD[30] VCC NC AD[23] AD[26] AD[31] SPDLED# RBIAS10 RST# CSTSCHG CLK_RUN# ACTLED# TDN AD[19] VSS VSS NC TCK VSSPP VSS VSS NC RDN FRAME# VSS VSS VSS FLD0 VIO VCC VSS A3 A6 A9 A12 VCC PME# ALTRST# LILED# B3 B6 B9 B12 VSSPP AD[27] ISOLATE# TO C3 C6 C9 C12 REQ# AD[28] SMBDATA VREF D3 D6 D9 D12 AD[20] VSS NC TI E3 E6 E9 E12 AD[17] VSS VSS VCC F3 F6 F9 F12 C/BE#[2] VSS VSS FLD2 G3 G6 G9 TRDY# VCC VSS Datasheet 109 82551QM — Networking Silicon Table 85. Pin Assignments Pin Name Pin Name Pin Name G10 G13 H1 H4 H7 H10 H13 J1 J4 J7 J10 J13 K1 K4 K7 K10 K13 L1 L4 L7 L10 L13 M1 M4 M7 M10 M13 N1 N4 N7 N10 N13 P1 P4 P7 P10 P13 VSS VCC STOP# NC VCC VSS FLD5 PAR NC VCC VCCR FLA0 AD[16] VCC VCC VCC VCC AD[14] VCC MDMCS# VCC FLA4 AD[11] C/BE#[0] AD[1] FLA15/EESK FLA7 VSSPP AD[7] AD[0] FLA14/EEDO FLA10 NC AD[6] EECS FLA13/EEDI FLA9 G11 G14 H2 H5 H8 H11 H14 J2 J5 J8 J11 J14 K2 K5 K8 K11 K14 L2 L5 L8 L11 L14 M2 M5 M8 M11 M14 N2 N5 N8 N11 N14 P2 P5 P8 P11 P14 VSS VSSPL INTA# VCC VCC NC FLD4 PERR# VCC VCC VCCR FLD7 VSSPP VCC VCC VCC FLA2 AD[15] VCC NC VSS FLA3 AD[12] AD[5] FLOE# FLA12 FLA6 AD[10] AD[4] VCC X1 FLA8/IOCHRDY VCC AD[3] VSSPL X2 NC G12 FLD3 H3 H6 H9 H12 DEVSEL# VCC VSS FLD6 J3 J6 J9 J12 GNT# VCC VCC FLA1 K3 K6 K9 K12 VCC VCC VCC VSSPL L3 L6 L9 L12 C/BE#[1] VSS VCC FLA5 M3 M6 M9 M12 AD[13] VSSPP FLWE# FLA11 N3 N6 N9 N12 AD[9] VCC FLCS# VSSPL P3 P6 P9 P12 AD[8] AD[2] FLA16 VCC 110 Datasheet Networking Silicon — 82551QM 14.2.2 Ball Grid Array Diagram Figure 33. Ball Grid Array Diagram A 1 NC B AD[22] C AD[21] D AD[18] E VCC F IRDY# G CLK H STOP# J PAR K AD[16] L AD[14] M AD[11] N VSSPP P NC 2 SERR# AD[23] RST# AD[19] VSSPP FRAME# VIO INTA# PERR# VSSPP AD[15] AD[12] AD[10] VCC 3 VCC VSSPP REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# VCC C/B3#[1] AD[13] AD[9] AD[8] 4 IDSEL AD[24] C/BE#[3] VSS VSS VSS NC NC NC VCC VCC C/BE#[0] AD[7] AD[6] 5 AD[25] AD[26] CSTSCHG VSS VSS VSS VCC VCC VCC VCC VCC AD[5] AD[4] AD[3] 6 PME# AD[27] AD[28] VSS VSS VSS VCC VCC VCC VCC VSS VSSPP VCC AD[2] 7 VCC VSSPP AD[29] VSS VSS VSS VSS VCC VCC VCC MDMCS# AD[1] AD[0] EECS 8 AD[30] AD[31] CLK_ RUN# VSS VSS VSS VSS VCC VCC VCC NC FLOE# VCC VSSPL 9 ALTRST# ISOLATE# SMBDATA NC VSS VSS VSS VSS VCC VCC VCC FLWE# FLCS# FLA16 10 SMBCLK SMB_ ALERT#/ LAN_PWR_ GOOD VSSPT NC VSS VSS VSS VSS VCCR VCC VCC FLA15/ EESK FLA14/ EEDO FLA13/ EEDI 11 VCC SPDLED# ACTLED# NC NC VSS VSS NC VCCR VCC VSS FLA12 X1 X2 12 LILED# TO VREF TI VCC FLD2 FLD3 FLD6 FLA1 VSSPL FLA5 FLA11 VSSPL VCC 13 TEST RBIAS 100 TDP TEXEC RDP FLD1 VCC FLD5 FLA0 VCC FLA4 FLA7 FLA10 FLA9 14 NC RBIAS 10 TDN TCK RDN FLD0 VSSPL FLD4 FLD7 FLA2 FLA3 FLA6 FLA8/ IOCHRDY NC Datasheet 111 82551QM — Networking Silicon 15.0 Reference Schematics This section shows a 10/100 Mbps design using the 82551QM Fast Ethernet Multifunction PCI/ CardBus Controller. 112 Datasheet Networking Silicon — 82551QM 3VSB The 82551IT can drive three LEDs with the cathode of each device connected to the 82551IT as shown with the SPEEDLED or a two LED configuration can be used, as shown. In the two LED configuration the link and the activity functions share an indicator. In this scheme the LINK LED would flash LOW each time activity is detected. LED 330 330 LILED ACTLED SPEEDLED A12 C11 B11 2 LED 1 This capacitor is normally not installed; however a placement can be provided. It might need to be placed based on the results of FCC conformance testing. If it is required, values in the pico fared range can be used. Large capacitance values installed in this location can have a negative effect on long cable performance. So care must be taken in selecting the values used. 8-22 pF Keep trace length from magnetics to RJ-45 connector under one inch. TDP C13 TDN C14 RDP E13 RDN E14 Keep all termination resistors as close to the 82551 as possible. 0.1 uF 2 1 2 1 1 2 Termplane Use plane for this signal to make a board capacitor. Termplane pF Optional capacitor to help with EFT Create termination plane in PCB. This plane conformance. acts as a path for low-frequency noise that might be coupled to unused pins. The plane should not have any direct connection. 0.1 uF CGND = Chassis ground Use plane for this signal 82551QM RD+ 1 RD2 0.1 uF uF RECEIVE 7 RX+ 5 CT 6 RX- MDI-X Mode Only RD+ 1 7 RX+ RDC 3 TD+ 16 1:1 TXCT 75 Ohms 10 TX+ RD2 6 RX- TDC 14 RECEIVE 11 TX1500pF 2kV 1:1 TD- 15 TD- 15 11 TX- TRANSMIT TD+ 16 MDI Mode Only TRANSMIT 1:1 10 TX+ 3VSB 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 Place decoupling capacitors as close to the 82551 as possible. If component placements are used on the bottom side of the board, then place decoupling under the 82551IT. Figure 34. Reference Schematic Layout (Sheet 1 of 2) Datasheet 2 4.7uF 4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1 0.1uF 113 82551QM — Networking Silicon PCI_5V 2) The voltage on VIO determines the slope of the signals on the bus. Although the device communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage. 1 100 K ohm 2 2 1 0.1uF 1) The decoupling capacitor should be added to the VIO pin. All Vcc pins are connected together on the PCB level. The power on the symbol is broken down between core power (Vcc), local bus power (Vccpl), transmit power (Vcct), and PCI power (Vccpp) just for clarity. G2 VIO 82551QM AD[31:0] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 TO PCI BUS FLA16 FLA15/EESK FLA14/EEDO FLA13/EEDI FL A12 FLA11 FLA10 FLA9 FLA8/IOCHRDY FLA7 FLA6 FLA5 FLA4 FLA3 FLA2 FLA1/AUXPWR F L A0 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0 EECS FLCS# FLCS# FLOE# FLWE# TEST TEXEC TCK TI TO VREF RBIAS10 RBIAS100 X1 P9 M10 N10 P10 M11 M12 N13 P13 N14 M13 M14 L12 L13 L14 K14 J12 J13 J14 H12 H13 H14 G12 F12 F13 F14 P7 N9 N9 M8 M9 A13 D13 D14 D12 B12 C12 B14 B13 N11 P11 2 1 EECS 3VSB VCC 3VSB 1 EEDI EEDO EESK 3 4 2 8 DI DO SK CS 1 3.3K 2 93C46 C/BE[3:0] C/BE0 C/BE1 C/BE2 C/BE3 FRAME# IRDY# TRDY# D E VSEL# S T O P# PAR INTA PERR# SERR# IDSEL R E Q# GNT# RST# CLK ISOLATE# AUX_GOOD PME# CLKRUN# M4 L3 F3 C4 F2 F1 G3 H3 H1 J1 H2 J2 A2 A4 C3 J3 C2 G1 B9 A9 A6 C5 C8 B10 A10 C9 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# IRDY# TRDY# DEVSEL# STOP# PAR INTA# PERR# SERR# IDSEL REQ# GNT# RST# CLK ISOLATE# ALTRS T # PME# CLKRUN# VREF: External VREF can be applied here if the internal reference is not used. The internal reference is recommended, but if an external reference is implemented, then this will cause the RBIAS values to change. 1 1 K ohm 1 619 1 649 2 2 RBIAS10 and RBIAS100 should be tuned for your specific application. The values shown are a good starting value. The ISOLATE signal should be a signal that X2 is driven low just prior to the PCI bus shutting down and it should be driven high immediately following the PCI bus re-activation. All Vss pins are connected together on the PCB level. The power on the symbol is broken down between core power (Vss), local bus power (Vsspl), transmit power (Vsst), and PCI power (Vsspp) just for clarity. 1 25 MHz 1 6 2 K ohm 2 Pulldown resistors are used on strapped pins to enable the NAND tree test mode to work. The value of 1 K ohm was chosen strictly on the basis of Intel’s test fixturing requirements Other values can be used, but it is recommended that resistors be used other than hard strapping the pins. 22 p F 1 2 PME# To PIIX4 Figure 35. Reference Schematic Layout (Sheet 2 of 2) 114 2 22 p F 2 Datasheet