GT28F320C3BD70

Intel£ Advanced+ Boot Block Flash Memory (C3) 28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ Flexible SmartVoltage Technology — 2.7 V– 3.6 V Read/Program/Erase — 12 V for Fast Production Programming 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option — Reduces Overall System Power High Performance — 2.7 V– 3.6 V: 70 ns Max Access Time Optimized Architecture for Code Plus Data Storage — Eight 4 Kword Blocks, Top or Bottom Parameter Boot — Up to One Hundred-Twenty-Seven 32 Kword Blocks — Fast Program Suspend Capability — Fast Erase Suspend Capability Flexible Block Locking — Lock/Unlock Any Block — Full Protection on Power-Up — WP# Pin for Hardware Block Protection Low Power Consumption — 9 mA Typical Read — 7 A Typical Standby with Automatic Power Savings Feature (APS) Extended Temperature Operation — –40 °C to +85 °C ■ ■ ■ ■ ■ ■ ■ 128-bit Protection Register — 64 bit Unique Device Identifier — 64 bit User Programmable OTP Cells Extended Cycling Capability — Minimum 100,000 Block Erase Cycles Software — Intel® Flash Data Integrator (FDI) — Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice) — Intel Basic Command Set — Common Flash Interface (CFI) Standard Surface Mount Packaging — 48-Ball µBGA*/VFBGA — 64-Ball Easy BGA Packages — 48-Lead TSOP Package ETOX™ VIII (0.13 µm) Flash Technology — 16, 32 Mbit ETOX™ VII (0.18 µm) Flash Technology — 16, 32, 64 Mbit ETOX™ VI (0.25 µm) Flash Technology — 8, 16 and 32 Mbit The Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest 0.13 µm and 0.18 µm technologies, represents a feature-rich solution for low-power applications. The C3 device incorporates low-voltage capability (3 V read, program, and erase) with highspeed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel® Flash Data Integrator (FDI) software and you have a costeffective, flexible, monolithic code plus data storage solution. Intel® Advanced+ Boot Block Flash Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel® Flash website: http://www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290645-017 October 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2003 *Third-party brands and names are the property of their respective owners. 2 Datasheet Contents Contents 1.0 Introduction ....................................................................................................................................7 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4 2.5 3.0 3.1 Document Purpose ...............................................................................................................7 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 Product Overview .................................................................................................................8 Ballout Diagram ....................................................................................................................8 Signal Descriptions .............................................................................................................13 Block Diagram ....................................................................................................................14 Memory Map .......................................................................................................................15 Bus Operations ...................................................................................................................17 3.1.1 Read ......................................................................................................................17 3.1.2 Write ......................................................................................................................17 3.1.3 Output Disable .......................................................................................................17 3.1.4 Standby..................................................................................................................18 3.1.5 Reset .....................................................................................................................18 Read Mode .........................................................................................................................19 4.1.1 Read Array.............................................................................................................19 4.1.2 Read Identifier .......................................................................................................19 4.1.3 CFI Query ..............................................................................................................20 4.1.4 Read Status Register.............................................................................................20 4.1.4.1 Clear Status Register .............................................................................21 Program Mode ....................................................................................................................21 4.2.1 12-Volt Production Programming...........................................................................21 4.2.2 Suspending and Resuming Program .....................................................................22 Erase Mode ........................................................................................................................22 4.3.1 Suspending and Resuming Erase .........................................................................23 Flexible Block Locking ........................................................................................................27 5.1.1 Locking Operation..................................................................................................28 5.1.1.1 Locked State ..........................................................................................28 5.1.1.2 Unlocked State.......................................................................................28 5.1.1.3 Lock-Down State....................................................................................28 Reading Block-Lock Status.................................................................................................28 Locking Operations during Erase Suspend ........................................................................29 Status Register Error Checking ..........................................................................................29 128-Bit Protection Register .................................................................................................29 5.5.1 Reading the Protection Register ............................................................................30 5.5.2 Programming the Protection Register....................................................................30 5.5.3 Locking the Protection Register .............................................................................30 VPP Program and Erase Voltages ......................................................................................30 Device Description ........................................................................................................................8 Device Operations .......................................................................................................................17 4.0 Modes of Operation .....................................................................................................................19 4.1 4.2 4.3 5.0 Security Modes ............................................................................................................................27 5.1 5.2 5.3 5.4 5.5 5.6 Datasheet 3 Contents 5.6.1 6.0 Program Protection................................................................................................ 31 Power Consumption.................................................................................................................... 32 6.1 6.2 6.3 6.4 6.5 Active Power (Program/Erase/Read).................................................................................. 32 Automatic Power Savings (APS) ........................................................................................ 32 Standby Power ................................................................................................................... 32 Deep Power-Down Mode.................................................................................................... 32 Power and Reset Considerations ....................................................................................... 33 6.5.1 Power-Up/Down Characteristics............................................................................ 33 6.5.2 RP# Connected to System Reset .......................................................................... 33 6.5.3 VCC, VPP and RP# Transitions ............................................................................ 33 Power Supply Decoupling................................................................................................... 34 Absolute Maximum Ratings ................................................................................................ 34 Operating Conditions .......................................................................................................... 35 DC Current Characteristics................................................................................................. 35 DC Voltage Characteristics................................................................................................. 38 AC Read Characteristics .................................................................................................... 39 AC Write Characteristics..................................................................................................... 43 Erase and Program Timings ............................................................................................... 47 Reset Specifications ........................................................................................................... 48 AC I/O Test Conditions ....................................................................................................... 49 Device Capacitance............................................................................................................ 49 6.6 7.0 7.1 7.2 7.3 7.4 8.0 8.1 8.2 8.3 8.4 8.5 8.6 Thermal and DC Characteristics ................................................................................................ 34 AC Characteristics ...................................................................................................................... 39 Appendix A Write State Machine States .............................................................................................50 Appendix B Flow Charts ......................................................................................................................52 Appendix C Common Flash Interface .................................................................................................58 Appendix D Mechanical Specifications ..............................................................................................64 Appendix E Additional Information ....................................................................................................67 Appendix F Ordering Information .......................................................................................................68 4 Datasheet Contents Revision History Date of Revision 05/12/98 Version -001 Original version 48-Lead TSOP package diagram change µBGA package diagrams change 32-Mbit ordering information change (Section 6) CFI Query Structure Output Table Change (Table C2) CFI Primary-Vendor Specific Extended Query Table Change for Optional Features and Command Support change (Table C8) Protection Register Address Change IPPD test conditions clarification (Section 4.3) µBGA package top side mark information clarification (Section 6) Byte-Wide Protection Register Address change VIH Specification change (Section 4.3) VIL Maximum Specification change (Section 4.3) ICCS test conditions clarification (Section 4.3) Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. Added tBHWH/tBHEH and tQVBL (Section 4.6) Programming the Protection Register clarification (Section 3.4.2) Removed all references to x8 configurations Removed reference to 40-Lead TSOP from front page Added Easy BGA package (Section 1.2) Removed 1.8 V I/O references Locking Operations Flowchart changed (Appendix B) Added tWHGL (Section 4.6) CFI Primary Vendor-Specific Extended Query changed (Appendix C) Max ICCD changed to 25 µA Table 10, added note indicating VCCMax = 3.3 V for 32-Mbit device Added specifications for 0.18 micron product offerings throughout document Added 64-Mbit density Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. 10/12/00 -010 Changed VccMax=3.3V reference to indicate that the affected product is the 0.25µm 32Mbit device. Minor text edits throughout document. Added 1.8v I/O operation documentation where applicable Added TSOP PCN ‘Pin-1’ indicator information Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’ 7/20/01 -011 Added ‘Vssq’ to Pin Descriptions Information Removed 0.4 µm references in DC characteristics table Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA Corrected ‘bottom’ parameter block sizes to on 8Mb device to 8 x 4KWords Minor text edits throughout document 10/02/01 2/05/02 -012 -013 Added specifications for 0.13 micron product offerings throughout document Corrected Iccw / Ippw / Icces /Ippes values. Added mechanicals for 16Mb and 64Mb Minor text edits throughout document. Description 07/21/98 -002 10/03/98 -003 12/04/98 12/31/98 02/24/99 -004 -005 -006 06/10/99 -007 03/20/00 04/24/00 -008 -009 Datasheet 5 Contents Date of Revision Version Updated 64Mb product offerings. Updated 16Mb product offerings. Description 4/05/02 -014 Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. 3/06/03 10/03 -016 -017 Complete technical update. Corrected information in the Device Geometry Details table, address 0x34. 6 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 1.0 1.1 Introduction Document Purpose This datasheet contains the specifications for the Intel® Advanced+ Boot Block Flash Memory (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. 1.2 Nomenclature 0x 0b Byte Word Kword Mword Kb KB Mb MB APS CUI OTP PR PRD PLR RFU SR SRD WSM Hexadecimal prefix Binary prefix 8 bits 16 bits 1024 words 1,048,576 words 1024 bits 1024 bytes 1,048,576 bits 1,048,576 bytes Automatic Power Savings Command User Interface One Time Programmable Protection Register Protection Register Data Protection Lock Register Reserved for Future Use Status Register Status Register Data Write State Machine 1.3 Conventions The terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (ball is the term used for CSP). Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4:1]) Set: When referring to registers, the term set means the bit is a logical 1. Clear: When referring to registers, the term clear means the bit is a logical 0. Block: A group of bits (or words) that erase simultaneously with one block erase instruction. Main Block: A block that contains 32 Kwords. Parameter Block: A block that contains 4 Kwords. Datasheet 7 Intel£ Advanced+ Boot Block Flash Memory (C3) 2.0 Device Description This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features, packaging, signal naming, and device architecture. 2.1 Product Overview The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks. The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated VPP input provides complete data protection when VPP ≤ VPPLK. The device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable OTP data registers. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. Additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status. A command User Interface(CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence issued to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. The device offers three low-power saving features: Automatic Power Savings (APS), standby mode, and deep power-down mode. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by deasserting CE#. The deep power-down mode begins when RP# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings. Combined, these three power-savings features significantly enhanced power consumption flexibility. 2.2 Ballout Diagram The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA packages. (Refer to Figure 1 on page 9, Figure 3 on page 11, and Figure 4 on page 12, respectively.) 8 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) Figure 1. 48-Lead TSOP Package A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 64 M 32 M Advanced+ Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW 16 M NOTES: 1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on Pins 9 and 10. Datasheet 9 Intel£ Advanced+ Boot Block Flash Memory (C3) Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP Current Mark: New Mark: Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel£ Advanced and Advanced + Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability. Product will continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes shown in Table 1. 48-Lead TSOP Extended 32 Mbit TE28F320C3TD70 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 Table 1. Extended 64 Mbit TE28F640C3TC80 TE28F640C3BC80 Extended 16 Mbit TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 Extended 8 Mbit TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 10 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package (Top View, Ball Down)1,2,3 1 2 3 4 5 16M 6 7 8 A A13 A11 A8 VPP WP# A19 A7 A4 B A14 A10 WE# 64M RP# 32M A21 A18 A17 A5 A2 C A15 A12 A9 A20 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 GND F GND D7 D13 D4 VCC D10 D1 OE# NOTES: 1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area. 2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 3. Unused address balls are not populated. Datasheet 11 Intel£ Advanced+ Boot Block Flash Memory (C3) Figure 4. 64-Ball Easy BGA Package1,2 1 A A1 B A2 C A3 D A4 E DQ8 DQ1 DQ9 DQ3 DQ12 DQ6 F CE# DQ0 DQ10 DQ11 DQ5 DQ14 DU G A0 H A22(2) OE# VCCQ VCC VSSQ DQ7 VCCQ DU VSSQ DQ2 DQ4 DQ13 DQ15 VSSQ A16 H DU VCCQ D7 VSSQ VCC VCCQ OE# A22(2) DU G A16 VSSQ D15 D13 DQ4 DQ2 VSSQ A0 DU DU F DU DU DQ14 DQ5 DQ11 DQ10 DQ0 CE# A5 DU DU DU DU A8 A9 E DU DU DQ6 DQ DQ3 DQ9 DQ1 DQ8 12 A7 WP# WE# DU A21(1) A12 A13 D A9 A8 DU DU DU DU A5 A4 A17 A19(1) RP# DU A20(1) A11 A14 C A13 A12 A21(1) DU WE# WP# A7 A3 A6 A18 VPP VCC GND A10 A15 B A14 A11 A20(1) DU RP# A19(1) A17 A2 2 3 4 5 6 7 8 A A15 A10 GND VCC VPP A18 A6 A1 8 7 6 5 4 3 2 1 Top View Ball Side - Bottom View - Ball Side NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. Unused address balls are not populated. 12 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 2.3 Signal Descriptions Table 2 lists the active signals used and provides a brief description of each. Table 2. Symbol Signal Descriptions Type Name and Function ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase cycle. A[MAX:0] INPUT 8 Mbit: AMAX= A18 16 Mbit: AMAX = A19 32 Mbit: AMAX = A20 64 Mbit: AMAX = A21 DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a Read operation. RESET/DEEP POWER-DOWN: Active-low input. DQ[15:0] INPUT/ OUTPUT CE# INPUT OE# INPUT RP# INPUT When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on the rising edge of the WE# pulse. WRITE PROTECT: Active-low input. WE# INPUT WP# INPUT When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to the lock-down state. See Section 5.0, “Security Modes” on page 27 for details on block locking. PROGRAM/ERASE POWER SUPPLY: Operates as an input at logic levels to control complete device protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. This pin cannot be left floating. VPP INPUT/ POWER Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands. Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5% to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for details on VPP voltage configurations. DEVICE CORE POWER SUPPLY: Supplies power for device operations. OUTPUT POWER SUPPLY: Output-driven source voltage. This ball can be tied directly to VCC if operating within VCC range. GROUND: For all internal circuitry. All ground inputs must be connected. DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or other balls, and must be left floating. NO CONNECT: Pin must be left floating. VCC VCCQ GND DU NC POWER POWER POWER - Datasheet 13 Intel£ Advanced+ Boot Block Flash Memory (C3) 2.4 Block Diagram DQ 0-DQ 15 VCCQ Output Buffer Input Buffer Outp ut M ulti ple xer Status Register Data Re gi ster Identifier Register I/O Logic CE# WE# OE# RP# WP# Power Reduction Control Data Comparator Command User Interface A[MAX:MIN] Y-Decoder Input Buffer 4 -KWor d Para mete r B loc k Y-Gating/Sensing 4 -KWor d Para mete r B loc k 32- KWord M ain Blo ck Write State Machine 32- KWord M ain Blo ck Program/Erase Voltage Switch VPP Address Latch X-Decoder VCC GND Address Counter 14 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 2.5 Memory Map The C3 device is asymmetrically blocked, which enables system code and data integration within a single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. See Table 3, “Top Boot Memory Map” on page 15 and Table 4, “Bottom Boot Memory Map” on page 16 for details. Table 3. Size (KW) Blk Top Boot Memory Map Size (KW) Blk 16-Mbit Memory Addressing (HEX) FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF ... 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) Blk 32-Mbit Memory Addressing (HEX) 1FF0001FFFFF 1FE0001FEFFF 1FD0001FDFFF 1FC0001FCFFF 1FB0001FBFFF 1FA0001FAFFF 1F90001F9FFF 1F80001F8FFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF ... 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) Blk 64-Mbit Memory Addressing (HEX) 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF ... 10000-17FFF 08000-0FFFF 00000-07FFF 8-Mbit Memory Addressing (HEX) 7F0007FFFF 7E0007EFFF 7D0007DFFF 7C0007CFFF 7B0007BFFF 7A0007AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF ... 10000-17FFF 8000-0FFFF 0000-07FFF 4 4 4 4 4 4 4 4 32 32 32 32 ... 32 32 32 22 21 20 19 18 17 16 15 14 13 12 11 ... 2 1 0 4 4 4 4 4 4 4 4 32 32 32 32 ... 32 32 32 38 37 36 35 34 33 32 31 30 29 28 27 ... 2 1 0 4 4 4 4 4 4 4 4 32 32 32 32 ... 32 32 32 70 69 68 67 66 65 64 63 62 61 60 59 ... 2 1 0 4 4 4 4 4 4 4 4 32 32 32 32 ... 32 32 32 134 133 132 131 130 129 128 127 126 125 124 123 ... 2 1 0 Datasheet 15 Intel£ Advanced+ Boot Block Flash Memory (C3) Table 4. Size (KW) 32 32 32 32 ... 32 32 32 4 4 4 4 4 4 4 4 Blk Bottom Boot Memory Map Size (KW) 32 32 32 32 ... 32 32 32 4 4 4 4 4 4 4 4 Blk 16-Mbit Memory Addressing (HEX) F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF ... 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32 32 32 32 ... 32 32 32 4 4 4 4 4 4 4 4 Blk 32-Mbit Memory Addressing (HEX) 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF ... 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32 32 32 32 . 32 32 32 4 4 4 4 4 4 4 4 Blk 64-Mbit Memory Addressing (HEX) 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF ... 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 8-Mbit Memory Addressing (HEX) 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF ... 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 22 21 20 19 ... 10 9 8 7 6 5 4 3 2 1 0 38 37 36 35 ... 10 9 8 7 6 5 4 3 2 1 0 70 69 68 67 ... 10 9 8 7 6 5 4 3 2 1 0 134 133 132 131 ... 10 9 8 7 6 5 4 3 2 1 0 16 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 3.0 Device Operations The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming. The internal WSM completely automates Program and Erase operations while the CUI signals the start of an operation and the status register reports device status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation. 3.1 Bus Operations The C3 device performs read, program, and erase operations in-system via the local CPU or microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of the flash device. Table 5 on page 17 summarizes these bus operations. Table 5. Bus Operations Mode RP# CE# OE# WE# DQ[15:0] Read Write Output Disable Standby Reset VIH VIH VIH VIH VIL VIL VIL VIL VIH X VIL VIH VIH X X VIH VIL VIH X X DOUT DIN High-Z High-Z High-Z NOTE: X = Don’t Care (VIL or VIH) 3.1.1 Read When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted. CE# is the device selection control; when active low, it enables the flash memory device. OE# is the data output control; when low, data is output on DQ[15:0]. See Figure 8, “Read Operation Waveform” on page 42. 3.1.2 Write A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever occurs first. See Figure 9, “Write Operations Waveform” on page 47. 3.1.3 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. DQ[15:0] are placed in a high-impedance state. Datasheet 17 Intel£ Advanced+ Boot Block Flash Memory (C3) 3.1.4 Standby Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during a Program or Erase operation, the device continues to consume active power until the Program or Erase operation is complete. 3.1.5 Reset From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See Figure 10, “Reset Operations Waveforms” on page 48. If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: 1. When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete. 2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH) or enter reset mode (if RP# is deasserted after tPLRH). See Figure 10, “Reset Operations Waveforms” on page 48. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL must be observed before a Read or Write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during a system reset. When the system comes out of reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel® Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 18 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 4.0 4.1 Modes of Operation Read Mode The flash memory has four read modes (read array, read identifier, read status, and CFI query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. Table 7, “Command Bus Operations” on page 24 and Table 8, “Command Codes and Descriptions” on page 25 summarize the commands used to reach these modes. Appendix A, “Write State Machine States” on page 50 is a comprehensive chart showing the state transitions. 4.1.1 Read Array When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output. • • • • WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read-array mode, as would be the case after a Program or Erase operation, the Read Array command (0xFF) must be issued to the CUI before array reads can occur. 4.1.2 Read Identifier The read-identifier mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 6 retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF). Datasheet 19 Intel£ Advanced+ Boot Block Flash Memory (C3) Table 6. Device Identification Codes Address1 Item Base Offset Data Description Manufacturer ID Block 0x00 0x0089 0x88C0 0x88C1 0x88C2 0x88C3 8-Mbit Top Boot Device 8-Mbit Bottom Boot Device 16-Mbit Top Boot Device 16-Mbit Bottom Boot Device 32-Mbit Top Boot Device 32-Mbit Bottom Boot Device 64-Mbit Top Boot Device 64-Mbit Bottom Boot Device Block is unlocked Block is locked Block is not locked-down Block is locked down Device ID Block 0x01 0x88C4 0x88C5 0x88CC 0x88CD Block Lock Status2 Block 0x02 DQ0 = 0b0 DQ0 = 0b1 DQ1 = 0b0 DQ1 = 0b1 Block Lock-Down Status2 Protection Register Lock Status Protection Register Block Block Block 0x02 0x80 0x81 0x88 Lock Data Register Data Multiple reads required to read the entire 128-bit Protection Register. NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 38 in a bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i.e. 0x0F8002. Then examine DQ0 of the data to determine if the block is locked. 2. See Section 5.2, “Reading Block-Lock Status” on page 28 for valid lock status. 4.1.3 CFI Query The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query Command (0x98). The CFI data structure contains information such as block size, density, command set, and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix C, “Common Flash Interface,” retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF). 4.1.4 Read Status Register The status register indicates the status of device operations, and the success/failure of that operation. The Read Status Register (0x70) command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the array, issue a Read Array (0xFF) command. The status-register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 0x00 when a Read Status Register command is issued. 20 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs last) which prevents possible bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register will not indicate completion of a Program or Erase operation. When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 9, “Status Register Bit Definition” on page 26). 4.1.4.1 Clear Status Register The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the Status Register. 4.2 Program Mode Programming is executed using a two-write cycle sequence. The Program Setup command (0x40) is issued to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a “0.” If users attempt to program “1”s, the memory cell contents do not change and no error occurs. The Status Register indicates programming status. While the program sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program-status bits should be checked. If the programming operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If SR[3] is set, then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR[1] is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status-register reads, be sure to reset the CUI to read-array mode. 4.2.1 12-Volt Production Programming When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control VPP. Figure 7 on page 31 shows examples of how the flash power supplies can be configured for various usage models. Datasheet 21 Intel£ Advanced+ Boot Block Flash Memory (C3) The 12 V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. 4.2.2 Suspending and Resuming Program The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, issuing the Program Suspend command to the CUI requests that the WSM suspend the program sequence at predetermined points in the program algorithm. The device continues to output status-register data after the Program Suspend command is issued. Polling status-register bits SR[7] and SR[2] will determine when the program operation has been suspended (both will be set to “1”). tWHRH1/ tEHRH1 specify the program-suspend latency. A Read-Array command can now be issued to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume. After the Program Resume command is issued to the flash memory, the WSM will continue with the programming process and status register bits SR[2] and SR[7] will automatically be cleared. The device automatically outputs status register data when read (see Figure 14, “Program Suspend / Resume Flowchart” on page 53) after the Program Resume command is issued. VPP must remain at the same VPP level used for program while in program-suspend mode. RP# must also remain at VIH. 4.3 Erase Mode To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.” When the status register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the status register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR[5] of the status register is set to indicate an erase error, and SR[3] is set to a “1” to identify that VPP supply voltage was not within acceptable limits. After an Erase operation, clear the status register (0x50) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent statusregister reads, it is advisable to place the flash in read-array mode after the erase is complete. 22 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 4.3.1 Suspending and Resuming Erase Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from—or program data to— another block in memory. Once the erase sequence is started, issuing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the Erase operation has been suspended. Erase-suspend latency is specified by tWHRH2/tEHRH2. A Read Array or Program command can now be issued to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The only valid commands while Erase is suspended are Read Status Register, Read Identifier, CFI Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH, which reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a standard Erase operation, the status register should be read and cleared before the next instruction is issued. Datasheet 23 Intel£ Advanced+ Boot Block Flash Memory (C3) Table 7. Command Bus Operations First Bus Cycle Command Notes Oper Addr Data Oper Addr Data Second Bus Cycle Read Array Read Identifier CFI Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program 1,3 1,3 1,3 1,3 1,3 2,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3 Write Write Write Write Write Write Write Write Write Write Write Write Write X X X X X X X X X X X X X 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0x20 0xB0 0xD0 0x60 0x60 0x60 0xC0 Write Write Write Write BA BA BA PA 0x01 0xD0 0x2F PD Write Write PA BA PD D0H Read Read Read IA QA X ID QD SRD X = "Don’t Care" SRD = Status Reg. Data PA = Prog Addr PD = Prog Data BA = Block Addr IA = Identifier Addr. ID = Identifier Data QA = Query Addr. QD = Query Data NOTES: 1. Following the Read Identifier or CFI Query commands, read operations output device identification data or CFI query information, respectively. See Section 4.1.2 and Section 4.1.3. 2. Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40. 3. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current draw. Bus operations are defined in Table 5, “Bus Operations” on page 17. 24 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) Table 8. Code (HEX) Command Codes and Descriptions Device Mode Command Description FF Read Array This command places the device in read-array mode, which outputs array data on the data pins. This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 4.2, “Program Mode” on page 21. This is a two-cycle command. Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,” (b) place the device into the read-status-register mode, and (c) wait for another command. See Section 4.3, “Erase Mode” on page 22. If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches and begin erasing the block indicated on the address pins. During program/ erase, the device will respond only to the Read Status Register, Program Suspend and Erase Suspend commands, and will output status-register data when CE# or OE# is toggled. If a Program or Erase operation was previously suspended, this command will resume that operation. If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock the block indicated on the address pins. If the block had been previously set to Lock-Down, this operation will have no effect. (See Section 5.1) Issuing this command will begin to suspend the currently executing Program/Erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit SR[7] to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input-control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and 3.2.6.1. This command places the device into read-status-register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a Program or Erase operation has been initiated. See Section 4.1.4, “Read Status Register” on page 20. The WSM can set the block-lock status SR[1], VPP Status SR[3], program status SR[4], and erase-status SR[5] bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.” Puts the device into the read-identifier mode so that reading the device will output the manufacturer/device codes or block-lock status. See Section 4.1.2, “Read Identifier” on page 19. Prepares the CUI for block-locking changes. If the next command is not Block Unlock, Block Lock, or Block Lock-Down, then the CUI will set both the program and erase-status-register bits to indicate a command-sequence error. See Section 5.0, “Security Modes” on page 27. If the previous command was Lock Set-Up, the CUI will latch the address and lock the block indicated on the address pins. (See Section 5.1) If the previous command was a Lock-Down Set-Up command, the CUI will latch the address and lock-down the block indicated on the address pins. (See Section 5.1) Puts the device into the CFI-Query mode so that reading the device will output Common Flash Interface information. See Section 4.1.3 and Appendix C, “Common Flash Interface”. This is a two-cycle command. The first cycle prepares the CUI for a program operation to the protection register. The second cycle latches addresses and data information and initiates the WSM to execute the Protection Program algorithm to the protection register. The flash outputs status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 5.5. 40 Program Set-Up 20 Erase Set-Up Erase Confirm D0 Program/Erase Resume Unlock Block B0 Program Suspend Erase Suspend 70 Read Status Register Clear Status Register Read Identifier Block Lock, Block Unlock, Block Lock-Down SetUp Lock-Block Lock-Down CFI Query Protection Program Set-Up 50 90 60 01 2F 98 C0 Datasheet 25 Intel£ Advanced+ Boot Block Flash Memory (C3) Table 8. Code (HEX) Command Codes and Descriptions Device Mode Command Description 10 00 Alt. Prog Set-Up Invalid/ Reserved Operates the same as Program Set-up command. (See 0x40/Program Set-Up) Unassigned commands should not be used. Intel reserves the right to redefine these codes for future functions. NOTE: See Appendix A, “Write State Machine States” for mode transition information. Table 9. WSMS 7 Status Register Bit Definition ESS 6 ES 5 PS 4 VPPS 3 PSS 2 NOTES: BLS 1 R 0 SR[7] WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR[6] = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR[5] = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase SR[4] = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking program or erasestatus bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an Erase Resume command is issued. When this bit is set to “1,” WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to “1,” WSM has attempted but failed to program a word/byte. The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1Min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register. SR[3] = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR[2] = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR[1] = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTE: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set. 26 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 5.0 5.1 Security Modes Flexible Block Locking The C3 device offers an instant, individual block-locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term “state [abc]” will be used to specify locking states; e.g., “state [001],” where a = value of WP#, b = bit D1 of the Block Lock status register, and c = bit D0 of the Block Lock status register. Figure 5, “Block Locking State Diagram” on page 27 displays all of the possible locking states. Figure 5. Block Locking State Diagram Power-Up/Reset Locked [X01] LockedDown4,5 [011] Hardware Locked5 [011] WP# Hardware Control Unlocked [X00] Software Locked [111] Unlocked [110] Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care. 2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to this block. D1 = ‘1’, Lock-down has been issued to this block. 3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states. Datasheet 27 Intel£ Advanced+ Boot Block Flash Memory (C3) 5.1.1 Locking Operation The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See Figure 5, “Block Locking State Diagram” on page 27 and Figure 17, “Locking Operations Flowchart” on page 56. The following concisely summarizes the locking functionality. 5.1.1.1 Locked State The default state of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked block will return an error on bit SR[1] of the Status Register. The state of a locked block can be changed to Unlocked or Lock Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 0x60 followed by 0x01. 5.1.1.2 Unlocked State Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 0x60 followed by 0xD0. 5.1.1.3 Lock-Down State Blocks that are Locked-Down (state [011]) are protected from Program and Erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked Down by writing the Lock-Down command sequence, 0x60 followed by 0x2F. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down function is disabled ([111]) and Locked-Down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low, blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state. 5.2 Reading Block-Lock Status The Lock status of each block can be read in read-identifier mode of the device by issuing the readidentifier command (0x90). Subsequent reads at Block Address + 0x00002 will output the Lock status of that block. The Lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock Down. DQ1 indicates Lock-Down status, and is set by the Lock-Down command. It cannot be cleared by software—only by device reset or power-down. See Table 6, “Device Identification Codes” on page 20 for block-status information. 28 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 5.3 Locking Operations during Erase Suspend Changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case when another block needs to be updated while an Erase operation is in progress. To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0), then check the status register until it indicates that the Erase operation has been suspended. Next, write the preferred Lock command sequence to a block and the Lock status will be changed. After completing any preferred Lock, Read, or Program operations, resume the Erase operation with the Erase Resume command (0xD0). If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking status bits will be changed immediately. But when the Erase is resumed, the Erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write State Machine States” on page 50 for detailed information on which commands are valid during Erase Suspend. 5.4 Status Register Error Checking Using nested-locking or program-command sequences during Erase Suspend can introduce ambiguity into status register results. Since locking changes are performed using a two-cycle command sequence, e.g., 0x60 followed by 0x01 to lock a block, following the Block Lock, Block Unlock, or Block Lock-Down Setup command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and SR[5] will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase Suspend, SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is complete, any possible error during the Erase cannot be detected via the status register because of the previous Lock-Command error. A similar situation happens if an error occurs during a Program-Operation error nested within an Erase Suspend. 5.5 128-Bit Protection Register The C3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to “match” the flash component with other system components, such as the CPU or ASIC, preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent further programming. Datasheet 29 Intel£ Advanced+ Boot Block Flash Memory (C3) 5.5.1 Reading the Protection Register The protection register is read in the read-identifier mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Figure 6, “Protection Register Mapping” retrieve the specified information. To return to readarray mode, issue the Read Array command (0xFF). 5.5.2 Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data, and program the specified location. The allowable addresses are shown in Table 6, “Device Identification Codes” on page 20. See Figure 18, “Protection Register Programming Flowchart” on page 57. Attempts to address Protection Program commands outside the defined protection register address space should not be attempted. Attempting to program to a previously locked protection register segment will result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). 5.5.3 Locking the Protection Register The user-programmable segment of the protection register is lockable by programming bit 1 of the PR-LOCK location to 0. See Figure 6, “Protection Register Mapping” on page 30. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout state is not reversible. Figure 6. Protection Register Mapping 0x88 64-bit Segment (User-Programmable) 0x85 0x84 128-Bit Protection Register 0 64-bit Segment (Intel Factory-Programmed) 0x81 PR Lock Register 0 0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5.6 VPP Program and Erase Voltages The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast production programming, 12 V programming can be used. Refer to Figure 7, “Example Power Supply Configurations” on page 31. 30 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) 5.6.1 Program Protection In addition to the flexible block locking, the VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When VPP is below or equal to VPPLK, any Program or Erase operation will result in an error, prompting the corresponding status-register bit (SR[3]) to be set. Figure 7. Example Power Supply Configurations System Supply 12 V Supply 10 ≤ KΩ 12 V Fast Programming Absolute Write Protection With V System Supply (Note 1) System Supply VCC VPP Prot# (Logic Signal) VCC VPP Low-Voltage Programming ≤ V PPLK PP Absolute Write Protection via Logic Signal System Supply VCC VPP VCC VPP Low-Voltage Programming 0645_06 12 V Supply Low Voltage and 12 V Fast Programming NOTE: 1. A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture for details. Datasheet 31 Intel£ Advanced+ Boot Block Flash Memory (C3) 6.0 Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep powerdown mode for ultra-low current consumption. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 6.1 Active Power (Program/Erase/Read) With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. 6.2 Automatic Power Savings (APS) Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are idle, APS circuitry places the device in a mode where typical current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read. 6.3 Standby Power When CE# is at a logic-high level (VIH), the flash memory is in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logichigh level during Erase or Program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time, and quantify the respective power consumption in each mode for their specific application. This approach will provide a more accurate measure of application-specific power and energy requirements. 6.4 Deep Power-Down Mode The deep power-down mode is activated when RP# = VIL. During read modes, RP# going low deselects the memory and places the outputs in a high-impedance state. Recovery from deep powerdown requires a minimum time of tPHQV for Read operations, and tPHWL/tPHEL for Write operations. 32 Datasheet Intel£ Advanced+ Boot Block Flash Memory (C3) During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register). 6.5 6.5.1 Power and Reset Considerations Power-Up/Down Characteristics In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must powerdown together. It is also recommended to power-up VPP with or after VCC has reached VCCmin. Conversely, VPP must powerdown with or slightly before VCC. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCmin before applying VCCQ and VPP. Device inputs should not be driven before supply voltage reaches VCCmin. Power supply transitions should only occur when RP# is low. 6.5.2 RP# Connected to System Reset The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 6.5.3 VCC, VPP and RP# Transitions The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after VCC transitions above VLKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read-array mode via the Read Array command if access to the flash-memory array is desired. Datasheet 33 Intel£ Advanced+ Boot Block Flash Memory (C3) 6.6 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues: • Standby current levels (ICCS) • Read current levels (ICCR) • Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND, and between its VPP and VSS. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.0 7.1 Warning: . Thermal and DC Characteristics Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Parameter Maximum Rating Notes Extended Operating Temperature During Read During Block Erase and Program Temperature under Bias Storage Temperature Voltage On Any Pin (except VCC and VPP) with Respect to GND VPP Voltage (for Block Erase and Program) with Respect to GND VCC and VCCQ Supply Voltage with Respect to GND Output Short Circuit Current –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –65 °C to +125 °C –0.5 V to +3.7 V –0.5 V to +13.5 V –0.2 V to +3.6 V 100 mA 4 1 1,2,3 NOTES: 1. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V for periods