GT28F800B3-B150

E n n n PRELIMINARY SMART 3 ADVANCED BOOT BLOCK WORD-WIDE 4-MBIT (256K X 16), 8-MBIT (512K X 16), 16-MBIT (1024K X 16) FLASH MEMORY FAMILY 28F400B3, 28F800B3, 28F160B3 Flexible SmartVoltage Technology  2.7V–3.6V Program/Erase  2.7V–3.6V Read Operation  12V VPP Fast Production Programming 2.7V or 1.8V I/O Option  Reduces Overall System Power Optimized Block Sizes  Eight 4-KW Blocks for Data, Top or Bottom Locations  Up to Thirty-One 32-KW Blocks for Code High Performance  2.7V–3.6V: 120 ns Max Access Time Block Locking  VCC-Level Control through WP# Low Power Consumption  20 mA Maximum Read Current Absolute Hardware-Protection  VPP = GND Option  VCC Lockout Voltage Extended Temperature Operation  –40°C to +85°C n n n n n n n n n Supports Code Plus Data Storage  Optimized for FDI, Flash Data Integrator Software  Fast Program Suspend Capability  Fast Erase Suspend Capability Extended Cycling Capability  10,000 Block Erase Cycles Automated Word Program and Block Erase  Command User Interface  Status Registers SRAM-Compatible Write Interface Automatic Power Savings Feature Reset/Deep Power-Down  1 µA ICCTypical  Spurious Write Lockout Standard Surface Mount Packaging  48-Ball µBGA* Package  48-Lead TSOP Package Footprint Upgradeable  Upgradeable from 2-, 4- and 8-Mbit Boot Block ETOX™ V (0.4 µ) Flash Technology n n n n n The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device. Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective, monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Word-Wide products will be available in 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp. May 1997 Order Number: 290580-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400B3, 28F800B3, 28F160B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\www.intel.com COPYRIGHT © INTEL CORPORATION 1996, 1997 *Third-party brands and names are the property of their respective owners CG-041493 E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE CONTENTS PAGE 1.0 INTRODUCTION .............................................5 1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements ..............................5 1.2 Product Overview.........................................6 2.0 PRODUCT DESCRIPTION..............................6 2.1 Package Pinouts ..........................................7 2.2 Block Organization .....................................11 2.2.1 Parameter Blocks ................................11 2.2.2 Main Blocks .........................................11 3.0 PRINCIPLES OF OPERATION .....................14 3.1 Bus Operation ............................................14 3.1.1 Read....................................................15 3.1.2. Output Disable....................................15 3.1.3 Standby ...............................................15 3.1.4 Deep Power-Down / Reset ..................15 3.1.5 Write....................................................15 3.2 Modes of Operation....................................15 3.2.1 Read Array ..........................................16 3.2.2 Read Intelligent Identifier .....................17 3.2.3 Read Status Register ..........................17 3.2.4 Program Mode.....................................18 3.2.5 Erase Mode .........................................19 3.3 Block Locking.............................................26 3.3.1 VPP = VIL for Complete Protection .......26 3.3.2 WP# = VIL for Block Locking................26 3.3.3 WP# = VIH for Block Unlocking ............26 3.4 VPP Program and Erase Voltages ..............26 PAGE 3.5 Power Consumption ...................................26 3.5.1 Active Power .......................................26 3.5.2 Automatic Power Savings (APS) .........27 3.5.3 Standby Power ....................................27 3.5.4 Deep Power-Down Mode.....................27 3.6 Power-Up/Down Operation.........................27 3.6.1 RP# Connected to System Reset ........27 3.6.2 VCC, VPP and RP# Transitions .............27 3.7 Power Supply Decoupling ..........................28 3.7.1 VPP Trace On Printed Circuit Boards ...28 4.0 ABSOLUTE MAXIMUM RATINGS ................29 5.0 OPERATING CONDITIONS (VCCQ = 2.7V– 3.6V) .............................................................29 5.1 DC Characteristics: VCCQ = 2.7V–3.6V.......30 6.0 OPERATING CONDITIONS (VCCQ = 1.8V– 2.2V) .............................................................34 6.1 DC Characteristics: VCCQ = 1.8V–2.2V.......34 7.0 AC CHARACTERISTICS...............................39 7.1 Reset Operations .......................................43 APPENDIX A: Ordering Information .................45 APPENDIX B: Write State Machine Current/Next States.....................................46 APPENDIX C: Access Speed vs. Capacitive Load .............................................................47 APPENDIX D: Architecture Block Diagram ......48 APPENDIX E: Additional Information ...............49 PRELIMINARY 3 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E REVISION HISTORY Number -001 -002 Original version Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program op. to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) IPPR maximum specification change from ±25 µA to ±50 µA Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8M and 4M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in Words not bytes) Minor wording changes Description 4 PRELIMINARY E 1.0 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE convenient upgrade from and/or compatibility to previous 4-Mbit and 8-Mbit Boot Block products. The Smart 3 product functions are similar to lower density products in both command sets and operation, providing similar pinouts to ease density upgrades. The Smart 3 Advanced Boot Block flash memory features • • • Enhanced blocking for easy segmentation of code and data or additional design flexibility Program Suspend command which permits program suspend to read WP# pin to lock and unlock the upper two (or lower two, depending on location) 4-Kword blocks VCCQ input for 1.8V–2.2V on all I/Os. See Figure 1-4 for pinout diagrams and VCCQ location Maximum program time improved data storage. specification for INTRODUCTION This preliminary datasheet contains the specifications for the Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features 1.8V–2.2V or 2.7V–3.6V I/Os and a low VCC/VPP operating range of 2.7V–3.6V for read and program/erase operations. In addition this family is capable of fast programming at 12V. Throughout this document, the term “2.7V” refers to the full voltage range 2.7V–3.6V (except where noted otherwise) and “VPP = 12V” refers to 12V ±5%. Section 1 and 2 provides an overview of the flash memory family including applications, pinouts and pin descriptions. Section 3 describes the memory organization and operation for these products. Finally, Sections 4, 5, 6 and 7 contain the operating specifications. • 1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements • The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3 Advanced Boot Block flash memory provides a Table 1. Smart 3 Advanced Boot Block Feature Summary Feature VCC Read Voltage VCCQ I/O Voltage VPP Program/Erase Voltage Bus Width Speed Memory Arrangement Blocking (top or bottom) 2.7V– 3.6V 1.8V–2.2V or 2.7V– 3.6V 2.7V– 3.6V or 11.4V– 12.6V 16 bit 120 ns 256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit), 1024-Kbit x 16 (16-Mbit) Eight 4-Kword parameter blocks (4/8/16) & Seven 32-Kword blocks (4-Mbit) Fifteen 32-Kword blocks (8-Mbit) Thirty-one 32-Kword main blocks (16-Mbit) WP# locks/unlocks parameter blocks All other blocks protected using V PP switch Extended: –40°C to +85°C 10,000 cycles 48-Lead TSOP, 48-Ball µBGA* CSP Section 2.2 Figures 5 and 6 28F160B3 Reference Table 9, Table 12 Table 9, Table 12 Table 9, Table 12 Table 2 Table 15 Locking Operating Temperature Program/Erase Cycling Packages Section 3.3 Table 8 Table 9, Table 12 Table 9, Table 12 Figures 1, 2, 3, and 4 5 PRELIMINARY SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 1.2 Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design. All Smart 3 Advanced Boot Block flash memory products provide program/erase capability at 2.7V or 12V and read with VCC at 2.7V. Since many designs read from the flash memory a large percentage of the time, 2.7V VCC operation can provide substantial power savings. The 12V VPP option maximizes program and erase performance during production programming. The Smart 3 Advanced Boot Block flash memory products are high-performance devices with low power operation. The available densities for wordwide devices (x16) are a. 4-Mbit (4,194,304-bit) flash memory organized as 256-Kwords of 16 bits each b. 8-Mbit (8,388,608-bit) flash memory organized as 512-Kwords of 16 bits each c. 16-Mbit (16,777,216-bit) flash memory organized as 1024-Kwords of 16 bits each. For byte-wide devices (x8) see the Smart 3 Advanced Boot Block Byte-Wide Flash Memory Family datasheet. The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. Program and erase automation allows program and erase operations to be executed using an industrystandard two-write command sequence to the CUI. Data writes are performed in word increments. Each word in the flash memory can be programmed independently of other memory locations; every erase operation erases all locations within a block simultaneously. Program suspend allows system software to suspend the program command in order to read from any other block. Erase suspend allows system software to suspend the block erase command in order to read from or program data to any other block. The Smart 3 Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered immediately following the completion of a read cycle. When the CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. A deep powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power-down is 1 µA typical (2.7V VCC). A minimum reset time of tPHQV is required from RP# switching high until outputs are valid to read attempts. With RP# at GND, the WSM is reset and Status Register is cleared. Section 3.5 contains additional information on using the deep power-down feature, along with other power consumption issues. The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6). Refer to the DC Characteristics Table, Sections 5.1 and 6.1, for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 7.0, for read, program and erase performance specifications. E 2.0 PRODUCT DESCRIPTION This section explains device pin description and package pinouts. 6 PRELIMINARY E 2.1 A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC WE# RP# V PP WP# NC NC A 17 A7 A6 A5 A4 A3 A2 A1 A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC WE# RP# V PP WP# NC A 18 A 17 A7 A6 A5 A4 A3 A2 A1 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Package Pinouts The Smart 3 Advanced Boot Block flash memory is available in 48-lead TSOP (see Figure 1) and 48ball µBGA packages (see Figures 2-4). In Figure 1, pin changes from one density to the next are circled. Both packages, 48-lead TSOP and 48-ball µBGA* package, are 16-bits wide and fully upgradeable across product densities (from 4 Mb to 16 Mb). 28F400B3 28F800B3 A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC WE# RP# V PP WP# A 19 A 18 A 17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A 16 VCCQ GND DQ15 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0 28F800B3 28F400B3 A 16 VCCQ GND DQ15 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0 A 16 VCCQ GND DQ15 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0 0580_01 16-Mbit Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW Figure 1. 48-Lead TSOP Package PRELIMINARY 7 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E 5 6 7 8 NC A7 A4 A17 A5 A2 A6 A3 A1 D8 CE# A0 D9 D0 GND 1 2 3 4 A A13 A11 A8 VPP WP# B A14 A10 WE# RP# NC C A15 A12 A9 D A16 D14 D5 D11 D2 E VCCQ D15 D6 D12 D3 F GND D7 D13 D4 VCC D10 D1 OE# 0580_02 NOTE: Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package 1 2 3 4 5 6 7 8 A A13 A11 A8 VPP WP# NC A7 A4 B A14 A10 WE# RP# A18 A17 A5 A2 C A15 A12 A9 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 GND F GND D7 D13 D4 VCC D10 D1 OE# 0580_03 NOTE: Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package 8 PRELIMINARY E 1 2 3 A A13 A11 A8 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 4 5 6 7 8 VPP WP# A19 A7 A4 B A14 A10 WE# RP# A18 A17 A5 A2 C A15 A12 A9 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 GND F GND D7 D13 D4 VCC D10 D1 OE# 0580_04 NOTE: Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. Figure 4. 16-Mbit 48-Ball µBGA* Chip Size Package (Top View, Ball Down) PRELIMINARY 9 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE The pin descriptions table details the usage of each device pin. Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions Symbol A0–A19 Type INPUT Name and Function E ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19] DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and intelligent identifier data. The data pins float to tri-state when the chip is de-selected. CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# inputs. OUTPUT ENABLE: Enables the device’s outputs through the data buffers during an array or status register read. OE# is active low. WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RESET/DEEP POWER-DOWN: Uses two voltage levels (V IL, VIH) to control reset/deep power-down mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation . When RP# transitions from logic-low to logic-high, the device defaults to the read array mode. DQ0–DQ7 INPUT/OUTPUT DQ8–DQ15 INPUT/OUTPUT CE# INPUT OE# WE# INPUT INPUT RP# INPUT WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked , preventing program and erase operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed. When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 3.3 for details on write protection. 10 PRELIMINARY E Symbol VCCQ VCC VPP SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued) Type INPUT Name and Function OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the VCC is at 2.7V. When this mode is used, the V CC should be regulated to 2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC Characteristics: VCCQ = 1.8V–2.2V). This input may be tied directly to V CC (2.7V–3.6V). See the DC Characteristics for further details. DEVICE POWER SUPPLY: 2.7V–3.6V PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage of either 2.7V–3.6V or 12V ± 5% must be applied to this pin. When V PP < VPPLK all blocks are locked and protected against Program and Erase commands. Applying 11.4V-12.6V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum (see Section 3.4 for details). GND NC GROUND: For all internal circuitry. All ground inputs must be connected. NO CONNECT: Pin may be driven or left floating. 2.2 Block Organization 2.2.1 PARAMETER BLOCKS The Smart 3 Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 10,000 times. For the address locations of each block, see the memory maps in Figure 5 (top boot blocking) and Figure 6 (bottom boot blocking). The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the wordrewrite functionality of EEPROMs can be emulated. Each 4-/8-/16-Mbit device contains eight parameter blocks of 4-Kwords (4,096-words) each. 2.2.2 MAIN BLOCKS After the parameter blocks, the remainder of the array is divided into equal size main blocks for data or code storage. Each 16-Mbit device contains thirty-one 32-Kword (32,768-word) blocks. Each 8-Mbit device contains fifteen 32-Kword blocks. Each 4-Mbit device contains seven 32-Kword blocks. PRELIMINARY 11 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E 4-Mbit Advanced Boot Block 3FFFF 3F000 3EFFF 3E000 3DFFF 3D000 3CFFF 3C000 3BFFF 3B000 3AFFF 3A000 39FFF 39000 38FFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 16-Mbit Advanced Boot Block FFFFF FF000 FEFFF FE000 FDFFF FD000 FCFFF FC000 FBFFF FB000 FAFFF FA000 F9FFF F9000 F8FFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7000 B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000 8-Mbit Advanced Boot Block 7FFFF 7F000 7EFFF 7E000 7DFFF 7D000 7CFFF 7C000 7BFFF 7B000 7AFFF 7A000 79FFF 79000 78FFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0580_05 Figure 5. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps 12 PRELIMINARY E 16-Mbit Advanced Boot Block FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 8-Mbit Advanced Boot Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 4-Mbit Advanced Boot Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0580_06 Figure 6. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps PRELIMINARY 13 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 3.0 PRINCIPLES OF OPERATION Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The Smart 3 Advanced Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs, fixed power supplies during erasure and programming, and maximum EEPROM compatibility. When VPP < VPPLK, the device will only execute the following commands successfully: Read Array, Read Status Register, Clear Status Register and Read Intelligent Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI. In addition, 2.7V or 12V on VPP allows program and erase of the device. All functions associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Machine (WSM) completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation. E 3.1 Bus Operation Smart 3 Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3. Table 3. Bus Operations for Word-Wide Mode Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr.) Intelligent Identifier (Dvc.) Write Notes 1,2,3 2 2 2,9 2,4 2,4,5 2,6,7, 8 RP# VIH VIH VIH VIL VIH VIH VIH CE# VIL VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL WP# X X X X X X X A0 X X X X VIL VIH X VPP X X X X X X VPPH DQ0–15 DOUT High Z High Z High Z 0089 H See Table 5 DIN NOTES: 1. Refer to DC Characteristics. 2. X must be VIL, VIH for control pins and addresses, VPPLK , VPPH1 or VPPH2 for VPP. 3. See DC Characteristics for VPPLK, VPPH1, VPPH2 voltages. 4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A19 = X 5. See Table 5 for device IDs. 6. Refer to Table 6 for valid DIN during a write operation. 7. Command writes for block erase or word program are only executed when VPP = VPPH1 or VPPH2. 8. To program or erase the lockable blocks, hold WP# at VIH. See Section 3.3. 9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified. 14 PRELIMINARY E 3.1.1 READ SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE The flash memory has three read modes available: read array, read identifier, and read status. These modes are accessible independent of the VPP voltage. The appropriate read mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output (DQ0–DQ15) control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 15 illustrates a read cycle. 3.1.2 OUTPUT DISABLE After return from power-down, a time tPHQV is required until the initial memory access outputs are valid. A delay (tPHWL or tPHEL) is required after return from power-down before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H (ready). If RP# is taken low for time tPLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. After returning from an aborted operation, time tPHQV or tPHWL/tPHEL must be met before a read or write operation is initiated respectively. 3.1.5 WRITE With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are placed in a high-impedance state. 3.1.3 STANDBY A write is any command that alters the contents of the memory array. There are two write commands: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to VIL for tPLRH or an appropriate suspend command). The Command User Interface does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings when WE# and CE# are low, OE# = VIH, and the proper address and data (command) are presented. The command is latched on the rising edge of the first WE# or CE# pulse, whichever occurs first. Figure 16 illustrates a write operation. Device operations are selected by writing specific commands into the CUI. Table 4 defines the available commands. Appendix B provides detailed information on moving between the different modes of operation. Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs DQ0–DQ15 are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 DEEP POWER-DOWN / RESET RP# at VIL initiates the deep power-down mode, sometimes referred to as reset mode. From read mode, RP# going low for time tPLPH accomplishes the following: 1. 2. deselects the memory places output drivers in a high-impedance state 3.2 Modes of Operation The flash memory has three read modes and two write modes. The read modes are read array, read identifier, and read status. The write modes are program and block erase. Three additional modes PRELIMINARY 15 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in Appendix B. 3.2.1 READ ARRAY When the device is in the read array mode, four control signals must be controlled to obtain data at the outputs. • • • • WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH) E When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place. Table 4. Command Codes and Descriptions Code 00 FF 40 Device Mode Invalid/ Reserved Read Array Program Set-Up Description Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions. Places the device in read array mode, such that array data will be output on the data pins. This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4. 10 20 Alternate (See 40H/Program Set-Up) Program Set-Up Erase Set-Up Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,” (b) place the device into the read status register mode, and (c) wait for another command. See Section 3.2.5. If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. If a program or erase operation was previously suspended, this command will resume that operation. During program/erase, the device will respond only to the Read Status Register, Program Suspend/Erase Suspend commands and will output status register data when CE# or OE# is toggled. D0 Program Resume Erase Resume/ Erase Confirm 16 PRELIMINARY E Code B0 Device Mode Program Suspend Erase Suspend 70 Read Status Register 50 Clear Status Register Intelligent Identifier SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 4. Command Codes and Descriptions (Continued) Description Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V IL. See Sections 3.2.4.1 and 3.2.5.1. This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3. The WSM can set the Block Lock Status (SR.1) , V PP Status (SR.3), Program Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.” Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A 0 = 0 for manufacturer, A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. 90 NOTE: See Appendix B for mode transition information. 3.2.2 READ INTELLIGENT IDENTIFIER 3.2.3 READ STATUS REGISTER To read the manufacturer and device codes, the device must be in read intelligent identifier mode, which can be reached by writing the Intelligent Identifier command (90H). Once in intelligent identifier mode, A0 = 0 outputs the manufacturer’s identification code and A0 = 1 outputs the device code. See Table 5 for product signatures. To return to read array mode, write the Read Array command (FFH). Table 5. Intelligent Identifier Table Device ID Size Mfr. ID -T (Top Boot) 8894H 8892H 8890H -B (Bottom Boot) 8895H 8893H 8891H The device status register indicates when a program or erase operation is complete, and the success or failure of that operation. To read the status register issue the Read Status Register (70H) command to the CUI. This causes all subsequent read operations to output data from the status register until another command is written to the CUI. To return to reading from the array, issue the Read Array (FFH) command. The status register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a Read Status Register command. The contents of the status register are latched on the falling edge of OE# or CE#. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. 4-Mbit 8-Mbit 16-Mbit 0089H 0089H 0089H PRELIMINARY 17 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see Table 7). 3.2.3.1 Clearing the Status Register When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted to a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode. 3.2.4.1 Suspending and Resuming Program E The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array. 3.2.4 PROGRAM MODE Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute the following sequence of internally timed events: 1. Program the desired bits of the addressed memory. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, there will be no change of the memory cell contents and no error occurs. The status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. The Program Suspend command allows program suspension in order to read data in other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to “1”). tWHRH1/tEHRH1 specify the program suspend latency. A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands, while program is suspended, are Read Status Register and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 8, Program Suspend/Resume Flowchart). VPP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at V IH. 3.2.4.2 VPP Supply Voltage during Program VPP supply voltage considerations are outlined in Section 3.4 18 PRELIMINARY E 3.2.5 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 3.2.5.1 Suspending and Resuming Erase ERASE MODE To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute the following sequence of internally timed events to: 1. Program all bits within the block to “0.” 2. Verify that all bits within the block are sufficiently programmed to “0.” 3. Erase all bits within the block to “1.” 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the status register is a “0.” When the status register indicates that erasure is complete, check the Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that VPP supply voltage was not within acceptable limits. After an erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to reset the flash to read array after the erase is complete. Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. A Read Array/Program command can now be written to the CUI in order to read/write data from/to blocks other than that which is suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands while erase is suspended are Erase Resume, Program, Program Resume, Read Array, or Read Status Register. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH. This reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. 3.2.5.2 VPP Supply Voltage during Erase VPP supply voltage considerations are outlined in Section 3.4. PRELIMINARY 19 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 6. Command Bus Definitions First Bus Cycle Command Read Array Intelligent Identifier Read Status Register Clear Status Register Write (Program) Alternate Write (Program) Block Erase/Confirm Program/Erase Suspend Program/Erase Resume ADDRESS BA = Block Address IA = Identifier Address PA = Program Address X = Don’t Care Notes 5 2,3.5 5 5 4,5 4,5 5 5 5 Oper Write Write Write Write Write Write Write Write Write Addr X X X X X X X X X Data FFH 90H 70H 50H 40H 10H 20H B0H D0H Write Write Write PA PA BA Read Read IA X E Second Bus Cycle Oper Addr Data ID SRD PD PD D0H DATA SRD = Status Register Data ID = Identifier Data PD = Program Data NOTES: 1. Bus operations are defined in Table 3. 2. A0 = 0 for manufacturer code, A0 = 1 for device code. 3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. 4. Either 40H or 10H command is valid. 5. When writing commands to the device, the upper data bus [DQ8–DQ15] should be either VIL or VIH, to minimize current draw. 20 PRELIMINARY E WSMS 7 ESS 6 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 7. Status Register Bit Definition ES 5 PS 4 VPPS 3 PSS 2 NOTES: BLS 1 R 0 SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Word Program 0 = Successful Word Program SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an Erase Resume command is issued. When this bit is set to “1,” WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to “1,” WSM has attempted but failed to program a word. The VPP Status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP Status bit is not guaranteed to report accurate feedback between VPPLK and VPPH. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. These bits are reserved for future use and should be masked out when polling the Status Register. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = Block Lock Status 1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) PRELIMINARY 21 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E Command Program Setup Program Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Start Bus Operation Write Write Write 40H Program Address/Data Read Read Status Register Standby SR.7 = 1? Yes Full Status Check if Desired No Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful If an error is detected, clear the status register before attempting retry or other error recovery. 0580_07 Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted VPP Range Error 1 Programming Error Standby Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Block - Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. Figure 7. Automated Word Programming Flowchart 22 PRELIMINARY E Start Write B0H Read Status Register SR.7 = 1 SR.2 = 1 Write FFH 0 Program Completed 0 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Bus Operation Write Command Program Suspend Comments Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed Read Standby Standby Write Read Array Data = FFH Addr = X Read array data from block other than the one being programmed. Read Write Program Resume Data = D0H Addr = X Read Array Data Done Reading Yes Write D0H No Write FFH Program Resumed Read Array Data 0580_08 Figure 8. Program Suspend/Resume Flowchart PRELIMINARY 23 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write Erase Setup Write Erase Confirm Read Start Bus Operation Write 20H Write D0H and Block Address Read Status Register No Suspend Erase Loop 0 Suspend Erase Yes Standby SR.7 = 1 Full Status Check if Desired Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful 0580_09 Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error Standby 1 Command Sequence Error Standby Standby Block Erase Error SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Attempted Erase of Locked Block - Aborted Figure 9. Automated Block Erase Flowchart 24 PRELIMINARY E Start Write B0H Read Status Register SR.7 = 1 SR.6 = 1 Write FFH/40H 0 Erase Completed 0 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Bus Operation Write Command Erase Suspend Comments Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed Read Standby Standby Write Read Array Data = FFH Addr = X Read array data from block other than the one being erased. Program data to block other than the one being erased. Read Program Read Array Data/ Program Array Write Erase Resume Data = D0H Addr = X Done Reading and/or Programming Yes Write D0H No Write FFH Erase Resumed Read Array Data 0580_10 Figure 10. Erase Suspend/Resume Flowchart PRELIMINARY 25 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E VPP X VIL WP# X X VIL VIH RP# VIL VIH VIH VIH Write Protection Provided All Blocks Locked All Blocks Locked Lockable Blocks Locked All Blocks Unlocked 3.3 Block Locking The Smart 3 Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks so that the kernel code for the system can be kept secure while other parameter blocks are programmed or erased as necessary. 3.3.1 VPP = VIL FOR COMPLETE PROTECTION The 12V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12V may be applied to VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. Table 8. Write Protection Truth Table for Advanced Boot Block Flash Memory Family The VPP programming voltage can be held low for complete write protection of all blocks in the flash device. When VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding Status Register bit (SR.3) to be set. 3.3.2 WP# = VIL FOR BLOCK LOCKING The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #37 and #38 for the 16-Mbit, blocks #21 and #22 for the 8-Mbit, and blocks #13 and #14 for the 4-Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 4-/8-/16-Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK). 3.3.3 WP# = VIH FOR BLOCK UNLOCKING ≥ VPPLK ≥ VPPLK 3.5 Power Consumption WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all block locking and VPP provides protection against spurious writes. Table 8 defines the write protection methods. While in operation, the flash device consumes active power. However, Intel Flash devices have a three-tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# = VIL the flash enters a deep power-down mode, where current is at a minimum. The combination of these features can minimize overall memory power consumption, and therefore, overall system power consumption. 3.5.1 ACTIVE POWER 3.4 VPP Program and Erase Voltages Intel’s Smart 3 products provide in-system programming and erase at 2.7V–3.6V VPP. For customers requiring fast programming in their manufacturing environment, Smart 3 includes an additional low-cost, backward-compatible 12V programming feature. 26 With CE# at a logic-low level and RP# at a logichigh level, the device is in the active mode. Refer to the DC Characteristics tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. PRELIMINARY E 3.5.2 3.5.3 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register). AUTOMATIC POWER SAVINGS (APS) Automatic Power Savings provides low-power operation during active mode. Power Reduction Control (PRC) circuitry allows the flash to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical ICC current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read. APS reduces active current to standby current levels for 2.7V–3.6V CMOS input levels. STANDBY POWER 3.6 Power-Up/Down Operation The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP or VCC, powers-up first. 3.6.1 RP# CONNECTED TO SYSTEM RESET With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ0–DQ15) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements. 3.5.4 DEEP POWER-DOWN MODE The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 VCC, VPP AND RP# TRANSITIONS The deep power-down mode of the Smart 3 Advanced Boot Block products switches the device into a low power savings mode, which is especially important for battery-based devices. This mode is activated when RP# = VIL (GND ± 0.2V). During read modes, RP# going low de-selects the memory and places the output drivers in a high impedance state. Recovery from the deep powerdown state, requires a minimum time equal to tPHQV (see AC Characteristics table). During program or erase modes, RP# transitioning low will abort the operation, but the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. PRELIMINARY 27 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE After any program or block erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired. Refer to AP-617 Additional Flash Data Protection Using VPP, RP#, and WP# for a circuit-level description of how to implement the protection schemes discussed in Section 3.5. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 VPP TRACE ON PRINTED CIRCUIT BOARDS E 3.7 Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Active current levels (I CCR) 3. Transient peaks produced by falling and rising edges of CE#. Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 28 PRELIMINARY E 4.0 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. ABSOLUTE MAXIMUM RATINGS* Extended Operating Temperature During Read ............................ –40°C to +85°C During Block Erase and Program............................ –40°C to +85°C Temperature Under Bias ......... –40°C to +85°C Storage Temperature................... –65°C to +125°C Voltage on Any Pin (except VCC, VCCQ and VPP) with Respect to GND ............... –0.5V to +5.0V1 VPP Voltage (for Block Erase and Program) with Respect to GND .........–0.5V to +13.5V1,2,4 VCC and VCCQ Supply Voltage with Respect to GND ............... –0.2V to +5.0V1 Output Short Circuit Current...................... 100 mA3 * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. NOTES: 1. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods < 20 ns. Maximum DC voltage on VPP may overshoot to +14.0V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time. VPP Program voltage is normally 2.7V–3.6V. Connection to supply of 11.4V–12.6V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 2. 3. 4. 5.0 OPERATING CONDITIONS (VCCQ = 2.7V–3.6V) Table 9. Temperature and Voltage Operating Conditions4 Parameter Operating Temperature 2.7V–3.6V VCC Supply Voltage 2.7V–3.6V I/O Supply Voltage Program and Erase Voltage 1,4 1,2,4 4 3 Block Erase Cycling 5 Notes Min –40 2.7 2.7 2.7 11.4 10,000 Max +85 3.6 3.6 3.6 12.6 Units °C Volts Volts Volts Volts Cycles Symbol TA VCC VCCQ VPP1 VPP2 Cycling NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ. 3. Applying VPP = 11.4V–12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 4. VCC, VCCQ and VPP1 must share the same supply when all three are between 2.7V and 3.6V. 5. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles. PRELIMINARY 29 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 5.1 Sym DC Characteristics: VCCQ = 2.7V–3.6V Table 10. DC Characteristics Parameter Notes VCC = 2.7V–3.6V Typ Max ± 1.0 ± 10 20 50 µA µA µA Unit E Test Conditions VCC = VCCMax = VCCQMax VIN = VCCQ or GND VCC = VCCMax = VCCQMax VIN = VCCQ or GND CMOS INPUTS VCC = VCCMax = VCCQMax CE# = RP# = VCCQ CMOS INPUTS VCC = VCCMax = VCCQMax VIN = VCCQ or GND RP# = GND ± 0.2V CMOS INPUTS VCC = VCCMax = VCCQMax OE# = VIH , CE# =VIL f = 5 MHz, IOUT = 0 mA Inputs = VIL or VIH VPP = VPPH1 (3V) Program in Progress VPP = VPPH2 (12V) Program in Progress VPP = VPPH1 (3V) Erase in Progress VPP = VPPH2 (12V) Erase in Progress CE# = VIH Erase Suspend in Progress CE# = VIH Program Suspend in Progress RP# = GND ± 0.2V VPP ≤ VCC µA ILI ILO ICCS Input Load Current Output Leakage Current VCC Standby Current 1 1 1,7 ICCD VCC Deep Power-Down Current 1,7 1 10 ICCR VCC Read Current 1,5,7 10 20 mA ICCW VCC Program Current 1,4,7 8 8 20 20 20 20 50 mA mA mA mA µA ICCE VCC Erase Current 1,4,7 8 8 ICCES ICCWS IPPD IPPR VCC Erase Suspend Current VCC Program Suspend Current VPP Deep Power-Down Current VPP Read Current 1,2,4,7 20 1,2,4,7 20 50 µA 1 0.2 5 µA 1 2 ±50 µA 30 PRELIMINARY E Sym Parameter IPPW VPP Program Current IPPE VPP Erase Current IPPES IPPWS VPP Erase Suspend Current VPP Program Suspend Current SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 10. DC Characteristics (Continued) Notes VCC = 2.7V–3.6V Typ 1,4 15 Max 40 mA VPP = VPPH1 (3V) Program in Progress 10 25 mA VPP = VPPH2 (12V) Program in Progress 1,4 13 25 mA VPP = VPPH1 (3V) Erase in Progress 8 25 mA VPP = VPPH2 (12V) Erase in Progress 1,4 50 200 µA VPP = VPPH1 or VPPH2 Erase Suspend in Progress VPP = VPPH1 or VPPH2 Program Suspend in Progress Unit Test Conditions 1,4 50 200 µA PRELIMINARY 31 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE Table 10. DC Characteristics (Continued) Sym Parameter Notes VCC = 2.7V–3.6V Min VIL VIH VOL VOH VPPLK VPPH1 VPPH2 VLKO VLKO2 VCC Program/Erase Lock Voltage VCCQ Program/Erase Lock Voltage Input Low Voltage Input High Voltage Output Low Voltage –0.4 VCCQ – 0.4V 0.10 Max 0.4 V V V Unit E Test Conditions VCC = VCCMin = VCCQMin IOL = 100 µA VCC = VCCMin = VCCQMin IOH = –100 µA Complete Write Protection Output High Voltage VPP Lock-Out Voltage VPP during Prog/Erase Operations 3 3 3,6 VCCQ – 0.1V 1.5 2.7 11.4 1.5 1.2 3.6 12.6 V V V V V V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25°C. 2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of I CWA and ICCR. C 3. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 6. Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 7. Includes the sum of VCC and VCCQ current. Table 11. Capacitance (TA = 25°C, f = 1 MHz) Sym CIN COUT Parameter Input Capacitance Output Capacitance Notes 1 1 Typ 6 10 Max 8 12 Units pF pF VIN = 0V VOUT = 0V Conditions NOTE: 1. Sampled, not 100% tested. 32 PRELIMINARY E VCCQ SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE INPUT 0.0 VCCQ 2 TEST POINTS VCCQ 2 OUTPUT 0580_11 NOTE: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%–90%) VPPLK writing a second FFH while in read status mode will return the flash to read array mode. 46 PRELIMINARY E 124 123 122 Access Time(ns) 121 120 119 118 117 116 115 30 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE APPENDIX C ACCESS TIME VS. CAPACITIVE LOAD (tAVQV vs. CL) Access Time vs. Load Capacitance Derating Curve Smart 3 Advanced Boot Block 50 70 100 Load Capacitance(pF) NOTE: VCCQ = 2.7V This chart shows a derating curve for device access time with respect to capacitive load. The value in the DC characteristics section of the specification corresponds to C L = 50 pF. NOTE: Sampled, but not 100% tested PRELIMINARY 47 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE APPENDIX D ARCHITECTURE BLOCK DIAGRAM E I/O Logic DQ0-DQ15 VCCQ Output Buffer Input Buffer Output Multiplexer Status Register Data Register Identifier Register Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block Data Comparator Command User Interface CE# WE# OE# RP# WP# Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block Write State Machine 32-KWord Main Block Program/Erase Voltage Switch VPP Address Latch Address Counter X-Decoder VCC GND 0580-20 48 PRELIMINARY E Order Number 210830 290605 292172 SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE APPENDIX E ADDITIONAL INFORMATION(1,2) Document/Tool 1997 Flash Memory Databook Smart 3 Advanced Boot Block Byte-Wide 8-Mbit (1024K x8), 16-Mbit (2056K x 8) Flash Memory Family Datasheet AP-617 Additional Flash Data Protection Using VPP, RP# and WP# NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. PRELIMINARY 49