S5000PAL

Intel® Server Board S5000PAL / S5000XAL Technical Product Specification Intel order number: D31979-010 Revision 1.7 February 2008 Enterprise Platforms and Services Division – Marketing ii Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Revision History Revision History Date April 2006 June 2006 August 2006 Revision Number 1.0 1.1 1.2 Modifications First external release. Updated theoretical memory bandwidth performance numbers. Added Platform Control sections. Memory RAS is now available. Updated Snoop Filter Section. Updated Figures #16 and #25. Updated Table 44 BMC sensor. Updated CMOS clear and password reset usage procedures. Updated regulatory tables. Removed platform control information that can be found in the Intel S5000 Server Board Family Datasheet. Updated processor support section. Updated Table 44 BMC sensor. Updated Processor support section ® January 2007 1.3 May 2007 August 2007 October 2007 February 2008 1.4 1.5 1.6 1.7 Revision 1.7 Intel order number: D31979-010 iii Disclaimers Intel® Server Board S5000PAL / S5000XAL TPS Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Server Board S5000PAL and the Intel® Server Board S5000XAL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel Corporation server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2008. iv Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Table of Contents Table of Contents 1. Introduction ........................................................................................................................ 12 1.1 1.2 2. 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 3. 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 3.4.1 3.4.2 3.5 4. 5. Chapter Outline...................................................................................................... 12 Server Board Use Disclaimer ................................................................................ 12 Intel® Server Board S5000PAL / S5000XAL Feature Set ..................................... 13 Server Board Layout.............................................................................................. 14 Connector and Component Locations ................................................................... 15 Light Guided Diagnostic LED Locations ................................................................ 17 External I/O Connector Locations.......................................................................... 18 Server Board Mechanical Drawings ...................................................................... 19 Intel® 5000P and 5000X Memory Controller Hubs (MCH) ..................................... 25 System Bus Interface............................................................................................. 25 Processor Support ................................................................................................. 25 Memory Sub-system .............................................................................................. 26 Snoop Filter (5000X MCH only) ............................................................................. 32 ESB-2 IO Controller ............................................................................................... 32 PCI Sub-system..................................................................................................... 33 Serial ATA Support ................................................................................................ 35 Parallel ATA (PATA) Support ................................................................................ 36 USB 2.0 Support.................................................................................................... 36 Video Support ........................................................................................................ 36 Network Interface Controller (NIC) ........................................................................ 38 Intel® I/O Acceleration Technology ........................................................................ 38 MAC Address Definition......................................................................................... 38 Super I/O ............................................................................................................... 39 Product Overview............................................................................................................... 13 Functional Architecture ..................................................................................................... 24 Platform Management........................................................................................................ 42 Connector / Header Locations and Pin-outs.................................................................... 43 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 Board Connector Information................................................................................. 43 Power Connectors ................................................................................................. 44 System Management Headers .............................................................................. 45 Intel® Remote Management Module (RMM) Connector ........................................ 45 Intel® RMM NIC Connector .................................................................................... 46 LCP/AUX IPMB Header ......................................................................................... 47 IPMB Header ......................................................................................................... 47 v Intel order number: D31979-010 Revision 1.7 Table of Contents Intel® Server Board S5000PAL / S5000XAL TPS 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 5.8 6. 6.1 6.1.1 6.1.2 6.2 6.3 7. 7.1 7.2 7.2.1 7.3 7.4 7.5 8. 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 vi Riser Card Slots..................................................................................................... 47 SSI Control Panel Connector................................................................................. 52 Bridge Board Connector ........................................................................................ 52 I/O Connector Pin-out Definition ............................................................................ 54 VGA Connector...................................................................................................... 54 NIC Connectors ..................................................................................................... 54 IDE Connector ....................................................................................................... 55 Intel® I/O Expansion Module Connector ................................................................ 55 SATA Connectors .................................................................................................. 56 Serial Port Connectors........................................................................................... 57 Keyboard and Mouse Connector ........................................................................... 57 USB 2.0 Connectors .............................................................................................. 58 Fan Headers .......................................................................................................... 59 Recovery Jumper Blocks ....................................................................................... 60 CMOS Clear and Password Reset Usage Procedure ........................................... 61 BMC Force Update Procedure .............................................................................. 61 BIOS Select Jumper .............................................................................................. 62 External RJ45 Serial Port Jumper Block................................................................ 63 5-Volt Standby LED ............................................................................................... 64 System ID LED and System Status LED ............................................................... 65 System Status LED – BMC Initialization ................................................................ 66 DIMM Fault LEDs .................................................................................................. 67 Processor Fault LED.............................................................................................. 67 Post Code Diagnostic LEDs .................................................................................. 68 Intel® Server Board S5000PAL / S5000XAL Design Specifications ..................... 69 Server Board Power Requirements ....................................................................... 70 Processor Power Support...................................................................................... 70 Power Supply Output Requirements ..................................................................... 71 Turn On No Load Operation .................................................................................. 71 Grounding .............................................................................................................. 72 Standby Outputs .................................................................................................... 72 Remote Sense ....................................................................................................... 72 Voltage Regulation ................................................................................................ 72 Dynamic Loading ................................................................................................... 73 Capacitive Loading ................................................................................................ 73 Revision 1.7 Intel order number: D31979-010 Jumper Block Settings ...................................................................................................... 60 Light Guided Diagnostics.................................................................................................. 64 Power and Environmental Specifications ........................................................................ 69 Intel® Server Board S5000PAL / S5000XAL TPS Table of Contents 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 9. 9.1 9.1.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.3 9.4 Closed-Loop Stability............................................................................................. 73 Common Mode Noise ............................................................................................ 73 Ripple / Noise ........................................................................................................ 74 Soft Starting ........................................................................................................... 74 Timing Requirements............................................................................................. 74 Residual Voltage Immunity in Standby Mode ........................................................ 77 Product Regulatory Compliance ............................................................................ 78 Product Safety & Electromagnetic (EMC) Compliance.......................................... 78 Electromagnetic Compatibility Notices .................................................................. 79 FCC Verification Statement (USA) ........................................................................ 79 ICES-003 (Canada) ............................................................................................... 79 Europe (CE Declaration of Conformity) ................................................................. 79 BSMI (Taiwan) ....................................................................................................... 80 RRL (Korea)........................................................................................................... 80 Product Ecology Compliance................................................................................. 81 Other Markings ...................................................................................................... 82 Regulatory and Certification Information......................................................................... 78 Appendix A: Integration and Usage Tips................................................................................ 83 Appendix B: BMC Sensor Tables ............................................................................................ 84 Appendix C: POST Code Diagnostic LED Decoder ............................................................. 100 Appendix D: POST Error Messages and Handling .............................................................. 104 Appendix E: Supported Intel® Server Chassis ..................................................................... 107 Glossary................................................................................................................................... 110 Reference Documents ............................................................................................................ 113 Revision 1.7 Intel order number: D31979-010 vii List of Figures Intel® Server Board S5000PAL / S5000XAL TPS List of Figures Figure 1. Components & Connector Location Diagram .............................................................. 16 Figure 2. Light Guided Diagnostic LED Location Diagram ......................................................... 17 Figure 3. Intel® Server Board S5000PAL / S5000XAL ATX I/O Layout ..................................... 18 Figure 4. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (1 of 2)19 Figure 5. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (2 of 2)20 Figure 6. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 1 ................ 21 Figure 7. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 2 ................ 22 Figure 8. Intel® Server Board S5000PAL / S5000XAL - Primary Side Duct and VR Restrictions23 Figure 9. Server Board Functional Block Diagram...................................................................... 24 Figure 10. CEK Processor Mounting .......................................................................................... 26 Figure 11. Memory Layout .......................................................................................................... 27 Figure 12. Recommended Minimum Two DIMM Memory Configuration .................................... 29 Figure 13. Recommended Four DIMM Configuration ................................................................. 30 Figure 14. Single Branch Mode Sparing DIMM Configuration .................................................... 31 Figure 15. Serial Port Configuration Jumper Location ................................................................ 40 Figure 16. SMBUS Block Diagram.............................................................................................. 42 Figure 17. Recovery Jumper Blocks (J1D1, J1D2, J1D3) ......................................................... 60 Figure 18. BIOS Select Jumper (J3H1) ...................................................................................... 62 Figure 19. External RJ45 Serial Port Configuration Jumper ....................................................... 63 Figure 20. 5V Standby Status LED Location .............................................................................. 64 Figure 21. System ID LED and System Status LED Locations................................................... 65 Figure 22. DIMM Fault LED Locations........................................................................................ 67 Figure 23. Processor Fault LED Location ................................................................................... 67 Figure 24. POST Code Diagnostic LED Location ....................................................................... 68 Figure 25. Power Distribution Block Diagram ............................................................................. 70 Figure 26. Output Voltage Timing ............................................................................................... 75 Figure 27. Turn On/Off Timing (Power Supply Signals).............................................................. 76 Figure 28. Diagnostic LED Placement Diagram ....................................................................... 100 Figure 29. 1U – Intel® Server Chassis SR1500 Overview ........................................................ 107 Figure 30. 1U – Intel® Server Chassis SR1550 Overview ........................................................ 108 Figure 31. 2U – Intel® Server Chassis SR2500 Overview ........................................................ 109 viii Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS List of Tables List of Tables Table 1. I2C Addresses for Memory Module SMB ..................................................................... 27 Table 2. Maximum 8 DIMM System Memory Configuration – x8 Single Rank ........................... 28 Table 3. Maximum 8 DIMM System Memory Configuration – x4 Dual Rank .............................. 28 Table 4. PCI Bus Segment Characteristics................................................................................. 33 Table 5. Video Modes ................................................................................................................. 37 Table 6. NIC2 Status LED........................................................................................................... 38 Table 7. Serial A Header Pin-out ................................................................................................ 39 Table 8. Rear Serial B Port Adapter Pin-out ............................................................................... 40 Table 9. Board Connector Matrix ................................................................................................ 43 Table 10. Power Connector Pin-out (J3K3) ................................................................................ 44 Table 11. 12V Power Connector Pin-out (J3K4)......................................................................... 44 Table 12. Power Supply Signal Connector Pin-out (J1K1) ......................................................... 44 Table 13. Intel® RMM Connector Pin-out (J1C5) ........................................................................ 45 Table 14. 30-pin Intel® RMM NIC Module Connector Pin-out (J1B2) ......................................... 46 Table 15. LPC/AUX IPMB Header Pin-out (J1C2) ...................................................................... 47 Table 16. IPMB Header Pin-out (J1C3) ...................................................................................... 47 Table 17. Low-profile Riser Slot Pin-out (J5B1).......................................................................... 47 Table 18. Full-height Riser Slot Pin-out (J4F1)........................................................................... 48 Table 19. Front Panel SSI Standard 24-pin Connector Pin-out (J3H2) ...................................... 52 Table 20. 120-pin Bridgeboard Connector Pin-out (J4G1) ......................................................... 52 Table 21. VGA Connector Pin-out (J6A1)................................................................................... 54 Table 22. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2)...................................... 54 Table 23. 44-pin IDE Connector Pin-out (J3G1) ......................................................................... 55 Table 24. 50-pin Intel® I/O Expansion Module Connector Pin-out (J3B1)................................... 56 Table 25. SATA Connector Pin-out (J1H1, J1G2, J1G1, J1F2, J1E3) ....................................... 56 Table 26. External RJ-45 Serial ‘B’ Port Pin-out (J9A2) ............................................................. 57 Table 27. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) ........................................................... 57 Table 28. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) ........................................... 57 Table 29. External USB Connector Pin-out (J5A1, J6A2)........................................................... 58 Table 30. Internal USB Connector Pin-out (J1J1)....................................................................... 58 Table 31. SSI Fan Connector Pin-out (J9K1,J5K1,J3K1,J3K2,J7A2,J7A1) ............................... 59 Table 32. Recovery Jumpers (J1D1, J1D2, J1D3) ..................................................................... 60 Table 33: Server Board Design Specifications ........................................................................... 69 Table 34. Dual-Core Intel® Xeon® Processor 5000 Sequence TDP Guidelines per processor .. 70 Table 35. 600W Load Ratings .................................................................................................... 71 Revision 1.7 Intel order number: D31979-010 ix List of Tables Intel® Server Board S5000PAL / S5000XAL TPS Table 36: No load operating range ........................................................................................... 71 Table 37. Voltage Regulation Limits ........................................................................................... 72 Table 38. Transient Load Requirements..................................................................................... 73 Table 39. Capacitive Loading Conditions ................................................................................... 73 Table 40. Ripple and Noise......................................................................................................... 74 Table 41. Output Voltage Timing ................................................................................................ 75 Table 42. Turn On/Off Timing ..................................................................................................... 76 Table 43. BMC Sensors.............................................................................................................. 86 Table 44: POST Progress Code LED Example ........................................................................ 100 Table 45. Diagnostic LED POST Code Decoder ...................................................................... 101 Table 46. POST Error Messages and Handling........................................................................ 104 Table 47. POST Error Beep Codes .......................................................................................... 106 Table 48. BMC Beep Codes ..................................................................................................... 106 x Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS List of Tables < This page intentionally left blank. > Revision 1.7 Intel order number: D31979-010 xi Introduction Intel® Server Board S5000PAL / S5000XAL TPS 1. Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high level architecture of the Intel® Server Board S5000PAL and Intel® Server Board S5000XAL. The Intel® S5000 Series Chipsets Server Board Family Datasheet should also be referenced for more in depth detail of various board sub-systems including chipset, BIOS, System Management, and System Management software. In addition, design level information for specific sub-systems can be obtained by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given sub-system. EPS and EDS documents are not publicly available. They are only made available under NDA with Intel and must be ordered through your local Intel representative. The Intel® Server Board S5000PAL/XAL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Refer to the Intel® Server Board S5000PAL/XAL Specification Update for published errata. 1.1 • • • • • • • • • • • • • • Chapter Outline Chapter 1 – Introduction Chapter 2 – Server Board Overview Chapter 3 – Functional Architecture Chapter 4 – Platform Management Chapter 5 – Connector & Header Location and Pin-out Chapter 6 – Configuration Jumpers Chapter 7 – Light Guided Diagnostics Chapter 8 – Power and Environmental Specifications Chapter 9 – Regulatory and Certification Information Appendix A – Integration and Usage Tips Appendix B – BMC Sensor Tables Appendix C – POST Code Diagnostic LED Decoder Appendix D – Post Code Errors Appendix E – Supported Intel® Server Chassis This document is divided into the following chapters 1.2 Server Board Use Disclaimer Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or nonoperating limits. 12 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Product Overview 2. Product Overview The Intel® Server Board S5000PAL and Intel® Server Board S5000XAL are monolithic printed circuit boards with features that were designed to support the high-density 1U and 2U server markets. 2.1 Intel® Server Board S5000PAL / S5000XAL Feature Set Feature 771-pin LGA sockets supporting 1 or 2 Dual-Core Intel® Xeon® processors 5000 sequence, with system bus speeds of 667 MHz, 1066 MHz, or 1333 MHz 8 Keyed DIMM slots supporting fully buffered DIMM technology (FBDIMM) memory. 240-pin DDR2-533 and DDR2-677 FBDIMMs must be used. Intel® 5000 Chipset Family which includes the following components: Intel® 5000P Memory Controller Hub or Intel® 5000X Memory Controller Hub Intel® 6321ESB I/O Controller Hub1 Note: Intel will only make available an OEM SKU of this server board using the Intel® 5000X Memory Controller Hub. Description Processors Memory Chipset On-board Connectors/Headers External connections: Stacked PS/2* ports for keyboard and mouse RJ45 Serial B port Two RJ45 NIC connectors for 10/100/1000 Mb connections Two USB 2.0 ports Video Connector Internal connectors/headers: One USB port header, capable of providing two USB 2.0 ports One DH10 Serial A header Six SATA ports via the ESB-2 and integrated SW RAID 0/1/10 support One 44pin (power + I/O) ATA/100 connector for optical drive support One Intel® Remote Management Module (Intel® RMM) connector (Intel® RMM use is optional) One Intel® I/O Expansion Module Connector supporting: Dual GB NIC Intel® I/O Expansion Module (Optional) External SAS Intel® I/O Expansion Module (Optional) Infiniband* I/O Expansion Module (Optional) SSI-compliant 24-pin control panel header SSI-compliant 24-pin main power connector, supporting the ATX-12V standard on the first 20 pins 8-Pin +12V Processor Power Connector Add-in PCI, PCI-X*, PCI Express* Cards On-board Video On-board Hard Drive Controller One low profile riser slot supporting 1U or 2U PCIe* riser cards One full height riser slot supporting 1U or 2U PCI-X* and PCIe* riser cards ATI* ES1000 video controller with 16MB DDR SDRAM Six ESB-2 SATA ports. Intel® Embedded Server RAID Technology II with SW RAID levels 0/1/10. Optional support for SW RAID 5 with activation key.2 Two 10/100/1000 Intel® 82563EB PHYs supporting Intel® I/O Acceleration Technology Six 4-pin Fan Headers supporting two processor fans, and four system fans Support for Intel® System Management Software LAN System Fans System Management 1 For the remainder of this document, the Intel® 6321ESB I/O Controller Hub will be refferred to as ESB-2. 2 Onboard SATA SW RAID 5 support provided as a post-launch product feature. Revision 1.7 Intel order number: D31979-010 13 Product Overview Intel® Server Board S5000PAL / S5000XAL TPS 2.2 Server Board Layout 14 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Product Overview 2.2.1 Connector and Component Locations The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure. A QQ J PP OO NN K L BC D EF GH I MM LL KK JJ II M N HH GG FF EE DD CC BB AA Z O P Q Y X W V U TS R TP02071 Revision 1.7 Intel order number: D31979-010 15 Product Overview Intel® Server Board S5000PAL / S5000XAL TPS A B C D E F G H I J K L M N O P Q R S T U Description BIOS Bank Select Jumper Intel ESB-2 IO Controller Hub IO Module Option Connector POST Code Diagnostic LEDs Intel Adaptive Slot – Full Height PCI Express* Riser Slot – Low Profile System Identification LED - Blue External IO Connectors Status LED – Green / Amber Serial ‘B’ Port Configuration Jumper System Fan #4 Header System Fan #3 Header FBDIMM Slots Intel 5000P Memory Controller Hub (MCH) or ® Intel 5000X Memory Controller Hub (MCH) CPU #1 Connector CPU #2 Connector CPU #1 Fan Header Voltage Regulator Heat Sink CPU #2 Fan Header Bridge Board Connector ATA-100 Optical Drive Connector (Power+IO) ® ® ® V W X Y Z AA BB CC DD EE FF GG HH II JJ KK LL MM NN OO PP QQ Description System Fan #2 Header CPU Power Connector Main Power Connector Battery Power Supply Management Connector Dual Port USB 2.0 Header System Fan #1 Header SSI 24-pin Control Panel Header SATA 0 SATA 1 SATA 2 SATA 3 SATA 4 SATA 5 SATA SW RAID 5 Activation Key Connector Intel Remote Management Module (RMM) Connector System Recovery Jumper Block Chassis Intrusion Switch Header 3-pin IPMB Header Intel Local Control Panel Header Serial ‘A’ Header Intel RMM NIC Connector ® ® ® Figure 1. Components & Connector Location Diagram 16 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Product Overview 2.2.2 Light Guided Diagnostic LED Locations A B C I J K L DM N O P S G Q E R F TP02317 A B C D Description Post Code Diagnostic LEDs System Identification LED – Blue System Status LED – Green / Amber DIMM Fault LEDs E F G Description CPU Fault LED CPU Fault LED 5-Volt Stand-by Present LED Figure 2. Light Guided Diagnostic LED Location Diagram Revision 1.7 Intel order number: D31979-010 17 Product Overview Intel® Server Board S5000PAL / S5000XAL TPS 2.2.3 External I/O Connector Locations The drawing below shows the layout of the rear I/O components for the server board. A B A B C D C D E E F G H F G H TP02296 PS/2 Mouse PS/2 Keyboard Serial Port B NIC port 1 (1 Gb) NIC port 2 (1 Gb) Video USB port 1 USB port 2 Figure 3. Intel® Server Board S5000PAL / S5000XAL ATX I/O Layout 18 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Product Overview 2.2.4 Server Board Mechanical Drawings Molex 43202-8927 6026A0027801 118.11 [4.650] 2 x 124.46 [4.900] 2 x 86.89 [3.421] 2 x 0.00 [0.000] 11.02 [0.434] 11.91 [0.469] 16.76 [0.660] 10.16 [0.400] 2 x 0.00 [0.000] 0.91 [0.036] 15.24 [0.600] 21.59 [0.850] Lotes B2515BB2M 6012A0019603 45.59 [1.795] 2 x 49.35 [1.943] 62.66 [2.467] 67.31 [2.650] Molex 22-44-7031 6012A0099701-HDR4P Molex 22-44-7031 6012A0099701 9 x Ø 0.125 [3.18] Typ. 124.26 [4.892] 127.43 [5.017] 152.40 [6.000] 6 x Betterment BTM-PP02.2F1611.007X 6012B0018302 0.16 [0.006] 22.86 [0.900] 7 x Ø 3.96 [0.156] Molex 877715-3205 6012A0100101 AMP 177983-5 6012A0103201 FCI 10027747-114101 6012A0105001 5 x Ø 8.00 [0.315] Silkscreen on secondary side for spacer 2 x 101.60 [4.000] 2 x 3.28 [0.129] 288.29 [11.350] 4 x 187.93 [7.399] 55.35 [2.179] Lotes AAA-PCI-033-K02 6012B0051002 196.85 [7.750] 16.51 [0.650] 33.91 [1.335] 44.89 [1.767] 82.80 [3.260] 227.33 [8.950] 228.60 [9.000] Lotes B2515BB2M 6012A0019603 Lotes B4L60BB2L 6012A0105401 8 x Ø 10.16 [0.400] 3 x 312.42 [12.300] 320.04 [12.600] 38.10 [1.500] Typ. 2 x 223.80 [8.811] 5.08 [0.200] 9.65 [0.380] 124.46 [4.900] 2 x 141.25 [5.561] 2 x 281.94 [11.100] 2 x 59.69 [2.350] Molex 3930-0080 6012A0022801 AMP 794108-1 6012A0022801 81.28 [3.200] Typ. TP02316 Figure 4. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (1 of 2) Revision 1.7 Intel order number: D31979-010 19 Product Overview 16.51 [0.650] 3 x 13.59 [0.535] 2 x 12.33 [0.485] 12.27 [0.483] 9.07 [0.357] 87.88 [3.460] 94.23 [3.710] 100.58 [3.960] 104.39 [4.110] 106.93 [4.210] 127.20 [5.008] 141.78 [5.582] Intel® Server Board S5000PAL / S5000XAL TPS 263.14 [10.360] 278.38 [10.960] 280.71 [11.052] 158.80 [6.252] 175.03 [6.891] 200.13 [7.879] 205.97 [8.109] 224.21 [8.827] 244.27 [9.617] 0.00 [0.000] 56.84 [2.238] 10.16 [0.400] 5 x 6.99 [0.275] 80.14 [3.155] 5.21 [0.205] 9.32 [0.367] 0.00 [0.000] 3.45 [0.136] 2 x 1.83 [0.072] 11.96 [0.471] 19.76 [0.778] 30.91 [1.217] 35.05 [1.380] 49.68 [1.956] 62.99 [2.480] 67.39 [2.653] 76.45 [3.010] 86.11 [3.390] 1st Pin 119.16 [4.692] 119.59 [4.708] 6.27 [0.247] 2.67 [0.105] 3.35 [0.132] 8.64 [0.340] 35.28 [1.389] 1st Pin 1st Pin 8 x 40.39 [1.590] 7 x 10.67 [0.420] 143.00 [5.630] 160.77 [6.330] 174.17 [6.857] 178.56 [7.030] 196.33 [7.730] 211.02 [8.308] 214.12 [8.430] 214.63 [8.450] 230.38 [9.070] 231.89 [9.130] 243.83 [9.600] 265.41 [10.449] 297.84 [11.726] 308.74 [12.155] 298.51 [11.752] 309.042 [12.167] R1.52 [0.060] 96.25 [3.789] 104.39 [4.110] 12.66 [0.498] 2 x 11.93 [0.470] 6 x 12.83 [0.505] 280.21 [11.032] 52.98 [2.086] 74.78 [2.944] 76.96 [3.030] 83.31 [3.280] TP02292 Figure 5. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (2 of 2) 20 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS H < 30 mm [1.181"] PCI BKT Drop Down H < 11.65 mm [0.459"] Under Rear Panel Tab Product Overview 16.51 [0.650] 13.18 [0.519] 9.27 [0.365] 3.28 [0.129] 0.00 [0.000] 0.76 [0.030] 267.51 [10.532] 288.29 [11.350] 198.02 [7.796] 207.98 [8.188] No Components Allowed for Retention Pins 2 x 5.08 [0.200] 10.16 [0.400] 3 x 5.08 [0.200] 0.00 [0.000] 2 x 3.07 [0.121] 21.23 [0.836] 28.17 [1.109] 41.96 [1.652] 53.34 [2.100] 60.15 [2.368] 57.89 [2.279] 96.98 [3.818] 98.88 [3.893] 101.90 [4.012] 109.40 [4.307] 120.85 [4.758] 125.27 [4.932] 129.69 [5.106] 134.62 [5.300] 137.72 [5.422] H < 5 mm [0.196"] PCI BKT Drop Down H < 12.7 mm [0.499"] Under LP PCI Option Card 3.81 [0.150] 0.18 [0.007] 10.80 [0.425] 18.97 [0.747] 46.76 [1.841] H < 3.5 mm [0.138"] for Three Boards 9 x No Components 5.0 dia. on Top No Components 3.5 dia. on Bottom H < 12.4 mm [0.488"] Under Riser PCIe Conn. 130.00 [5.118] H < 26 mm [1.023"] Under Riser PCI-X Conn. 102.77 [4.046] H < 10mm [0.394"] PCI BKT DROP DOWN 170.64 [6.718] 184.12 [7.249] H < 11.8 mm [0.465"] Under Riser Card H < 15.2 mm [0.600"] Under FH PCI Option Card 169.98 [6.692] 177.47 [6.987] 180.92 [7.123] 188.72 [7.430] H < 3mm [0.118"] PCI BKT DROP DOWN 234.75 [9.242] 264.97 [10.432] 273.02 [10.749] REF ONLY H < 7 mm [0.275"] Under Heat Sink H < 9.5 mm [0.374"] Under Bridge Board 4 x 7.62 [0.300] 316.00 [12.441] 320.04 [12.600] 199.67 [7.861] 203.48 [8.011] REF ONLY H < 11 mm [0.433"] Under Heat Sink 282.22 [11.111] 9.70 [0.382] 89.36 [3.518] 94.41 [3.717] 96.57 [3.802] 111.84 [4.403] 120.93 [4.761] TP02293 Figure 6. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 1 Revision 1.7 Intel order number: D31979-010 21 Product Overview 16.51 [0.650] 0.00 [0.000] Intel® Server Board S5000PAL / S5000XAL TPS 288.29 [11.350] H < 1.47 mm [0.058"] Typ. 2 X 5.00 [0.197] 3 X 3.99 [0.157] 3.00 [0.118] No Components or Surface Layer Traces in this Zone. 3 Ground Pad on Side 2 10.16 [0.400] 0.00 [0.000] 10.13 [0.399] H < 2 mm [0.078] Ø 29.46 [1.160] Typ. 15.24 [0.600] Typ. Backside Spring Area. No Motherboard Component Placement Allowed. 180.34 [7.100] 200.03 [7.875] 0.200" [5.08 mm Max] Keep IN for 2U and above Platforms. 0.100" [2.54 mm Max] Keep IN for 1U Platforms on Side 2. 257.73 [10.147] 4 x 4.45 [0.175] 276.86 [10.900] Limited Height 1.27 mm [0.05"] on Side 2, Dia. 29.5 mm [1.160"] Ø 2.000 [50.8 mm] Typ. 5.08 [0.200] Typ. 20.32 [0.800] Typ. Limited Height 1.27 mm [0.05"] on Side 2 320.04 [12.600] 266.95 [10.510] 279.68 [11.011] 123.47 [4.861] 136.14 [5.360] 184.40 [7.260] 197.10 [7.760] 205.99 [8.110] 218.72 [8.611] 7.52 [0.296] TP02294 Figure 7. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 2 22 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS 285.75 [11.250] 199.21 [7.843] 113.13 [4.454] 16.51 [0.650] 0.00 [0.000] Product Overview 10.16 [0.400] 0.00 [0.000] NO Components Allowed for Duct 143.51 [5.650] 2 x 173.99 [6.850] 182.83 [7.198] H < 10.0 mm [0.394"] Under Duct H < 0.8 mm [0.310"] Under VR H < 1.5 mm [0.059"] Under VR 256.54 [10.100] 3 x 274.32 [10.800] 2 x 77.22 [3.040] 298.51 [11.753] 11.69 [0.460] TP02295 5.52 [0.217] 4.83 [0.190] 109.86 [4.325] 125.78 [4.952] NO Components Allowed 5.08 [0.200] H < 27 mm [1.063"] Under Duct Figure 8. Intel® Server Board S5000PAL / S5000XAL - Primary Side Duct and VR Restrictions Revision 1.7 Intel order number: D31979-010 6.35 [0.250] 23 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3. Functional Architecture The architecture and design of the Intel® Server Board S5000PAL / S5000XAL is based on the Intel® 5000 Chipset Family. The chipset is designed for systems based on the Dual-Core Intel® Xeon® processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The chipset is made up of two main components: the Memory Controller Hub (MCH) for the host bridge and the ESB2 I/O controller hub for the I/O subsystem. This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up this server board. For more in depth detail of the functionality for each of the chipset components and each of the functional architecture blocks, see the Intel® S5000 Server Board Family Datasheet. Figure 9. Server Board Functional Block Diagram Note: The diagram above uses the Intel® 5000P MCH as a general reference designator for both MCH components supported on this server board. 24 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture 3.1 Intel® 5000P and 5000X Memory Controller Hubs (MCH) This section will describe the general functionality of the memory controller hub as it is implemented on this server board. Depending on the version of the server board in use, it may support either the Intel® 5000P MCH or the Intel® 5000X MCH. Features that are unique to a particular MCH will be so referenced. The Memory Controller Hub (MCH) is a single 1432 pin FCBGA package which includes the following core platform functions: • • • • • System Bus Interface for the processor sub-system Memory Controller PCI Express* Ports including the Enterprise South Bridge Interface (ESI) FBD Thermal Management SMBUS Interface Additional information about MCH functionality can be obtained from the Intel® S5000 Series Chipsets Server Board Family Datasheet, the Intel® 5000P Memory Controller Hub External Design Specification (Yellow Cover), or the Intel® 5000X Memory Controller Hub External Design Specification (Yellow Cover). Note: Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel representative. 3.1.1 System Bus Interface The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the Dual-Core Intel® Xeon® processors 5000 sequence. Each front side bus on the MCH uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333 MHz data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each bus. 3.1.2 • • • • Processor Support The server board supports the following processors: One or two Dual-Core Intel® Xeon® processors 5000 or 5100 sequence with a 677-, 1066-, or 1333-MHz front side bus. Up to two Quad-Core Intel® Xeon® processors 5300 sequence with a 1066- or 1333-MHz front side bus. Up to two 45nm 2P Dual-Core Intel® Xeon® processors. Systems based on S5000PALR or S5000XALR only. Up to two 45nm next generation Quad-Core Intel® Xeon® processors. Systems based on S5000PALR or S5000XALR only. Previous generations of the Intel® Xeon® processor are not supported on the server board. See http://support.intel.com/support/motherboards/server/s5000pal/ for a complete updated list of supported processors. ( http://support.intel.com/support/motherboards/server/sb/CS-022346.htm/ is sub-directory of above S5000PAL URL that reflects supported processor list) Note: Only Dual-Core Intel® Xeon® processors 5000 sequence, that support system bus speeds of 667 MHz, 1066 MHz, and1333 MHz are supported on this server board. Revision 1.7 Intel order number: D31979-010 25 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.1.2.1 Processor Population Rules When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. Mixed processor steppings is supported. However, the stepping of one processor cannot be greater than one stepping back of the other. When only one processor is installed, it must be in the socket labeled CPU1. The other socket must be empty. The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not supported. No terminator is required in the second processor socket when using a single processor configuration. 3.1.2.2 Common Enabling Kit (CEK) Design Support The server board complies with Intel’s Common Enabling Kit (CEK) processor mounting and heat sink retention solution. The server board ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heat sink attaches to the CEK, over the top of the processor and the thermal interface material (TIM). See the figure below for the stacking order of the chassis, CEK spring, server board, TIM, and heat sink. The CEK spring is removable, allowing for the use of non-Intel heat sink retention solutions. Note: The processor heat sink and CEK spring shown in the following diagram are for reference purposes only. The actual processor heat sink and CEK solutions compatible with this generation server board may be of a different design. Heatsink assembly Thermal interface material (TIM) Server board CEK spring Chassis Figure 10. CEK Processor Mounting 3.1.3 Memory Sub-system On the Intel® Server Board S5000PAL / S5000XAL, the MCH provides four channels of Fully Buffered DIMM (FB-DIMM) memory. Each channel can support up to 2 Dual Ranked FB-DIMM DDR2 DIMMs. FBDIMM memory channels are organized in to two branches for support of RAID 1 (mirroring). The MCH can support up to 8 DIMMs or a maximum memory size of 32 GB physical memory in non-mirrored mode and 16 GB physical memory in a mirrored configuration. The read bandwidth for each FB-DIMM channel is 4.25 GB/s for DDR2 533 FB-DIMM memory which gives a total read bandwidth of 17 GB/s for four FBDIMM channels. Thus, this provides 8.5 GB/s of write memory bandwidth for four FB-DIMM channels. The read bandwidth for each FB-DIMM channel is 5.3GB/s for DDR2 667 FB-DIMM memory which gives 26 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture a total read bandwidth of 21GB/s for four FB-DIMM channels. Thus, this provides 10.7 GB/s of write memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667. On the Intel® Server Board S5000PAL / S5000XAL, a pair of channels becomes a branch where Branch 0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are organized into two branches for support of RAID 1(mirroring). Channel B Channel A Channel C Channel D MC H 1 MA DIM M A2 1 DIM M B 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02299 Figure 11. Memory Layout To boot the system, the system BIOS on the server board uses a dedicated I2C bus to retrieve DIMM information needed to program the MCH memory registers. The following table provides the I2C addresses for each DIMM slot. Table 1. I2C Addresses for Memory Module SMB Device DIMM A1 DIMM A2 DIMM B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1 DIMM D2 Address 0xA0 0xA2 0xA0 0xA2 0xA0 0xA2 0xA0 0xA2 3.1.3.1 Memory RASUM Featuresi The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features. These features include the Intel® x4 Single Device Data Correction (Intel® x4 SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors, Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. See the Intel® S5000 Series Chipsets Server Board Family Datasheet for more information describing these features. 3.1.3.2 Supported Memory The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory). The following tables show the maximum memory configurations supported using the specified memory technology. Revision 1.7 Intel order number: D31979-010 27 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS Table 2. Maximum 8 DIMM System Memory Configuration – x8 Single Rank DRAM Technology x8 Single Rank 256 Mb 512 Mb 1024 Mb 2048 Mb Maximum Capacity Mirrored Mode 1 GB 2 GB 4 GB 8 GB Maximum Capacity Non-Mirrored Mode 2 GB 4 GB 8 GB 16 GB Table 3. Maximum 8 DIMM System Memory Configuration – x4 Dual Rank DRAM Technology x4 Dual Rank 256 Mb 512 Mb 1024 Mb 2048 Mb Maximum Capacity Mirrored Mode 4 GB 8 GB 16 GB 16 GB Maximum Capacity Non-Mirrored Mode 8 GB 16 GB 32 GB 32 GB Note: DDR2 DIMMs that are not fully buffered are NOT supported on this server board. See the Intel® Server Board S5000PAL / S5000XAL Tested Memory List for a complete list of supported memory for this server board. 3.1.3.3 DIMM Population Rules and Supported DIMM Configurations DIMM population rules depend on the operating mode of the memory controller, which is determined by the number of DIMMs installed. DIMMs must be populated in pairs. DIMM pairs are populated in the following DIMM slot order: A1 & B1, C1 & D1, A2 & B2, C2 & D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. However, DIMM capacities can be different between different DIMM pairs. For example, a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 & B1, and 1GB DIMMs installed in DIMM slots C1 & D1. Intel supported DIMM configurations for this server board are shown in the following table. Supported and Validated configuration : Slot is populated Supported but not validated configuration : Slot is populated Slot is not populated Mirroring: Sparing: Y = Yes. Indicates that configuration supports Memory Mirroring. Y(x) = Yes. Indicates that configuration supports Memory Sparing. Where x = 0 : Sparing supported on Branch0 only 1 : Sparing supported on Branch1 only 0,1 : Sparing supported on both branches Branch 0 Channel A DIMM_A1 DIMM_A2 Channel B DIMM_B1 DIMM B2 Channel C DIMM C1 Branch 1 Channel D DIMM D1 DIMM D2 Mirroring Possible Sparing Possible DIMM C2 28 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture Y (0) Y Y (0) Y Y (0, 1) Notes: - Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1. - The supported memory configurations must meet population rules defined above. - For best performance, the number of DIMMs installed should be balanced across both memory branches. For Example: a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight DIMM configuration will perform better then a six DIMM configuration. - Although mixed DIMM capacities between channels is supported, Intel does not validate DIMMs in mixed DIMM configurations. 3.1.3.3.1 Minimum Non-Mirrored Mode Configuration The server board is capable of supporting a minimum of one DIMM installed. However, for system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed. The following diagram shows the recommended minimum DIMM memory configuration. Populated DIMM slots are shown in Grey. Channel B Channel A Channel C Channel D MC H A1 IMM M A2 D DIM M B1 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02300 Figure 12. Recommended Minimum Two DIMM Memory Configuration Note: The server board supports single DIMM mode operation. Intel will only validate and support this configuration with a single 512MB x8 FBDIMM installed in DIMM slot A1. Revision 1.7 Intel order number: D31979-010 29 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.1.3.4 Non-mirrored mode memory upgrades The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the same slot position on both channels. DIMMs pairs must be identical with respect to size, speed, and organization. DIMMs that cover adjacent slot positions do not need to be identical. When adding two DIMMs to the configuration shown in Figure 12, the DIMMs should be populated in DIMM slots C1 and D1 as shown in the following diagram. Populated DIMM slots are shown in Grey. Channel B Channel A Channel C Channel D MC H A1 IMM M A2 D DIM M B1 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02301 Figure 13. Recommended Four DIMM Configuration Functionally, DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1. However, your system will not achieve equivalent performance. Figure 13 shows the supported DIMM configuration that is recommended because it allows both memory branches from the MCH to operate independently and simultaneously. FBD bandwidth is doubled when both branches operate in parallel. 3.1.3.4.1 Mirrored Mode Memory Configuration When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch 1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support memory mirroring is four DIMMs, populated as shown in Figure 13 above. All four DIMMs must be identical with respect to size, speed, and organization. To upgrade a four DIMM mirrored memory configuration, four additional DIMMs must be added to the system. All four DIMMs in the second set must be identical to the first with the exception of speed. The MCH will adjust to the lowest speed DIMM. 30 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture 3.1.3.4.2 DIMM Sparing Mode Memory Configuration The MCH provides DIMM sparing capabilities. Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails. DIMM sparing occurs within a given bank of memory and is not supported across branches. There are two supported Memory Sparing configurations. 3.1.3.4.2.1 Single Branch Mode Sparing Slot 2 Slot 1 DIMM_A2 DIMM_A1 DIMM_B2 DIMM_B1 DIMM_C2 DIMM_C1 DIMM_D2 DIMM_D1 Channel A Channel B Channel C Channel D Branch 0 Branch 1 Intel® 5000P/5000X Memory Controller Hub Figure 14. Single Branch Mode Sparing DIMM Configuration • • • • • • • DIMM_A1 and DIMM_B1 must be identical in organization, size and speed. DIMM_A2 and DIMM_B2 must be identical in organization, size and speed. DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed. DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed. Sparing should be enabled in BIOS setup. BIOS will configure Rank Sparing Mode. The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} will be selected as the spare pair unit. Revision 1.7 Intel order number: D31979-010 31 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.1.3.4.2.2 Dual Branch Mode Sparing Dual branch mode sparing requires that all eight DIMM slots be populated and must comply with the following population rules. • • • • • • • • • • • DIMM_A1 and DIMM_B1 must be identical in organization, size and speed. DIMM_A2 and DIMM_B2 must be identical in organization, size and speed. DIMM_C1 and DIMM_D1 must be identical in organization, size and speed. DIMM_C2 and DIMM_D2 must be identical in organization, size and speed. DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed. DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed. DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed. DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed. Sparing should be enabled in BIOS setup. BIOS will configure Rank Sparing Mode. The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} and {DIMM_C1, DIMM_D1} and {DIMM_C2, DIMM_D2} will be selected as the spare pair units. 3.1.4 Snoop Filter (5000X MCH only) The 5000X version of the MCH includes a snoop filter. Depending on the application of the server, this feature can be used to enhance the performance of the server by eliminating unnecessary traffic on the system bus. By removing the excess traffic from the snooped bus, the full bandwidth is available for other operations. 3.2 ESB-2 IO Controller The ESB-2 is a multi-function device that provides four distinct functions: an IO Controller, a PCI-X* Bridge, a Gigabit Ethernet Controller, and a Baseboard Management Controller (BMC). Each function within the ESB-2 has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller. A primary role of the ESB-2 is to provide the gateway to all PC-compatible I/O devices and features. The server board uses the following ESB-2 features: • • • • • • • • • • • • • PCI-X* bus interface Six Channel SATA interface w/SATA Busy LED Control Dual GbE MAC Baseboard Management Controller (BMC) Single ATA interface, with Ultra DMA 100 capability Universal Serial Bus 2.0 (USB) interface Removable Media Drives LPC bus interface PC-compatible timer/counter and DMA controllers APIC and 8259 interrupt controller Power management System RTC General purpose I/O 32 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture This section describes the function of most of the listed features as they pertain to this server board. For more detail information, see the Intel® S5000 Series Chipsets Server Board Family Datasheet or the Intel® Enterprise South Bridge-2 External Design Specification (Yellow Cover) 3.2.1 PCI Sub-system The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X*, with six independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification, Revision 2.3. The table below lists the characteristics of the PCI bus segments. Details about each bus segment follow the table. Table 4. PCI Bus Segment Characteristics PCI Bus Segment PCI32 ESB-2 PXA ESB-2 PE1 ESB-2 PCIe* Port2 PE2 ESB-2 PCIe Port3 PE4, PE5 BNB PCIe Ports 4,5 PE6, PE7 BNB PCIe Ports 6,7 Voltage 3.3V 3.3V/5.0V 3.3V 3.3V Width 32 bit 64 bit x4 x4 Speed 33MHz 133MHz 10Gb/S 10Gb/S Type PCI PCI-X* PCIe* PCIe On-board Device Support Used internally for video controller Full height riser slot, up to three slots on riser card Used for Intel chassis for mid-plane IOP Mezzanine connector for Intel I/O Expansion Module Low profile riser slot, up to two x4 slots on 2U riser, or one x8 slot on 1U riser. Full height riser slot, up to two x4 slots on riser or one x8 ® 3.3V x8 20Gb/S PCIe 3.3V x8 20Gb/S PCIe 3.2.1.1 PCI32: 32-bit, 33-MHz PCI Bus Segment All 32-bit, 33-MHz PCI I/O is directed through the ESB-2 ICH6. The 32-bit, 33-MHz PCI segment created by the ESB-2-ICH6 is known as the PCI32 segment. The PCI32 segment supports the following embedded devices: • 2D Graphics Accelerator: ATI* ES1000 Video Controller 3.2.1.2 PXA: 64-bit, 133MHz PCI-X* Bus Segment One 64-bit PCI-X* bus segment is directed through the ESB-2 ICH6. This PCI-X segment, PXA, can support up to three add-in cards on a riser card plugged into the full height riser card slot (J4F1). 3.2.1.3 PE1: One x4 PCI Express* Bus Segment One x4 PCI Express* bus segment is directed through the ESB-2. This PCI Express segment, PE1, supports the optional Active SAS Midplane IOP as used in supported Intel chassis for this server board. 3.2.1.4 PE2: One x4 PCI Express* Bus Segment One x4 PCI Express* bus segment is directed through the ESB-2. This PCI Express segment, PE2, supports one x4 PCI Express segment to the proprietary Intel® I/O Expansion Module mezzanine connector (J3B1). Revision 1.7 Intel order number: D31979-010 33 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.2.1.5 PE4, PE5: Two x4 PCI Express* Bus Segments Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express segments, PE4 and PE5, support one x8 or two x4 PCI Express segments to the low profile riser slot (J5B1). 3.2.1.6 PE6, PE7: Two x4 PCI Express* Bus Segments Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express segments, PE6 and PE7, support one x8 or two x4 PCI Express segments to the full height riser slot (J4F1). 3.2.1.7 PCI Riser Slots The server board has two riser slots capable of supporting riser cards for both 1U and 2U system configurations. Because of board placement resulting in different pin orientations, and expanded technology support associated with the full-height riser, the riser slots are not the same and require different riser cards. The low profile riser slot (J5B1) utilizes a 98-pin connector. It is capable of supporting one x8 (1U) or two x4 (2U) low profile PCI Express* add-in cards. The x8 PCI Express* bus can support bus speeds of up to 20 Gb/S. The following table provides the supported bus throughput for the given riser card used and the number of add-in cards installed. Low Profile Riser 1U – 1 add-in card slot 2U – 2 add-in card slots 1 add-in card populated x8 or x4 x4 2 add-in cards populated NA x4 Note: There are no population rules for installing a single low profile add-in card in the 2U LP riser card; a single add in card can be installed in either PCI Express* slot. While each slot can accommodate a x8 card, each slot will only support x4 bus speeds. The full height riser slot (J4F1) implements Intel® Adaptive Slot Technology. This 280-pin connector is capable of supporting riser cards that meet either the PCI-X* or PCI Express* technology specifications. The following tables show the maximum bus speed supported with different add-in card populations for each supported riser card. Full Height PCI-X* (Passive) Riser 1U – 1 add-in card slot 2U – 3 add-in card slots 1 add-in card populated Up to 133MHz Up to 100MHz in top PCI slot 2 add-in cards populated NA Up to 100MHz using top and middle slots 3 add-in cards populated NA 66MHz Note: For the 2U PCI-X* (passive) riser card, add-in cards should be installed starting with the top slot first, followed by the middle, and then the bottom. Any add-in card populated in the bottom PCI slot will cause the bus to operate at 66MHz. Full Height PCI-X* (Active) Riser 2U – 3 add-in card slots 1 add-in card populated Up to 133MHz 2 add-in cards populated Up to 133MHz 3 add-in cards populated Up to 133MHz Note: Each PCI slot on the 2U PCI-X* (active) riser card operates on an independent PCI bus. Therefore, using an add-in card that operates below 133MHz will not affect the bus speed of the other PCI slots. 34 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture Full Height PCI Express* Riser 1U – 1 add-in card slot 2U – 3 add-in card slots 1 add-in card populated x4 or x8 Single PCIe* x4 in either slot or x8 in middle slot Or PCI-X* – Up to 133MHz in bottom slot 2 add-in cards populated NA Single PCIe* – x4 in either slot or x8 in middle slot and PCI-X* – Up to 133MHz Or Dual PCIe – x4 3 add-in cards populated NA Dual PCIe* – x4 And PCI-X* – Up to 133MHz 3.2.2 Serial ATA Support The ESB-2 has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on the server board are numbered SATA-0 thru SATA-5. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS Setup Utility during POST. 3.2.2.1 Intel® Embedded Server RAID Technology II Support The onboard storage capability of this server board includes support for Intel® Embedded Server RAID Technology which provides three standard software RAID levels: data stripping (RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level 10). For higher performance, data stripping can be used to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is used for data security. Should a disk fail, a mirrored copy of the failed disk is brought on-line. There is no loss of either PCI resources (request/grant pair) or add-in card slots. With the addition of an optional Intel RAID Activation Key, Intel® Embedded Server RAID Technology is also capable of providing fault tolerant data stripping (software RAID Level 5), such that if a SATA hard drive should fail, the lost data can be restored on a replacement drive from the other drives that make up the RAID 5 pack. See Figure 1. Components & Connector Location Diagram for the location of Intel RAID Activation Key connector location. Note: Availability of the Intel RAID Activation Key to support software RAID 5 will be deferred until after product launch of this server board. Intel® Embedded Server RAID Technology functionality requires the following items: • • • • Intel® ESB-2 IO Controller Hub Intel® Embedded Server RAID Technology Option ROM Intel® Application Accelerator RAID Edition drivers, most recent revision At least two SATA hard disk drives Intel® Embedded Server RAID Technology is not available in the following configurations: • • The SATA controller in compatible mode Intel® Embedded Server RAID Technology has been disabled Revision 1.7 Intel order number: D31979-010 35 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.2.2.2 Intel® Embedded Server RAID Technology Option ROM The Intel® Embedded Server RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel® Embedded Server RAID Technology implementation and provides the ability for an Intel® Embedded Server RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel® Embedded Server RAID Technology volume(s) attached to the Intel® RAID controller. 3.2.3 Parallel ATA (PATA) Support The integrated IDE controller of the ESB-2 ICH6 provides one IDE channel. It redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100MB/s. For this server board, the IDE channel was designed to provide Slim-line Optical Drive support to the platform. The BIOS initializes and supports ATAPI devices such as CDROM, CD-RW and DVD. The IDE channel is accessed through a single high density 44-pin connector ((J3G1) which provides both power and IO signals. The ATA channel can be configured and enabled or disabled by accessing the BIOS Setup Utility during POST. Note: The IDE connector on this server board is NOT a standard 40 IDE connector. Instead, this connector has an additional 4 power pins over and above the standard 40 I/O pins. The design intent of this connector is to provide support for a slim-line optical drive only. 3.2.4 USB 2.0 Support The USB controller functionality integrated into ESB-2 provides the server board with the interface for up to eight USB 2.0 ports. Two external connectors are located on the back edge of the server board. One internal 2x5 header is provided, capable of supporting two optional USB 2.0 ports. Three USB ports are routed through the bridge board connector providing optional USB support for a system Control Panel or other USB requirements. An additional USB port is dedicated to the Intel® Remote Management Module (Intel® RMM) connector. 3.3 Video Support The server board provides an ATI* ES1000 PCI graphics accelerator, along with 16MB of video DDR SDRAM and support circuitry for an embedded SVGA video sub-system. The ATI ES1000 chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin BGA. One 4Mx16x4 bank DDR SDRAM chip provides 16MB of video memory. The SVGA sub-system supports a variety of modes, up to 1024 x 768 resolution in 8 / 16 / 32bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate. Video is accessed using a standard 15-pin VGA connector found on the back edge of the server board. Video signals are also made available through the 120-pin bridgeboard connector which provides signals for an optional video connector to be present on the platform’s control panel. Video is routed to both the rear video connector and a control panel video connector. Video is present at both connectors simultaneously and cannot be disabled at either connector individually. Hot plugging the video while the system is still running is supported. On-board video can be disabled using the BIOS Setup Utility or when an add-in video card is installed. System BIOS also provides the option for dual video operation when an add-in video card is configured in the system. 36 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture 3.3.1.1 Video Modes The ATI ES1000 chip supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD. Table 5. Video Modes 2D Mode 640x480 800x600 1024x768 1152x864 1280x1024 1600x1200 Refresh Rate (Hz) 60, 72, 75, 85, 90, 100, 120, 160, 200 60, 70, 72, 75, 85, 90, 100, 120,160 60, 70, 72, 75,85,90,100 43,47,60,70,75,80,85 60,70,74,75 52 8 bpp Supported Supported Supported Supported Supported Supported 2D Video Mode Support 16 bpp 32 bpp Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported 3.3.1.2 Video Memory Interface The memory controller sub-system of the ES1000 arbitrates requests from the direct memory interface, the VGA graphics controller, the drawing co-processor, the display controller, the video scalar, and the hardware cursor. Requests are serviced in a manner that ensures display integrity and maximum CPU/co-processor drawing performance. The server board supports a 16MB (4Meg x 16-bit x 4 banks) DDR SDRAM device for video memory. 3.3.1.3 Dual Video The BIOS supports single and dual video modes. The dual video mode is enabled by default. • • In single mode (Dual Monitor Video = Disabled), the on-board video controller is disabled when an add-in video card is detected. In dual mode (On-board Video = Enabled, Dual Monitor Video = Enabled), the on-board video controller is enabled and will be the primary video device. The external video card will be allocated resources and is considered the secondary video device. BIOS Setup provides user options to configure the feature as follows. On-board Video Dual Monitor Video Enabled Disabled Enabled Disabled Shaded if on-board video is set to "Disabled" Revision 1.7 Intel order number: D31979-010 37 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS 3.4 Network Interface Controller (NIC) Network interface support is provided from the built in Dual GbE MAC features of the ESB-2 in conjunction with the Intel® 82563EB compact Physical Layer Transceiver (PHY). Together, they provide the server board with support for dual LAN ports designed for 10/100/1000 Mbps operation. The 82563EB device is based upon proven PHY technology integrated into the Intel® Gigabit Ethernet Controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASET, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82563EB device is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps Each Network Interface Controller (NIC) drives two LEDs located on each network interface connector. The link/activity LED (to the right of the connector) indicates network connection when on, and Transmit/Receive activity when blinking. The speed LED (to the left of the connector) indicates 1000Mbps operation when amber, 100-Mbps operation when green, and 10-Mbps when off. The table below provides an overview of the LEDs. Table 6. NIC2 Status LED LED Color Off Green/Amber (Left) Green Amber Green (Right) On Blinking LED State 10 Mbps 100 Mbps 1000 Mbps Active Connection Transmit / Receive activity NIC State Intel I/O Acceleration Technology moves network data more efficiently through Dual-Core Intel® Xeon® processor 5000 sequence-based servers for improved application responsiveness across diverse operating systems and virtualized environments. Intel® I/OAT improves network application responsiveness by unleashing the power of Dual-Core Intel® Xeon® processors 5000 sequence through more efficient network data movement and reduced system overhead. Intel multi-port network adapters with Intel® I/OAT provide high-performance I/O for server consolidation and virtualization via stateless network acceleration that seamlessly scales across multiple ports and virtual machines. Intel® I/OAT provides safe and flexible network acceleration through tight integration into popular operating systems & virtual machine monitors, avoiding the support risks of 3rd-party network stacks and preserving existing network requirements such as teaming and failover. ® 3.4.1 Intel® I/O Acceleration Technology 3.4.2 MAC Address Definition Each Intel® Server Board S5000PAL / S5000XAL has four MAC addresses assigned to it at the Intel factory. During the manufacturing process, each server board will have a white MAC address sticker placed on the board. The sticker will display the MAC address in both bar code and alpha numeric formats. The printed MAC address is assigned to NIC 1 on the server board. NIC 2 is assigned the NIC 1 MAC address + 1. Two additional MAC addresses are assigned to the Baseboard Management Controller (BMC) embedded in the ESB-2. These MAC addresses are used by the BMC’s embedded network stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is assigned the NIC1 MAC address + 2, and BMC LAN Channel 2 is assigned the NIC1 MAC address + 3. 38 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture 3.5 Super I/O Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device. This chip contains all of the necessary circuitry to support the following functions: • • • • • GPIOs Two serial ports Keyboard and mouse support Wake up control System health support 3.5.1.1 Serial Ports The server board provides two serial ports: an external RJ45 serial port, and an internal DH10 serial header. Serial A is an optional port accessed through a 9-pin internal DH-10 header. A standard DH10 to DB9 cable can be used to direct the Serial A port to the rear of a chassis. The Serial A interface follows the standard RS232 pin-out as defined in the following table. Table 7. Serial A Header Pin-out Pin 1 2 3 4 5 6 7 8 9 Signal Name DCD DSR RX RTS TX CTS DTR RI GND Serial Port A Header Pin-out The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device. Using an RJ45 connector for a serial port allows direct support for serial port concentrators, which typically use RJ45 connectors and are widely used in the high-density server market. For server applications that use a serial concentrator to access the system management features of the server board, a standard 8-pin CAT-5 cable from the serial concentrator is plugged directly into the rear RJ45 serial port. To allow support for either of two serial port configuration standards, a jumper block located directly behind the rear RJ45 serial port must be configured appropriately according to the desired standard. For serial concentrators that require a DCD signal, the jumper block must be configured with the serial port jumper over pins 1 and 2. For serial concentrators that require a DSR signal (Default), the jumper block must be configured with the serial port jumper over pins 3 and 4. Pin 1 on the jumper is identified by “*”. Note: By default, the rear RJ45 serial port is configured to support a DSR signal. This configuration is compatible with the Cisco* standard. Revision 1.7 Intel order number: D31979-010 39 Functional Architecture Intel® Server Board S5000PAL / S5000XAL TPS J8A3 2 3 4 1-2: DCD to DTR 3-4: DSR to DTR (factory default) TP02303 Figure 15. Serial Port Configuration Jumper Location Pins 1-2 3-4 What happens at system reset… Serial port is configured for DCD to DTR Serial port is configured for DSR to DTR (default) For server applications that require a DB9 serial connector, an 8-pin RJ45-to-DB9 adapter must be used. The following table provides the pin-out required for the adapter to provide RS232 support. A standard DH10-to-DB9 cable and 8-pin RJ45 to DB9 DCD and DSR adapters are available from Intel in the Serial Port Accessory Kit, product code: AXXRJ45DB92. Table 8. Rear Serial B Port Adapter Pin-out RJ45 1 2 3 4 5 6 7 8 Signal Request to Send Data Terminal Ready Transmitted Data Signal Ground Ring Indicator Received Data DCD or DSR Clear To Send Abbreviation RTS 7 DTR TD SGND RI RD DCD/DSR CTS 4 3 5 9 2 1 or 6 (see note) 8 DB9 Note: The RJ45-to-DB9 adapter should match the configuration of the serial device used. One of two pinout configurations is used, depending on whether the serial device requires a DSR or DCD signal. The final adapter configuration should also match the desired pin-out of the RJ45 connector, as it can also be configured to support either DSR or DCD. 3.5.1.2 Floppy Disk Controller The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS does recognize USB floppy devices. 3.5.1.3 Keyboard and Mouse Support Dual stacked PS/2 ports, located on the back edge of the server board, are provided for keyboard and mouse support. Either port can support a mouse or keyboard. Neither port supports hot plugging. 40 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Functional Architecture 3.5.1.4 Wake-up Control The super I/O contains functionality that allows various events to power-on and power-off the system. 3.5.1.5 System Health Support The super I/O provides an interface via GPIOs for BIOS and Server Management Firmware to activate the Diagnostic LEDs, the FRU fault indicator LEDs for processors, DIMMs, fans and the system status LED. Refer to Figure 2. Light Guided Diagnostic LED Location Diagram for the location of the LEDs on the baseboard. The super I/O also provides PMW fan control to the system fans, monitors tach and presence signals for the system fans and monitors baseboard and control panel temperature. Revision 1.7 Intel order number: D31979-010 41 Platform Management Intel® Server Board S5000PAL / S5000XAL TPS 4. Platform Management The platform management sub-system on the server board is based on the integrated Baseboard Management Controller (BMC) features of the ESB-2. The on board platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board. See Appendix B for onboard sensor data. For more detailed platform management information, see the Intel® S5000 Server Board Family Datasheet. Figure 16. SMBUS Block Diagram 42 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5. 5.1 Connector / Header Locations and Pin-outs Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. Table 9 lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 9. Board Connector Matrix Connector Power supply Quantity 3 J3K4 J3K3 J1K1 J8G1, J5G1 J7B1,J7B2,J8B1,J8B2,J8B3,J9B1,J9B2, J9B3 J4F1 J5B1 J4G1 J1C5 J1B2 J3B1 J1E4 J3G1 J3K1, J3K2 J7A2, J7A1 J5K1, J9K1 BT1J1 J9A1 J5A1, J6A2 J1B1 J9A2 J6A1 JA8A1, JA8A2 Reference Designators Connector Type CPU Power Main Power P/S Aux CPU Sockets DIMM Sockets Card Edge Card Edge Card Edge Mezzanine Mezzanine Mezzanine Key Holder Shrouded Header Header Header Header Battery Holder PS2, stacked External Header External, RJ45 External, D-Sub External LAN connector with built-in magnetic Header Header Header Header Header Header Pin Count 8 24 5 771 240 280 98 120 120 30 50 3 44 4 4 4 3 12 4 9 10 15 14 CPU Main Memory Full Height Riser Low Profile Riser Bridge Board Connector RMM RMM NIC Intel I/O Expansion Module SATA RAID Key IDE (I/O + Power) Front System Fans #1 & #2 Rear System Fans #3 & #4 CPU Fans Battery Keyboard/Mouse Rear USB Serial Port A Serial Port B Video connector LAN connector 10/100/1000 SSI Control Panel Internal USB Intrusion detect Serial ATA LCP / AUX IPMB IPMB ® 2 8 1 1 1 1 1 1 1 1 2 2 2 1 1 2 1 1 1 2 1 1 2 6 1 1 J3H2 J1J1 J1C4 J1H1,J1G2,J1G1,J1F2,J1F1,J1E3 J1C2 J1C3 24 10 2 7 4 3 Revision 1.7 Intel order number: D31979-010 43 Connector / Header Locations and Pin-outs Connector System Recovery Setting Jumpers Quantity 4 Intel® Server Board S5000PAL / S5000XAL TPS Connector Type Jumper Pin Count 3 Reference Designators J1D1, J1D2, J1D3, J3H1 5.2 Power Connectors The main power supply connection is obtained using an SSI compliant 2x12 pin connector (J3K3). In addition, there are two additional power related connectors; one SSI compliant 2x4 pin power connector (J3K4) providing support for additional 12V, and one SSI compliant 1x5 pin connector (J1K1) providing I2C monitoring of the power supply. The following tables define the connector pin-outs. Table 10. Power Connector Pin-out (J3K3) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal +3.3Vdc +3.3Vdc GND +5Vdc GND +5Vdc GND PWR_OK 5VSB +12Vdc +12Vdc +3.3Vdc Color Orange Orange Black Red Black Red Black Gray Purple Yellow Yellow Orange Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal +3.3Vdc -12Vdc GND PS_ON# GND GND GND RSVD_(-5V) +5Vdc +5Vdc +5Vdc GND Color Orange Blue Black Green Black Black Black White Red Red Red Black Table 11. 12V Power Connector Pin-out (J3K4) Pin 1 2 3 4 5 6 7 8 GND GND GND GND +12Vdc +12Vdc +12Vdc +12Vdc Signal Color Black Black Black Black Yellow/Black Yellow/Black Yellow/Black Yellow/Black Table 12. Power Supply Signal Connector Pin-out (J1K1) Pin Signal 1 SMB_CLK_ESB_FP_PWR_R 2 3 4 5 SMB_DAT_ESB_FP_PWR_R SMB_ALRT_3_ESB_R 3.3V SENSE3.3V SENSE+ Color Orange Black Red Yellow Green 44 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5.3 System Management Headers 5.3.1 Intel® Remote Management Module (RMM) Connector A 120-pin Intel® RMM Connector (J1C5) is included on the server board for sole support of the optional Intel® Remote Management Module. There is no support for third party ASMI cards on this server board. Note: This connector is NOT compatible for use with Intel® Server Management Module Professional Edition (Product Code AXXIMMPRO) or the Intel® Server Management Module Advanced Edition (Product Code AXXIMMADV). Table 13. Intel® RMM Connector Pin-out (J1C5) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Signal Name Reserved - NC ESB_PLT_RST_G1_N GND Reserved - NC Reserved - NC GND GND USB_ESB_P7P USB_ESB_P7N GND P3V3 LPC_LAD LPC_LAD P3V3 LPC_LCLK P3V3 SMB_1_3V3SB_MS_DAT SMB_1_3V3SB_SL_DAT SMB_1_3V3SB_MS_CLK SMB_1_3V3SB_INT P3V3_AUX SPB_IMM_DSR_N SPB_IMM_RTS_N SPB_IMM_CTS_N SPB_IMM_DCD_N SPB_RI_N SPB_IMM_SOUT P3V3_AUX V_LCDCNTL3 P3V3_AUX Reserved - NC Reserved - NC GND V_LCDCNTL0 Reserved - NC GND Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 56 60 62 64 66 68 70 72 Signal Name GND Reserved - NC Reserved - NC GND GND Reserved - NC IRQ_SERIAL_R GND GND Reserved - NC Reserved - NC GND LPC_FRAME_N LPC_LAD LPC_LAD P3V3 SMB_IPMB_3V3SB_DAT SMB_IPMB_3V3SB_CLK SMB_0_3V3SB_MS_CLK SMB_0_3V3SB_INT SMB_0_3V3SB_MS_DAT SMB_0_3V3SB_SL_DAT P3V3_AUX FM_IMM_PRESENT_N SPB_IMM_DTR_N SPB_IMM_SIN P3V3_AUX V_LCDDATA7 V_LCDDATA6 V_LCDDATA5 V_LCDDATA4 V_LCDDATA3 V_LCDCNTL1 GND V_LCDDATA15 V_LCDDATA714 Revision 1.7 Intel order number: D31979-010 45 Connector / Header Locations and Pin-outs Pin 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 Signal Name V_LCDDATA23 V_LCDDATA22 V_LCDDATA21 V_LCDDATA20 V_LCDDATA19 GND FM_MAN_LAN_TYPE1 FM_MAN_LAN_TYPE1 Reserved - NC Reserved - NC MII_MDC_RMII_SPARE MII_COL_RMIIB_RXER GND MII_TXER_RMIIB_TXEN MII_MDIO_RMIIB_PRESENT GND MII_RXD3_RMIIB_RXD1 MII_RXD2_RMIIB_RXD0 GND MII_RXD1_RMIIA_RXD1 MII_RXD0_RMIIA_RXD0 GND MII_RXCLK MII_RXDV_RMIIA_CRS Intel® Server Board S5000PAL / S5000XAL TPS Pin 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 Signal Name V_LCDDATA13 V_LCDDATA12 V_LCDDATA11 GND V_LCDCNTL2 V_DVO_DDC_SDA V_DVO_DDC_SCL RST_PS_PWRGD Reserved - NC Reserved - NC Reserved - NC GND MII_CRS_RMIIB_CRS MII_TXCLK_RMIIB_RXCLK GND MII_TXD3_RMIIB_TXD1 MII_TXD2_RMIIB_TXD0 GND MII_TXD1_RMIIA_TXD1 MII_TXD0_RMIIA_TXD0 GND MII_TXEN_RMIIA_TXEN MII_RXER_RMIIA_TXER GND 5.3.2 Intel® RMM NIC Connector The server board provides an internal 30-pin mezzanine style connector (J1B2) to accommodate a proprietary form factor RMM NIC module. The following table details the pin-out of the RMM NIC module connector. Table 14. 30-pin Intel® RMM NIC Module Connector Pin-out (J1B2) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 Signal Name FM_MAN_LAN_TYPE2 FM_MAN_LAN_TYPE1 GND MII_TXCLK_RMIIB_RXCLK MII_CRS_RMIIB_CRS GND MII_TXD2_RMIIB_TXD0 MII_TXD1_RMIIA_TXD1 GND MII_TXD3_RMIIB_TXD1 MII_TXD0_RMIIA_TXD0 GND MII_TXEN_RMIIA_TXEN P3V3_AUX MII_RXER_RMIIA_RXER Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Signal Name MII_MDC_RMII_SPARE MII_COL_RMIIB_RXER GND MII_TXER_RMIIB_TXEN MII_MDIO_RMIIB_PRESENT GND MII_RXD3_RMIIB_RXD1 MII_RXD3_RMIIB_RXD0 GND MII_RXD1_RMIIA_RXD1 MII_RXD0_RMIIA_RXD0 GND MII_RXCLK P3V3_AUX MII_RXDV_RMIIA_CRS 46 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5.3.3 LCP/AUX IPMB Header Table 15. LPC/AUX IPMB Header Pin-out (J1C2) Pin 1 2 3 4 Signal Name SMB_IPMB_5VSB_DAT GND SMB_IPMB_5VSB_CLK P5V_STBY Description BMC IMB 5V Standby Data Line Ground BMC IMB 5V Standby Clock Line +5V Standby Power 5.3.4 IPMB Header Table 16. IPMB Header Pin-out (J1C3) Pin 1 2 3 Signal Name SMB_IPMB_5VSB_DAT GND SMB_IPMB_5VSB_CLK Description BMC IMB 5V Standby Data Line BMC IMB 5V Standby Clock Line 5.4 Riser Card Slots The server board has two riser card slots. The full height riser slot (J4F1) utilizes Intel® Adaptive Slot Technology. It is capable of supporting riser cards that support either the PCI-X* or PCI Express* full height / full length add-in cards. The low profile riser slot (J5B1) supports riser cards that support low profile PCI Express* add-in cards. The following tables show the pin-out for these riser slots. Table 17. Low-profile Riser Slot Pin-out (J5B1) Pin Side B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GND PE4_MCH_TXP_C 1 PCI Spec Signal P12V P12V P12V GND SMB_PCI3V3SB_CLK SMB_PCI3V3SB_DAT GND P3V3 PD_LPTRST_N P3V3_AUX PE_WAKE_N P3V3 GND PE4_MCH_TXP_C PE4_MCH_TXN_C GND 0 0 Pin Side A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PCI Spec Signal P12V P12V GND PD_LP_TCK PU_LP_TDI FP_CHASSIS_INTRU PU_LP_TMS P3V3 P3V3 PE_RST_LP_N GND CLK_100M_LP_PCIE_SLOT1_P CLK_100M_LP_PCIE_SLOT1_N GND PE4_MCH_RXP PE4_MCH_RXN GND P3V3 0 0 Revision 1.7 Intel order number: D31979-010 47 Connector / Header Locations and Pin-outs Pin Side B PCI Spec Signal 20 PE4_MCH_TXN_C 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 GND PE5_MCH_TXP_C PE5_MCH_TXN_C GND GND PE5_MCH_TXP_C PE5_MCH_TXN_C GND GND PE5_MCH_TXP_C PE5_MCH_TXN_C GND GND PE5_MCH_TXP_C PE5_MCH_TXN_C GND FM_LP_RISER_TYPE1 FM_LP_RISER_TYPE0 3 3 2 2 1 1 0 0 GND GND PE4_MCH_TXP_C PE4_MCH_TXN_C GND GND PE4_MCH_TXP_C PE4_MCH_TXN_C GND P3V3 3 3 2 2 Intel® Server Board S5000PAL / S5000XAL TPS Pin Side A 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 PCI Spec Signal GND PE4_MCH_RXP PE4_MCH_RXN GND GND PE4_MCH_RXP PE4_MCH_RXN GND GND PE4_MCH_RXP PE4_MCH_RXN GND CLK_100M_LP_PCIE_SLOT2_P CLK_100M_LP_PCIE_SLOT2_N GND PE5_MCH_RXP PE5_MCH_RXN GND GND PE5_MCH_RXP PE5_MCH_RXN GND GND PE5_MCH_RXP PE5_MCH_RXN GND GND PE5_MCH_RXP PE5_MCH_RXN GND 3 3 2 2 1 1 0 0 3 3 2 2 1 1 1 42 43 44 45 46 47 48 49 42 43 44 45 46 47 48 49 Table 18. Full-height Riser Slot Pin-out (J4F1) Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal 140 139 138 137 136 135 134 133 132 131 130 129 12V 12V Ground -12V 12V GND REFCLK2+ REFCLK2+ GND GND HSOp(0) HSOn(0) 140 139 138 137 136 135 134 133 132 131 130 129 12V 12V GND 3.3VAux Wake# 12V 3.3V PERST_N GND REFCLK1+ REFCLK1+ GND 48 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 GND GND HSOp(1) HSOn(1) GND GND HSOp(2) HSOn(2) GND GND HSOp(3) HSOn(3) GND GND HSOp(4) HSOn(4) GND GND HSOp(5) HSOn(6) GND GND HSOp(6) HSOn(6) GND GND HSOp(7) HSOn(7) GND +5V INTB# INTD# +5V Reserved +5V IOP INTA IOP INTB GND CLK3 GND CLK2 GND REQ2# GND Reserved GND KEY 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 HSIp(0) HSIn(0) GND GND HSIp(1) HSIn(1) GND GND HSIp(2) HSIn(2) GND GND HSIp(3) HSIn(3) GND GND HSIp(4) HSIn(4) GND GND HSIp(5) HSIn(5) GND GND HSIp(6) HSIn(6) GND GND HSIp(7) HSIn(7) GND ZCR_PRSNT_L +5V +5V ZCR_MSKID_L +5V INTA# INTC# GND REQ3# GND GNT3# GND RST# GND Reserved KEY Revision 1.7 Intel order number: D31979-010 49 Connector / Header Locations and Pin-outs Intel® Server Board S5000PAL / S5000XAL TPS Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal KEY 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Reserved GND CLK1 Ground REQ1# +3.3V PME2# AD[31] AD[29] Ground AD[27] AD[25] +3.3V C/BE[3]# AD[23] Ground AD[21] AD[19] +3.3V AD[17] C/BE[2]# Ground IRDY# +3.3V DEVSEL# PCI-XCAP LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] Ground AD[12] AD[10] M66EN Ground Ground AD[08] AD[07] +3.3V AD[05] AD[03] Ground AD[01] 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 KEY +5V Reserved GND GNT2# +3.3V GNT1# Ground PME1# PME3# AD[30] +3.3V AD[28] AD[26] Ground AD[24] RSVRD +3.3V AD[22] AD[20] Ground AD[18] AD[16] +3.3V FRAME# Ground TRDY# Ground STOP# +3.3V SMBD SMBCLK Ground PAR AD[15] +3.3V AD[13] AD[11] Ground AD[09] C/BE[0]# +3.3V AD[06] AD[04] Ground AD[02] AD[00] 50 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 KEY KEY 11 10 9 8 7 6 5 4 3 2 1 AD[41] Ground AD[39] AD[37] 3.3V AD[35] AD[33] Ground Type1 Type0 Size +3.3V ACK64# +5V +5V Reserved Ground C/BE[6]# C/BE[4]# Ground AD[63] AD[61] 3.3V AD[59] AD[57] Ground AD[55] AD[53] Ground AD[51] AD[49] 3.3V AD[47] AD[45] Ground AD[43] 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 KEY KEY 11 10 9 8 7 6 5 4 3 2 1 3.3V AD[40] AD[38] Ground AD[36] AD[34] Ground AD[32] PXH_RST_N Ground PXH_PWROK +3.3V REQ64# +5V +5V +5V C/BE[7]# C/BE[5]# Ground PAR64 AD[62] 3.3V AD[60] AD[58] Ground AD[56] AD[54] 3.3V AD[52] AD[50] Ground AD[48] AD[46] Ground AD[44] AD[42] Revision 1.7 Intel order number: D31979-010 51 Connector / Header Locations and Pin-outs Intel® Server Board S5000PAL / S5000XAL TPS 5.5 SSI Control Panel Connector The server board provides a 24-pin SSI control panel connector (J3H2) for use with non-Intel chassis. The following table provides the pin-out for this connector. Table 19. Front Panel SSI Standard 24-pin Connector Pin-out (J3H2) Pin 1 3 5 7 9 11 13 15 17 19 21 23 Signal Name P3V3_STBY Key FP_PWR_LED_L P3V3 HDD_LED_ACT_R FP_PWR_BTN_L GND Reset Button GND FP_ID_BTN_L TEMP_SENSOR FP_NMI_BTN_L Pin 2 4 6 8 10 12 14 16 18 20 22 24 Signal Name P3V3_STBY P5V_STBY FP_ID_LED_L FP_STATUS_LED1_R FP_STATUS_LED2_R LAN_ACT_A_L LAN_LINKA_L PS_I2C_3VSB_SDA PS_I2C_3VSB_SCL FP_CHASSIS_INTRU LAN_ACT_B_L LAN_LINKB_L 5.6 Bridge Board Connector For use in supported Intel® Server Chassis, the server board provides a 120-pin high-density bridge board connector (J4G1) to route control panel, mid-plane, and backplane signals from the server board to the specified system board. The following table provides the pin-outs for this connector. Table 20. 120-pin Bridgeboard Connector Pin-out (J4G1) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Signal Name SMB_HOST_3V3_CLK SMB_HOST_3V3_DAT FM_BRIDGE_PRESENT_N GND PE1_ESB_RXN_C PE1_ESB_RXP_C GND FM_FAN_D_PRSNT6 GND PE1_ESB_RXN_C PE1_ESB_RXP_C GND FM_FAN_D_PRSNT4 GND PE1_ESB_RXN_C PE1_ESB_RXP_C GND FM_RAID_PRESENT Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Signal Name GND PE1_ESB_TXN_C PE1_ESB_TXP_C GND PE_WAKE_N GND PE1_ESB_TXN_C PE1_ESB_TXP_C GND FM_FAN_D_PRSNT5 GND PE1_ESB_TXN_C PE1_ESB_TXP_C GND RST_MP_PWRGD GND PE1_ESB_TXN_C PE1_ESB_TXP_C 52 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Pin A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 Signal Name GND PE1_ESB_RXN_C PE1_ESB_RXP_C GND FM_FAN_D_PRSNT1 FM_FAN_D_PRSNT3 FM_FAN_D_PRSNT2 GND USB_ESB_P4P USB_ESB_P4N GND USB_ESB_OC_N USB_ESB_OC_N GND USB_ESB_P3P USB_ESB_P3N GND FP_NMI_BTN_N KEY BMC_RST_BTN_N FP_PWR_BTN_N FP_ID_BTN GND SMB_IPMB_ 5VSB_SDA SMB_IPMB_ 5VSB_CLK GND LED_ HDD_ACTIVITY_N P3V3 FP_PWR_LED_N_R P3V3_STBY FP_ID_LED_R1_N FM_SIO_TEMP_SENSOR LED_FAN3_FAULT LED_FAN2_FAULT LED_FAN1_FAULT FAN_PWM_CPU1 GND FAN_PWM_CPU2 PCI_FAN_TACH9 FAN_TACH7 FAN_TACH5 FAN_TACH3_H7 FAN_TACH1_H7 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 Pin B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 Connector / Header Locations and Pin-outs Signal Name GND FM_RAID_MODE GND CLK_100M_SRLAKE_N CLK_100M_SRLAKE_P GND SGPIO_DATAOUT1_R SGPIO_DATAOUT0_R SGPIO_LOAD_R SGPIO_CLOCK_N GND USB_ESB_P2P USB_ESB_P2N GND USB_ESB_OC_N NIC1_LINK_LED_N NIC1_ACT_LED_N LED_STATUS_GREEN_R1 KEY NIC2_LINK_LED_N NIC2_ACT_LED_N LED_STATUS_AMBER_R1 GND SMB_SN_3V3SB_DAT_BUF SMB_SN_3V3SB_CLK_BUF GND V_IO_HSYNC2_BUF_FP V_IO_VSYNC2_BUF_FP GND V_IO_BLUE_CONN_FP V_IO_GREEN_CONN_FP V_IO_RED_CONN_FP GND LED_FAN10_FAULT LED_FAN5_FAULT LED_FAN4_FAULT FAN_IO_PWM GND PCI_FAN_TACH10 FAN_TACH8 FAN_TACH6 FAN_TACH4_H7 FAN_TACH2_H7 Revision 1.7 Intel order number: D31979-010 53 Connector / Header Locations and Pin-outs Intel® Server Board S5000PAL / S5000XAL TPS 5.7 I/O Connector Pin-out Definition 5.7.1 VGA Connector The following table details the pin-out definition of the VGA connector (J6A1). Table 21. VGA Connector Pin-out (J6A1) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal Name V_IO_R_CONN V_IO_G_CONN V_IO_B_CONN TP_VID_CONN_B4 GND GND GND GND TP_VID_CONN_B9 GND TP_VID_CONN_B11 V_IO_DDCDAT V_IO_HSYNC_CONN V_IO_VSYNC_CONN V_IO_DDCCLK Description Red (analog color signal R) Green (analog color signal G) Blue (analog color signal B) No connection Ground Ground Ground Ground No Connection Ground No connection DDCDAT HSYNC (horizontal sync) VSYNC (vertical sync) DDCCLK 5.7.2 NIC Connectors The server board provides two RJ45 NIC connectors oriented side by side on the back edge of the board (JA8A1, JA8A2). The pin-out for each connector is identical and is defined in the following table. Table 22. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2) Pin 1 2 3 4 5 6 7 8 9 10 11 (D1) 12 (D2) 13 (D3) 14 15 16 GND P1V8_NIC NIC_A_MDI3P NIC_A_MDI3N NIC_A_MDI2P NIC_A_MDI2N NIC_A_MDI1P NIC_A_MDI1N NIC_A_MDI0P NIC_A_MDI0N NIC_LINKA_1000_N (LED NIC_LINKA_100_N (LED) NIC_ACT_LED_N NIC_LINK_LED_N GND GND Signal Name 54 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5.7.3 IDE Connector The server board includes an IDE connector to access the single IDE channel from the ESB-2 IO controller hub. The design intent for this connector is to provide IDE support for a single slim-line optical drive, such as CDROM or DVD. The connector is not a standard 40-pin IDE connector, instead it has 44 pins providing support for both power and IO signals. The pin-out for this connector is defined in the following table. Table 23. 44-pin IDE Connector Pin-out (J3G1) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Signal Name ESB_PLT_RST_IDE_N RIDE_DD_7 RIDE_DD_6 RIDE_DD_5 RIDE_DD_4 RIDE_DD_3 RIDE_DD_2 RIDE_DD_1 RIDE_DD_0 GND RIDE_DDREQ RIDE_DIOW_N RIDE_DIOR_N RIDE_PIORDY RIDE_DDACK_N IRQ_IDE RIDE_DA1 RIDE_DA0 RIDE_DCS1_N LED_IDE_N P5V GND Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 GND RIDE_DD_8 RIDE_DD_9 RIDE_DD_10 RIDE_DD_11 RIDE_DD_12 RIDE_DD_13 RIDE_DD_14 RIDE_DD_15 KEY GND GND GND GND GND TP_PIDE_32 IDE_PRI_CBLSNS RIDE_DA2 RIDE_DCS3_N GND P5V GND Signal Name 5.7.4 Intel® I/O Expansion Module Connector The server board provides an internal 50-pin mezzanine style connector (J3B1) to accommodate proprietary form factor Intel® I/O Expansion Modules, which expand the IO capabilities of the server board without sacrificing an add-in slot from the riser cards. There are three planned IO modules for use on this server board: external 4 port SAS, dual Gb NIC, and Infiniband*. For more detail on the supported IO modules, please refer to the Intel® Server Board S5000PAL / S5000XAL IO Module Hardware Specification. The following table details the pin-out of the Intel® I/O Expansion Module connector. Revision 1.7 Intel order number: D31979-010 55 Connector / Header Locations and Pin-outs Intel® Server Board S5000PAL / S5000XAL TPS Table 24. 50-pin Intel® I/O Expansion Module Connector Pin-out (J3B1) Pin 1 3 5 7 9 11 13 15 17 19 21 22 25 27 29 31 33 35 37 39 41 43 45 47 49 Signal Name P3V3_AUX PE_RST_G2_PM_N GND GND PE2_ESB_TXP_C PE2_ESB_TXN_C GND GND PE2_ESB_TXP_C PE2_ESB_TXN_C GND GND PE2_ESB_TXP_C PE2_ESB_TXN_C GND GND PE2_ESB_TXP_C PE2_ESB_TXN_C GND GND PE_WAKE_N P3V3 P3V3 P3V3 P3V3 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Signal Name P3V3_AUX GND PE2_ESB_RXP_C PE2_ESB_RXN_C GND GND PE2_ESB_RXP_C PE2_ESB_RXN_C GND GND PE2_ESB_RXP_C PE2_ESB_RXN_C GND GND PE2_ESB_RXP_C PE2_ESB_RXN_C GND GND CLK_100M_LP_PCIE_SLOT3_P CLK_100M_LP_PCIE_SLOT3_N GND P3V3 P3V3 P3V3 P3V3 5.7.5 SATA Connectors The server board provides six SATA (Serial ATA) connectors: SATA-0 (J1H1), SATA-1 (J1G2), SATA-2 (J1G1), SATA-3 (J1F2), SATA-4 (J1F1), and SATA-5 (J1E3), for use with an internal SATA backplane. The pin configuration for each connector is identical and is defined in the following table. Table 25. SATA Connector Pin-out (J1H1, J1G2, J1G1, J1F2, J1E3) Pin 1 2 3 4 5 6 7 Signal Name GND SATA#_TX_P_C SATA#_TX_N_C GND SATA#_RX_N_C SATA#_RX_P_C GND Description GND1 Positive side of transmit differential pair Negative side of transmit differential pair GND2 Negative side of Receive differential pair Positive side of Receive differential pair GND3 56 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5.7.6 Serial Port Connectors The server board provides one external RJ45 Serial ‘B’ port (J9A2) and one internal 9-pin Serial ‘A’ port header (J1B1). The following tables define the pin-outs for each. Table 26. External RJ-45 Serial ‘B’ Port Pin-out (J9A2) Pin 1 2 3 4 5 6 7 8 Note: A jumper block on the server board will determine whether DSR or DCD is routed to pin 7. The board will have the jumper block configured with DSR enabled at production. 1 Signal Name SPB_RTS SPB_DTR SPB_OUT_N GND SPB_RI SPB_SIN_N SPB_DSR _DCD SPB_CTS Description RTS (request to send) DTR (Data terminal ready) TXD (Transmit data) Ground RI (Ring Indicate) RXD (receive data) Data Set Ready / Data Carrier Detect 1 CTS (clear to send) Table 27. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) Pin 1 2 3 4 5 6 7 8 9 Signal Name SPA_DCD SPA_DSR SPA_SIN_L SPA_RTS SPA_SOUT_N SPA_CTS SPA_DTR SPA_RI GND Description DCD (carrier detect) DSR (data set ready) RXD (receive data) RTS (request to send) TXD (Transmit data) CTS (clear to send) DTR (Data terminal ready) RI (Ring Indicate) Ground 5.7.7 Keyboard and Mouse Connector Two stacked PS/2 ports (J9A1) are provided to support both a keyboard and a mouse. Either PS/2 port can support a mouse or keyboard. The following table details the pin-out of the PS/2 connector. Table 28. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) Pin 1 2 3 4 5 6 7 8 9 Signal Name KB_DATA_F TP_PS2_2 GND P5V_KB_F KB_CLK_F TP_PS2_6 MS_DAT_F TP_PS2_8 GND Description Keyboard Data Test point – keyboard Ground Keyboard / mouse power Keyboard Clock Test point – keyboard / mouse Mouse Data Test point – keyboard / mouse Ground Revision 1.7 Intel order number: D31979-010 57 Connector / Header Locations and Pin-outs Pin 10 11 12 13 14 15 16 17 Signal Name P5V_KB_F MS_CLK_F TP_PS2_12 GND GND GND GND GND Intel® Server Board S5000PAL / S5000XAL TPS Description Keyboard / mouse power Mouse Clock Test point – keyboard / mouse Ground Ground Ground Ground Ground 5.7.8 USB 2.0 Connectors The following table details the pin-out of the external USB connectors (J5A1, J6A2) found on the back edge of the server board. Table 29. External USB Connector Pin-out (J5A1, J6A2) Pin Signal Name 1 USB_OC#_FB_1 2 3 4 USB_P#N_FB_2 USB_P#N_FB_2 GND Description USB_PWR DATAL0 (Differential data line paired with DATAH0) DATAH0 (Differential data line paired with DATAL0) Ground One 2x5 header on the server board (J1J1) provides an option to support an additional two USB 2.0 ports. The pin-out of the connector is detailed in the following table. Table 30. Internal USB Connector Pin-out (J1J1) Pin 1 2 3 4 5 6 7 8 9 10 Signal Name P5V_USB2_VBUS0 P5V_USB2_VBUS1 Description USB Power (Ports 0,1) USB Power (Ports 0,1) USB_ESB_P0N_CONN USB Port 0 Negative Signal USB_ESB_P1N_CONN USB Port 0 Positive Signal USB_ESB_P0P_CONN USB_ESB_P1P_CONN Ground Ground -TP_USB_ESB_NC No Pin TEST POINT USB Port 1 Negative Signal USB Port 1 Positive Signal 58 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs 5.8 Fan Headers The server board incorporates three system fan circuits which support a total of six SSI compliant 4-pin fan connectors. Two fan connectors are designated as processor cooling fans, CPU1 Fan (J9K1) and CPU2 Fan (J5K1). These connectors can support CPU fans that draw a maximum of 1.2 Amps each. Two system fan connectors can be found towards the front edge of the server board, System Fan 1 (J3K1), System Fan 2 (J3K2). These connectors are capable of supporting a maximum fan load of 3.5 Amps each. Two additional system fan connectors can be found near the back edge of the server board, System Fan 3(J7A1) and System Fan 4 (J7A2). These two connectors are capable of supporting a maximum fan load of 2.5 Amps per connector. With the proper Sensor Data Record (SDR) installed, Server Management software can monitor all system fans in use. The pin configuration for each fan connector is identical and is defined in the following table. Table 31. SSI Fan Connector Pin-out (J9K1,J5K1,J3K1,J3K2,J7A2,J7A1) Pin 1 2 3 4 Signal Name Ground 12V Fan Tach Fan PWM Type GND Power Out In Description GROUND is the power supply ground Power supply 12V FAN_TACH signal is connected to the BMC to monitor the fan speed FAN_PWM signal to control fan speed Note: Intel Corporation server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits Revision 1.7 Intel order number: D31979-010 59 Jumper Block Settings Intel® Server Board S5000PAL / S5000XAL TPS 6. Jumper Block Settings The server board has several 2-pin and 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “▼”. 6.1 Recovery Jumper Blocks Table 32. Recovery Jumpers (J1D1, J1D2, J1D3) Jumper Name J1D1: BMC Force Update J1D2: Password Clear J1D3: CMOS Clear Pins 1-2 2-3 What happens at system reset… BMC Firmware Force Update Mode – Disabled (Default) BMC Firmware Force Update Mode – Enabled These pins should have a jumper in place for normal system operation. (Default) If these pins are jumpered, administrator and user passwords will be cleared immediately. These pins should not be jumpered for normal operation. These pins should have a jumper in place for normal system operation. (Default) If these pins are jumpered, the CMOS settings will be cleared immediately. These pins should not be jumpered for normal operation 1-2 2-3 1-2 2-3 BMC Force Update Mode Disable 2 3 J1D2 Password Reset 2 Enable 3 J1D1 2 3 J1D3 Clear CMOS TP02080 Figure 17. Recovery Jumper Blocks (J1D1, J1D2, J1D3) 60 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Jumper Block Settings 6.1.1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1D3) and Password Reset (J1D2) recovery features are designed so that the desired operation can be achieved with minimal system down time. The usage procedure for these two features has changed from previous generation Intel® Server Boards. The following procedure outlines the new usage model. CMOS Clear Procedure: 1. Power down the server; do not remove AC power. 2. Open the server and move the jumper from the default operating position (pins1-2) to the “clear” position (pins 2-3). 3. Wait 5 seconds. 4. Move the jumper back to the default position (pins 1-2). 5. Close the server system and power up the server. 6. CMOS is now cleared and can be reset by going into the BIOS setup. Password Reset Procedure: 1. Power down the server; do not remove AC power. 2. Open the server and move the jumper from the default operating position (pins1-2) to the “reset” position (pins 2-3). 3. Power up the server. 4. The password is now cleared. 5. Power down the server; do not remove AC power. 6. Move the jumper back to the default position (pins 1-2) and close the server system. 7. The password can be reset by going into the BIOS setup. Note: Removing AC power before performing the CMOS clear operation will cause the system to automatically power up and immediately power down, after the procedure is followed and AC power is reapplied. Should this occur, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power up system and proceed to the BIOS Setup Utility to reset desired settings. 6.1.2 BMC Force Update Procedure When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state, the server board provides a BMC Force Update jumper (J1D1) which will force the BMC into the proper update state. The following procedure should be following in the event the standard BMC firmware update process fails. • • • • • • • • Power down the server and remove AC power. Open the server and move the jumper from the default operating position (pins1-2) to the “enabled” position (pins 2-3). Close the server system and reconnect AC power and power up the server. Perform the standard BMC firmware update procedure as documented in README.TXT file that is included in the given BMC Firmware Update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating that the BMC is still in update mode. Power down and remove AC power. Open the server and move the jumper from the “enabled” position (pins 2-3) to the “disabled” position (pins 1-2). Close the server system and reconnect AC power and power up the server. Revision 1.7 Intel order number: D31979-010 61 Jumper Block Settings Intel® Server Board S5000PAL / S5000XAL TPS Note: Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position. The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default – disabled position when the server is running normally. 6.2 BIOS Select Jumper The jumper block at J3H1, located just to the left of the SSI control panel header, is used to select which BIOS image the system will boot to. Pin 1 on the jumper is identified with a ‘▼’. This jumper should only be moved if you wish to force the BIOS to boot to the secondary bank which may hold a different version of BIOS. The rolling BIOS feature of the baseboard will automatically alternate the Boot BIOS to the secondary bank in the event the BIOS image in the primary bank is corrupted and cannot boot for any reason. 3 2 3 2 1-2: Force BIOS to bank 0 J3H1 2-3: System is configured for normal operation (factory default) TP02305 Figure 18. BIOS Select Jumper (J3H1) Pins 1-2 2-3 What happens at system reset… Force BIOS to bank 0 System is configured for normal operation (Default) Note: When performing a BIOS update procedure, the BIOS select jumper must be set to its default position (pins 2-3). 62 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Jumper Block Settings 6.3 External RJ45 Serial Port Jumper Block The jumper block J8A3, located directly behind the external RJ45 serial port, is used to configure either a DSR or a DCD signal to the connector. J8A3 2 3 4 1-2: DCD to DTR 3-4: DSR to DTR (factory default) TP02303 Figure 19. External RJ45 Serial Port Configuration Jumper Revision 1.7 Intel order number: D31979-010 63 Light Guided Diagnostics Intel® Server Board S5000PAL / S5000XAL TPS 7. Light Guided Diagnostics The server board has several on-board diagnostic LEDs to assist in troubleshooting board level issues. This section shows where each LED is located and provides a high level usage description. For a more detailed description of what drives the diagnostic LED operation, refer to the Intel® S5000 Series Chipsets Server Board Family Datasheet. 7.1 5-Volt Standby LED Several server management features of this server board require that a 5 volt stand-by voltage be supplied from the power supply. Some of the features and components that require this voltage be present when the system is “Off” include the BMC within the ESB-2, onboard NICs, and optional Intel® RMM. The LED located just below the system recovery jumper block labeled “5V STBY” is illuminated when AC power is applied to the platform and 5 Volt standby voltage is supplied to the server board by the power supply. TP02307 Figure 20. 5V Standby Status LED Location 64 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Light Guided Diagnostics 7.2 System ID LED and System Status LED The server board provides LEDs for both System ID and System Status. ID LED Status LED TP02309 Figure 21. System ID LED and System Status LED Locations. The blue “System ID” LED can be illuminated using either of two mechanisms. • • By pressing the System ID Button on the system control panel the ID LED will display a solid blue color, until the button is pressed again. By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either blink blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issued to turn it off. Revision 1.7 Intel order number: D31979-010 65 Light Guided Diagnostics Intel® Server Board S5000PAL / S5000XAL TPS The bi-color System Status LED will operate as follows: Color Off Green / Amber Green Green State N/A Alternating Blink Solid on Blink Criticality Not ready Not ready System OK Degraded Description AC power off Pre DC Power On – 15-20 second BMC Initialization when AC is applied to the server. Control Panel buttons are disabled until BMC initialization is complete. System booted and ready. System degraded • Unable to use all of the installed memory (more than one DIMM installed). • Correctable errors over a threshold of 10 and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED should light up. • In mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2). • Redundancy loss such as power-supply or fan. This does not apply to non-redundant sub-systems. • PCI-e link errors • CPU failure / disabled – if there are two processors and one of them fails • Fan alarm – Fan failure. Number of operational fans should be more than minimum number needed to cool the system • Non-critical threshold crossed – Temperature and voltage • Chassis Intrusion events, including lost LAN connection Non-fatal alarm – system is likely to fail • Critical voltage threshold crossed • • • Amber Solid on Critical, nonrecoverable VRD hot asserted Minimum number of fans to cool the system not present or failed In non-sparing and non-mirroring mode if the threshold of ten correctable errors is crossed within the window Amber Blink Non-critical Fatal alarm – system has failed or shutdown • DIMM failure when there is one DIMM present, no good memory present • Run-time memory uncorrectable error in non-redundant mode • IERR signal asserted • Processor 1 missing • Temperature (CPU ThermTrip, memory TempHi, critical threshold crossed) • No power good – power fault • Processor configuration error (for instance, processor stepping mismatch) 7.2.1 System Status LED – BMC Initialization When the AC power is first applied to the system and 5V-STBY is present, the BMC controller on the server board requires 15-20 seconds to initialize. During this time, the system status LED will blink, alternating between amber and green, and the power button functionality of the control panel is disabled preventing the server from powering up. Once BMC initialization has completed, the status LED will stop blinking and the power button functionality is restored and can be used to turn on the server. 66 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Light Guided Diagnostics 7.3 DIMM Fault LEDs The server board provides a memory fault LED for each DIMM slot. The DIMM fault LED is illuminated when the system BIOS disables the specified DIMM after it reaches a specified number of given failures or if specific critical DIMM failures are detected. See the Intel® S5000 Series Chipsets Server Board Family Datasheet for more details. TP02310 Figure 22. DIMM Fault LED Locations 7.4 Processor Fault LED The server board provides a Processor Fault LED for each of the two processor sockets. These LEDs will illuminate when a CPU is disabled or a CPU configuration error is detected. CPU 2 CPU 1 TP02311 Figure 23. Processor Fault LED Location Revision 1.7 Intel order number: D31979-010 67 Light Guided Diagnostics Intel® Server Board S5000PAL / S5000XAL TPS 7.5 Post Code Diagnostic LEDs During the system boot process, BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, BIOS will display the given POST code to the POST code diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the diagnostic LEDs can be used to identify the last POST process to be executed. See Appendix C for a complete description of how these LEDs are read, and for a list of all supported POST codes. TP02312 Figure 24. POST Code Diagnostic LED Location 68 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications 8. 8.1 Power and Environmental Specifications Intel® Server Board S5000PAL / S5000XAL Design Specifications Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 33: Server Board Design Specifications Operating Temperature Non-Operating Temperature DC Voltage Shock (Unpackaged) Shock (Packaged) < 20 lbs ≥ 20 to < 40 ≥ 40 to < 80 ≥ 80 to < 100 ≥100 to < 120 ≥120 Vibration (Unpackaged) Note: 1 0º C to 55º C (32º F to 131º F) -40º C to 70º C (-40º F to 158º F) ± 5% of all nominal voltages Trapezoidal, 50 g, 170 inches/sec 36 inches 30 inches 24 inches 18 inches 12 inches 9 inches 5 Hz to 500 Hz 3.13 g RMS random 1 Chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel Xeon processor 5000 sequence maximum case temperature. ® ® Disclaimer Note: Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Revision 1.7 Intel order number: D31979-010 69 Power and Environmental Specifications Intel® Server Board S5000PAL / S5000XAL TPS 8.2 Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel® Server Board S5000PAL / S5000XAL, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on this server board. Figure 25. Power Distribution Block Diagram 8.2.1 Processor Power Support The server board supports the Thermal Design Point (TDP) guideline for Dual-Core Intel® Xeon® processors 5000 sequence. The Flexible Motherboard Guidelines (FMB) has also been followed to help determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and TCASE for the Dual-Core Intel® Xeon® processor 5000 sequence family. Table 34. Dual-Core Intel® Xeon® Processor 5000 Sequence TDP Guidelines per processor TDP Power 130 W Max TCASE 70º C Icc MAX 150 A Note: These values are for reference only. The Dual-Core Intel® Xeon® processor 5000 sequence Datasheet contains the actual specifications for the processor. If the values found in the Dual-Core Intel® Xeon® processor 5000 sequence Datasheet are different than those published here, the Dual-Core Intel® Xeon® processor 5000 sequence Datasheet values will supersede these, and should be used. 70 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications 8.2.2 Power Supply Output Requirements This section is for reference purposes only. Its intent is to provide guidance to system designers for determining a proper power supply for use with this server board. The contents of this section specify the power supply requirements Intel used to develop a power supply for its 1U server platform. The combined power of all outputs shall not exceed the rated output power of the power supply. The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions. Table 35. 600W Load Ratings Voltage +3.3 V +5 V +12 V1 +12 V2 +12 V3 +12 V4 -12 V +5 VSB 1. 2. 3. 4. 5. 6. Minimum Continuous 1.5 A 1.0 A 0.5 A 0.5 A 0.5 A 0.5 A 0A 0.1 A Maximum Continuous 10 A 20 A 16 A 16 A 16 A 16 A 0.5 A 3.0 A Peak 18 A 18 A 3.5 A Maximum continuous total DC output power should not exceed 600W. Peak load on the combined 12 V output shall not exceed 49A. Maximum continuous load on the combined 12 V output shall not exceed 44A. Peak total DC output power should not exceed 650W. Peak power and current loading shall be supported for a minimum of 12 seconds. Combined 3.3V and 5V power shall not exceed 100W. 8.2.3 Turn On No Load Operation At power on the system shall present a no load condition to the power supply. In this no load state the voltage regulation limits for the 3.3V and 5V are relaxed to +/-10% and the +12V rails relaxed to +10/-8%. When operating loads are applied the voltages must regulated to there normal limits. Table 36: No load operating range Voltage +3.3 V +5 V +12 V1 +12 V2 +12 V3 +12 V4 -12 V +5 VSB Minimum Continuous 0A 0A 0A 0A 0A 0A 0A 0.1 A Maximum Continuous 7A 5A 5A 5A 6A 5A 0.5 A 3.0 A Peak 7A 7A 3.5 A Revision 1.7 Intel order number: D31979-010 71 Power and Environmental Specifications Intel® Server Board S5000PAL / S5000XAL TPS 8.2.4 Grounding The grounds of the pins of the power supply output connector provide the power return path. The output connector ground pins shall be connected to safety ground (power supply enclosure). This grounding should be well designed to ensure passing the maximum allowed Common Mode Noise levels. The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 mΩ. This path may be used to carry DC current. 8.2.5 Standby Outputs The 5VSB output shall be present when an AC input greater than the power supply turn on voltage is applied. 8.2.6 Remote Sense The power supply has remote sense return (ReturnS) to regulate out ground drops for all output voltages: +3.3V, +5V, +12V1, +12V2, +12V3, -12V, and 5VSB. The power supply uses remote sense (3.3VS) to regulate out drops in the system for the +3.3V output. The +5V, +12V1, +12V2, +12V3, –12V and 5VSB outputs only use remote sense referenced to the ReturnS signal. The remote sense input impedance to the power supply must be greater than 200 Ω on 3.3VS and 5VS; this is the value of the resistor connecting the remote sense to the output voltage internal to the power supply. Remote sense must be able to regulate out a minimum of a 200 mV drop on the +3.3V output. The remote sense return (ReturnS) must be able to regulate out a minimum of a 200 mV drop in the power ground return. The current in any remote sense line shall be less than 5 mA to prevent voltage sensing errors. The power supply must operate within specification over the full range of voltage drops from the power supply’s output connector to the remote sense points. 8.2.7 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. Table 37. Voltage Regulation Limits PARAMETER + 3.3V + 5V + 12V1,2,3,4 - 12V + 5VSB TOLERANCE - 5% / +5% - 5% / +5% - 5% / +5% - 5% / +9% - 5% / +5% MIN +3.14 +4.75 +11.40 -10.80 +4.75 NOM +3.30 +5.00 +12.00 -12.00 +5.00 MAX +3.46 +5.25 +12.60 -13.20 +5.25 UNITS Vrms Vrms Vrms Vrms Vrms 72 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications 8.2.8 Dynamic Loading The output voltages shall remain within limits for the step loading and capacitive loading specified in the table below. The load transient repetition rate shall be tested between 50 Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The Δ step load may occur anywhere within the MIN load to the MAX load conditions. Table 38. Transient Load Requirements Output +3.3V +5V 12V1+12V2+12V3+12 V4 +5VSB Notes: 1) Step loads on each 12V output may happen simultaneously. 2) The +12V should be tested with 2200μF evenly split between the four +12V rails. Δ Step Load Size (See note 2) 5.0A 6.0A 28.0A 0.5A Load Slew Rate 0.25 A/μsec 0.25 A/μsec 0.25 A/μsec 0.25 A/μsec Test capacitive Load 250 μF 400 μF 1,2 2200 μF 20 μF 8.2.9 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges. Table 39. Capacitive Loading Conditions Output +3.3V +5V +12V1,2,3,4 -12V +5VSB MIN 250 400 500 each 1 20 MAX 6,800 4,700 11,000 350 350 Units μF μF μF μF μF 8.2.10 Closed-Loop Stability The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges. A minimum of: 45 degrees phase margin and -10dB-gain margin is required. Closed-loop stability must be ensured at the maximum and minimum loads as applicable. 8.2.11 Common Mode Noise The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency band of 10Hz to 30MHz. 1. The measurement shall be made across a 100 Ω resistor between each of the DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure). 2. The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent. Revision 1.7 Intel order number: D31979-010 73 Power and Environmental Specifications Intel® Server Board S5000PAL / S5000XAL TPS 8.2.12 Ripple / Noise The maximum allowed ripple/noise output of the power supply is defined in the following table. This is measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor are placed at the point of measurement. Table 40. Ripple and Noise +3.3V 50mVp-p +5V 50mVp-p +12V1/2/3/4 120mVp-p -12V 120mVp-p +5VSB 50mVp-p 8.2.13 Soft Starting The power supply shall contain a control circuit which provides a monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5 V standby, but the turn on/off shall be monotonic. 8.2.14 Timing Requirements These are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms, except for 5VSB; it is allowed to rise from 1.0 to 25 ms. All outputs must rise monotonically. Each output voltage shall reach regulation within 50 ms (Tvout_on) of each other during turn on of the power supply. Each output voltage shall fall out of regulation within 400 msec (Tvout_off) of each other during turn off. The following diagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low, and the PSON signal with the AC input applied. 74 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications Table 41. Output Voltage Timing Item Tvout_rise Tvout_on Description MIN Output voltage rise time from each main output. 5.0 * All main outputs must be within regulation of each other within this time. Tvout_off All main outputs must leave regulation within this time. 1 The 5VSB output voltage rise time shall be from 1.0ms to 25.0ms MAX 70 50 1 UNITS msec msec msec 400 V out 10% V out V1 V2 V3 V4 Tvout_rise Tvout_on Tvout_off TP02313 Figure 26. Output Voltage Timing Revision 1.7 Intel order number: D31979-010 75 Power and Environmental Specifications Intel® Server Board S5000PAL / S5000XAL TPS Table 42. Turn On/Off Timing Item Tsb_on_delay Tac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay Tpson_pwok Tpwok_on Tpwok_off Tpwok_low Tsb_vout T5VSB_holdup Description Delay from AC being applied to 5VSB being within regulation. Delay from AC being applied to all output voltages being within regulation. Time all output voltages stay within regulation after loss of AC. Measured at 60% of maximum load. Delay from loss of AC to de-assertion of PWOK. Measured at 60% of maximum load. # Delay from PSON active to output voltages within regulation limits. # Delay from PSON de-active to PWOK being de-asserted. Delay from output voltages within regulation limits to PWOK asserted at turn on. Delay from PWOK de-asserted to output voltages (3.3V, 5V, 12V, -12V) dropping out of regulation limits. Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal. Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on. Time the 5VSB output voltage stays within regulation after loss of AC. MIN MAX 1500 2500 21 20 5 400 50 100 1 100 50 70 1000 500 UNITS msec msec msec msec msec msec msec msec msec msec msec AC Input Tvout_holdup V out TAC_on_delay Tsb_on_delay Tpwok_on Tpwok_holdup Tpwok_off Tpwok_low Tsb_on_delay Tpwok_on PWOK Tpwok_off Tpson_pwok 5 VSB Tsb_vout T5VSB_holdup PSON Tpson_on_delay AC turn on/off cycle PSON turn on/off cycle TP02314 Figure 27. Turn On/Off Timing (Power Supply Signals) 76 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications 8.2.15 Residual Voltage Immunity in Standby Mode The power supply shall be immune to any residual voltage placed on its outputs (typically a leakage voltage through the system from standby output) up to 500 mV. There shall be no additional heat generated, nor stress of any internal components with this voltage applied to any individual output, and all outputs simultaneously. It also should not trip the power supply protection circuits during turn on. Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV when AC voltage is applied and the PSON# signal is de-asserted. Revision 1.7 Intel order number: D31979-010 77 Regulatory and Certification Information Intel® Server Board S5000PAL / S5000XAL TPS 9. Regulatory and Certification Information 9.1 Product Regulatory Compliance Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product categories and environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, may require further evaluation. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device. The following table references Server Board Compliance and markings that may appear on the product. Markings below are typical markings however, may vary or be different based on how certification is obtained. Note: Certifications Emissions requirements are to Class A 9.1.1 Product Safety & Electromagnetic (EMC) Compliance Compliance Reference Marking Example Compliance Regional Compliance Description Reference Australia / New Zealand AS/NZS 3548 (Emissions) N232 Canada / USA CSA 60950 – UL 60950 (Safety) Industry Canada ICES-003 (Emissions) CANADA ICES-003 CLASS A CANADA NMB-003 CLASSE A CENELEC Europe International Korea Low Voltage Directive 93/68/EEC; EMC Directive 89/336/EEC EN55022 (Emissions) EN55024 (Immunity) CE Declaration of Conformity CB Certification – IEC60950 CISPR 22 / CISPR 24 RRL Certification MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) BSMI CNS13438 None Required 인증번호: CPU-Model Name (A) Taiwan D33025 78 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Regulatory and Certification Information 9.2 Electromagnetic Compatibility Notices 9.2.1 FCC Verification Statement (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 Phone: 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • • • • Reorient or relocate the receiving antenna. Increase the separation between the equipment and the receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product. All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception. 9.2.2 ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,” ICES-003 of the Canadian Department of Communications. 9.2.3 Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance. Revision 1.7 Intel order number: D31979-010 79 Regulatory and Certification Information Intel® Server Board S5000PAL / S5000XAL TPS 9.2.4 BSMI (Taiwan) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 9.2.5 RRL (Korea) Following is the RRL certification information for Korea. English translation of the notice above: 1. 2. 3. 4. 5. Type of Equipment (Model Name): On License and Product Certification No.: On RRL certificate. Obtain certificate from local Intel representative Name of Certification Recipient: Intel Corporation Date of Manufacturer: Refer to date code on product Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product 80 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Regulatory and Certification Information 9.3 Product Ecology Compliance Intel has a system in place to restrict the use of banned substances in accordance with world wide product ecology regulatory requirements. The following is Intel’s product ecology compliance criteria. Compliance Regional Description Compliance Reference Compliance Reference Marking Example California California Code of Regulations, Title 22, Division 4.5; Chapter 33: Best Management Practices for Perchlorate Materials. Special handling may apply. See www.dtsc.ca.gov/hazar douswaste/perchlorate This notice is required by California Code of Regulations, Title 22, Division 4.5; Chapter 33: Best Management Practices for Perchlorate Materials. This product / part include a battery which contains Perchlorate material. China China RoHS Administrative Measures on the Control of Pollution Caused by Electronic Information Products” (EIP) #39. Referred to as China RoHS. Mark requires to be applied to retail products only. Mark used is the Environmental Friendly Use Period (EFUP). Number represents years. China Recycling (GB18455-2001) Mark requires to be applied to be retail product only. Marking applied to bulk packaging and single packages. Not applied to internal packaging such as plastics, foams, etc. Intel Internal Specification All materials, parts and subassemblies must not contain restricted materials as defined in Intel’s Environmental Product Content Specification of Suppliers and Outsourced Manufacturers – None Required http://supplier.intel.com/ehs/environmental.htm Europe European Directive 2002/95/EC Restriction of Hazardous Substances (RoHS) Threshold limits and banned substances are noted below. Quantity limit of 0.1% by mass (1000 PPM) for: Lead, Mercury, Hexavalent Chromium, Polybrominated Biphenyls Diphenyl Ethers (PBB/PBDE) Quantity limit of 0.01% by mass (100 PPM) for: Cadmium None Required Germany German Green Dot Applied to Retail Packaging Only for Boxed Boards Revision 1.7 Intel order number: D31979-010 81 Regulatory and Certification Information Compliance Regional Description Intel® Server Board S5000PAL / S5000XAL TPS Compliance Reference Marking Example Compliance Reference Intel Internal Specification All materials, parts and subassemblies must not contain restricted materials as defined in Intel’s Environmental Product Content Specification of Suppliers and Outsourced Manufacturers – None Required http://supplier.intel.com/ehs/environmental.htm International ISO11469 - Plastic parts weighing >25gm are intended to be marked with per ISO11469. Recycling Markings – Fiberboard (FB) and Cardboard (CB) are marked with international recycling marks. Applied to outer bulk packaging and single package. Japan >PC/ABS< Japan Recycling Applied to Retail Packaging Only for Boxed Boards 9.4 Other Markings Compliance Description Compliance Reference Compliance Reference Marking Example Country of Origin Logistic Requirements Applied to products to indicate where product was made. Made in XXXX 82 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off. When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. Mixed processor steppings is supported. However, the stepping of one processor can not greater then one stepping back of the other. Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board. On the back edge of the server board are four diagnostic LEDs which display a sequence of red, green, or amber POST codes during the boot process. If the server board hangs during POST, the LEDs will display the last POST event run before the hang. Only Fully Buffered DIMMs (FBD) are supported on this server board. For a list of supported memory for this server board, see the Intel® Server Board S5000PAL / S5000XAL Tested Memory List. For a list of Intel supported operating systems, add-in cards, and peripherals for this server board, see the Intel® Server Board S5000PAL / S5000XAL Tested Hardware and OS List. Only Dual-Core Intel® Xeon® processors 5000 sequence, with system bus speeds of 667/1066/1333 MHz are supported on this server board. Previous generation Intel® Xeon® processors are not supported. For best performance, the number of DIMMs installed should be balanced across both memory branches. For example: a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight DIMM configuration will perform better then a six DIMM configuration. There are no population rules for installing a single low profile add-in card in the 2U LP riser card; a single add in card can be installed in either PCI Express* slot. While each slot can accommodate a x8 card, each slot will only support x4 bus speeds. For the 2U PCI-X* (passive) riser card, add-in cards should be installed starting with the top slot first, followed by the middle, and then the bottom. Any add-in card populated in the bottom PCI slot will cause the bus to operate at 66MHz. Each PCI slot on the 2U PCI-X* (active) riser card operates on an independent PCI bus. Therefore, using an add-in card that operates below 133MHz will not affect the bus speed of the other PCI slots. The IDE connector on this server board is NOT a standard 40-pin IDE connector. Instead, this connector has an additional 4 power pins over and above the standard 40 I/O pins. The design intent of this connector is to provide support for a slim-line optical drive only. Removing AC Power before performing the CMOS clear operation will cause the system to automatically power up and immediately power down after the procedure is followed and AC power is re-applied. Should this occur, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power up system and proceed to the BIOS setup utility to reset desired settings. Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position (pins 2-3). The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default (disabled) position (pins 1-2) when the server is running normally. When performing a BIOS update procedure, the BIOS select jumper must be set to its default position (pins 2-3). When AC power is applied to the server, a 25-30 second delay is necessary to initialize the BMC. During this initialization period, the Power Button functionality is disabled. Revision 1.7 Intel order number: D31979-010 83 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: BMC Sensor Tables This appendix lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 1.5, for sensor and event/reading-type table information. Sensor Type The Sensor Type references the values enumerated in the Sensor Type Codes table in the IPMI specification. It provides the context in which to interpret the sensor, e.g., the physical entity or characteristic that is represented by this sensor. Event / Reading Type The Event/Reading Type references values from the Event/Reading Type Code Ranges and Generic Event/Reading Type Codes tables in the IPMI specification. Note that digital sensors are a specific type of discrete sensors, which have only two states. Event Offset/Triggers Event Thresholds are ‘supported event generating thresholds’ for threshold types of sensors. o o [u,l][nr,c,nc]: upper non-recoverable, upper critical, upper non-critical, lower non-recoverable, lower critical, lower non-critical uc, lc: upper critical, lower critical Event Triggers are ‘supported event generating offsets’ for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor specific response. Assertion / De-assertion Enables Assertion and de-assertion indicators reveal the type of events the sensor can generate: o As: Assertions o De: De-assertion Readable Value / Offsets o Readable Value indicates the type of value returned for threshold and other non-discrete type sensors. o Readable Offsets indicate the offsets for discrete sensors that are readable via the Get Sensor Reading command. Unless otherwise indicated, all event triggers are readable, i.e., Readable Offsets consists of the reading type offsets that do not generate events. Event Data This is the data that is included in an event message generated by the associated sensor. For threshold-based sensors, the following abbreviations are used: o R: Reading value o T: Threshold value 84 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Rearm Sensors - The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor: A: Auto-rearm M: Manual rearm Default Hysteresis - Hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative Hysteresis). Criticality - Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED. Standby - Some sensors operate on standby power. These sensors may be accessed and / or generate events when the main (system) power is off, but AC power is present. Revision 1.7 Intel order number: D31979-010 85 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Table 43. BMC Sensors Sensor Name Sensor Number System Applicability All Sensor Type Event / Reading Type Sensor Specific 6Fh Event Offset Triggers Power down Power cycle A/C lost Soft power control failure Power unit failure Predictive failure Power Unit 02h Redundancy Chassisspecific Power Unit 09h Generic 0Bh Redundancy regained Non-red: suff res from redund Redundancy lost Redundancy degraded Non-red: suff from insuff Non-red: insufficient Redun degrade from full Redun degrade from nonredundant OK Critical OK Degraded Non-Critical OK As – Trig Offset A X Critical Criticality Assert / De-assert As Readable Value / Offsets – Event Data Rearm Standby Power Unit 01h Status Power Unit 09h OK Trig Offset A X 86 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name Watchdog Sensor Number 03h System Applicability All Sensor Type Watchdog 2 23h Event / Reading Type Sensor Specific 6Fh Event Offset Triggers Timer expired, status only Hard reset Power down Power cycle Timer interrupt Criticality Assert / De-assert As OK Readable Value / Offsets – Event Data Rearm Standby Trig Offset A X Platform Security Violation 04h All Platform Security Violation Attempt 06h Sensor Specific 6Fh Secure mode violation attempt Out-of-band access password violation OK As – Trig Offset A X Physical Security 05h Physical Chassis Security Intrusion is chassis- 05h specific All Critical Interrupt 13h Sensor Specific 6Fh Sensor Specific 6Fh Chassis intrusion LAN leash lost 1 OK As and De – Trig Offset A X FP Diag Interrupt (NMI) 07h Front panel NMI OK / diagnostic interrupt Bus uncorrectable error As – Trig Offset A – System Event Log 09h All Event Logging Disabled 10h Sensor Specific 6Fh Log area reset / cleared OK As – Trig Offset A X Session Audit 0Ah All 2Ah Session Audit Sensor Specific 6Fh 00h – Session activation 01h – Session deactivation OK As – As defined by IPMI A X Revision 1.7 Intel order number: D31979-010 87 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name System Event ('System Event') BB +1.2V Vtt BB+1.9V NIC Core BB +1.5V AUX BB +1.5V BB +1.8V BB +3.3V BB +3.3V STB BB +1.5V ESB BB +5V BB +1.2V NIC BB +12V AUX BB 0.9V BB Vbat Sensor Number 0Bh System Applicability All Event / Reading Type System Event Sensor Specific 12h 6Fh Sensor Type Event Offset Triggers 00 – System reconfigured 04 – PEF action [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] 01h – Limit exceeded Criticality Assert / De-assert As OK Readable Value / Offsets – Event Data Rearm Standby Trig Offset A X 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Eh All All All All All All All All All All All All All Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Digital Discrete 05h Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Critical As and De As and De As and De As and De As and De As and De As and De As and De As and De As and De As and De As and De As and De Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog – R, T R, T R, T R, T R, T R, T R, T R, T R, T R, T R, T R, T R, T A A A A A A A A A A A A A – X – – – – X X – – – – X 88 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name BB Temp Front Panel Temp Fan 1A Fan 2A Fan 3A Fan 4A Fan 5A Tach Fan (not used on this server) Fan 1B Fan 2B Fan 3B Fan 4B Fan 5B Fan 1 Present Sensor Number 30h 32h System Applicability All All Sensor Type Temperature 01h Temperature 01h Event / Reading Type Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Event Offset Triggers [u,l] [c,nc] [u,l] [c,nc] Criticality Assert / De-assert As and De As and De Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined Readable Value / Offsets Analog Analog Event Data Rearm Standby R, T R, T A A X X 50h 51h 52h 53h 54h 55h Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h [l] [c,nc] [l] [c,nc] [l] [c,nc] [l] [c,nc] [l] [c,nc] [l] [c,nc] As and De As and De As and De As and De As and De As and De Analog Analog Analog Analog Analog Analog R, T R, T R, T R, T R, T R, T M M M M M M – – – – – – 56h 57h 58h 59h 5Ah 60h Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Generic 08h [l] [c,nc] [l] [c,nc] [l] [c,nc] [l] [c,nc] [l] [c,nc] Device present Threshold defined Threshold defined Threshold defined Threshold defined Threshold defined OK As and De As and De As and De As and De As and De As and De Analog Analog Analog Analog Analog – R, T R, T R, T R, T R, T T M M M M M A – – – – – – Revision 1.7 Intel order number: D31979-010 89 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name Fan 2 Present Fan 3 Present Fan 4 Present Fan 5 Present Fan 6 Present Fan 7 Present Fan 8 Present Fan 9 Present Fan 10 Present Fan Redundancy Sensor Number 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Fh System Applicability Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Chassisspecific Sensor Type Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Event / Reading Type Generic 08h Generic 08h Generic 08h Generic 08h Generic 08h Generic 08h Generic 08h Generic 08h Generic 08h Generic 0Bh Event Offset Triggers Device present Device present Device present Device present Device present Device present Device present Device present Device present Redundancy regained Redundancy lost Redundancy degraded Criticality Assert / De-assert As and De As and De As and De As and De As and De As and De As and De As and De As and De As OK OK OK OK OK OK OK OK OK OK Degraded Readable Value / Offsets – – – – – – – – – – Event Data Rearm Standby T T T T T T T T T Trig Offset A A A A A A A A A A – – – – – – – – – X Non-red: suff OK res from redund Non-red: suff from insuff Non-red: insufficient Critical 90 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name Sensor Number System Applicability Sensor Type Event / Reading Type Event Offset Triggers Redun degrade from full Redun degrade from nonredundant Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby OK Power Supply Status 1 70h Chassisspecific Power Supply Sensor Specific 08h 6Fh Presence Failure Predictive fail A/C lost Configuration error OK Critical Non-Critical Critical Non-Critical OK Critical Non-Critical Critical Non-Critical Threshold defined As and De – Trig Offset A X Power Supply Status 2 71h Chassisspecific Power Supply Sensor Specific 08h 6Fh Presence Failure Predictive fail A/C lost Configuration error As and De – Trig Offset A X Power Nozzle Power Supply 1 Power Nozzle Power Supply 2 Power Gauge V1 rail (+12v) Power Supply 1 78h Chassisspecific Current 03h Threshold 01h [u] [c,nc] As and De Analog R, T A – 79h Chassisspecific Current 03h Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A – 7Ah Chassisspecific Current 03h Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A – Revision 1.7 Intel order number: D31979-010 91 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name Power Gauge V1 rail (+12v) Power Supply 2 Power Gauge (aggregate power) Power Supply 1 Sensor Number 7Bh System Applicability Chassisspecific Sensor Type Current 03h Event / Reading Type Threshold 01h Event Offset Triggers [u] [c,nc] Criticality Assert / De-assert As and De Threshold defined Readable Value / Offsets Analog Event Data Rearm Standby R, T A – 7Ch Chassisspecific Other Units 0Bh Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A – 7Dh Power Gauge (aggregate power) Power Supply 2 System ACPI Power State 82h Chassisspecific Other Units 0Bh Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A – All System ACPI Power State 22h Sensor Specific 6Fh S0 / G0 S1 S3 S4 S5 / G2 G3 mechanical off OK As – Trig Offset A X Button 84h All Button 14h Sensor Specific 6Fh Digital Discrete 03h Power button Reset button 01h – State asserted OK As – Trig Offset A X SMI Timeout 85h All SMI Timeout F3h Critical As and De – Trig Offset A – 92 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name Sensor Failure Sensor Number 86h System Applicability All Sensor Type Sensor Failure F6h Event / Reading Type OEM Sensor Specific 73h Event Offset Triggers I2C device not found I C device error detected I C bus timeout 2 2 Criticality Assert / De-assert As OK Readable Value / Offsets – Event Data Rearm Standby Trig Offset A X NMI Signal 87h State SMI Signal 88h State Proc 1 Status 90h All OEM C0h Digital Discrete 03h Digital Discrete 03h Sensor Specific 6Fh 01h – State asserted 01h – State asserted IERR Thermal trip Config error Presence Disabled OK – 01h – – – All OEM C0h OK – 01h – – – All Processor 07h Critical Non-rec Critical OK Degraded Critical Non-rec Critical OK Degraded Threshold defined Threshold defined OK Degraded As and De – Trig Offset M X Proc 2 Status 91h All Processor 07h Sensor Specific 6Fh IERR Thermal trip Config error Presence Disabled As and De – Trig Offset M X Proc 1 Temp Proc 2 Temp 98h 9Ah All All Critical Interrupt 13F Temperature 01h Temperature 01h Sensor Specific 6Fh Threshold 01h Threshold 01h PCIe Link0 [u,l] [c,nc] [u,l] [c,nc] Bus correctable error Bus uncorrectable error As and De As and De As Analog Analog – R, T R, T See the BIOS EPS A A A – – – PCIe Link0 A0h Revision 1.7 Intel order number: D31979-010 93 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name Sensor Number PCIe Link1 A1h System Applicability Critical Interrupt 13F Sensor Type Sensor Specific 6Fh Event / Reading Type PCIe Link1 Event Offset Triggers Bus correctable error Bus uncorrectable error Criticality Assert / De-assert As OK Degraded Readable Value / Offsets – Event Data Rearm Standby See the BIOS EPS A – PCIe Link2 A2h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link2 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link3 A3h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link3 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link4 A4h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link4 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link5 A5h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link5 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link6 A6h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link6 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link7 A7h Critical Interrupt Sensor Specific PCIe Link7 Bus correctable error OK As – See the BIOS EPS A – 94 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name Sensor Number System Applicability 13F Sensor Type Event / Reading Type Event Offset Triggers Bus uncorrectable error Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby 6Fh Degraded PCIe Link8 A8h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link8 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link9 A9h Critical Interrupt 13F Sensor Specific 6Fh PCIe Link9 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link10 AAh Critical Interrupt 13F Sensor Specific 6Fh PCIe Link10 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link11 ABh Critical Interrupt 13F Sensor Specific 6Fh PCIe Link11 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link12 ACh Critical Interrupt 13F Sensor Specific 6Fh PCIe Link12 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – PCIe Link13 ADh Critical Interrupt 13F Sensor Specific 6Fh PCIe Link13 Bus correctable error Bus uncorrectable error OK Degraded As – See the BIOS EPS A – Revision 1.7 Intel order number: D31979-010 95 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name Proc 1 Thermal Control Proc 2 Thermal Control Proc 1 VRD Over Temp Proc 2 VRD Over Temp Sensor Number C0h System Applicability All Sensor Type Temperature 01h Event / Reading Type Threshold 01h Threshold 01h Digital Discrete 05h Digital Discrete 05h Threshold 01h Threshold 01h Digital Discrete 05h Digital Discrete 05h Generic 03h Sensor Specific 6Fh Event Offset Triggers [u] [c,nc] Criticality Assert / De-assert As and De Threshold defined Threshold defined Non-Critical Readable Value / Offsets Analog Event Data Rearm Standby Trig Offset M – C1h All Temperature 01h [u] [c,nc] As and De Analog Trig Offset M – C8h All Temperature 01h 01h – Limit exceeded 01h – Limit exceeded [u,l] [c,nc] [u,l] [c,nc] 01h – Limit exceeded 01h – Limit exceeded 01h –- State asserted Fault status asserted Device installed Disabled Sparing As and De – Trig Offset M – C9h All Temperature 01h Non-Critical As and De – Trig Offset M – Proc 1 Vcc D0h Proc 2 Vcc D1h Proc 1 Vcc D2h Out-ofRange Proc 2 Vcc Outof-Range CPU Population Error DIMM A1 D8h D3h All All All Voltage 02h Voltage 02h Voltage 02h Threshold defined Threshold defined Non-Critical As and De As and De As and De Analog Analog Discrete R, T R, T R, T A A A – – – All Voltage 02h Non-Critical As and De Discrete R, T A – All Processor 07h Critical As and De – R, T A – E0h All Slot Connector 21h Degraded OK Degraded OK Degraded As – Trig Offset A – DIMM A2 E1h All Slot Connector Sensor Specific Fault status asserted As – Trig Offset A – 96 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name Sensor Number System Applicability Sensor Type 21h Event / Reading Type 6Fh Event Offset Triggers Device installed Disabled Sparing Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded OK Degraded As – Trig Offset A – As – Trig Offset A – As – Trig Offset A – As – Trig Offset A – As – Trig Offset A – As – Trig Offset A – DIMM B1 E2h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Device installed Disabled Sparing DIMM B2 E3h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Device installed Disabled Sparing DIMM C1 E4h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Device installed Disabled Sparing DIMM C2 E5h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Device installed Disabled Sparing DIMM D1 E6h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Device installed Disabled Sparing DIMM D2 E7h All Slot Connector Sensor Specific Fault status asserted Revision 1.7 Intel order number: D31979-010 97 Appendix B: Sensor Tables Intel® Server Board S5000PAL / S5000XAL TPS Sensor Name Sensor Number System Applicability Sensor Type 21h Event / Reading Type 6Fh Event Offset Triggers Device installed Disabled Sparing Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby OK Degraded OK OK As – Trig Offset A – Memory A Error ECh All Memory 0Ch Sensor Specific 6Fh Correctable ECC Uncorrectable ECC Correctable ECC Uncorrectable ECC Correctable ECC Uncorrectable ECC Correctable ECC Uncorrectable ECC Entity present Memory B Error EDh Systemspecific Memory 0Ch Sensor Specific 6Fh OK As – Trig Offset A – Memory C Error EEh Systemspecific Memory 0Ch Sensor Specific 6Fh OK As – Trig Offset A – Memory D Error EFh Systemspecific Memory 0Ch Sensor Specific 6Fh OK As – Trig Offset A – B0 DIMM Sparing Enabled B0 DIMM Sparing Redundancy F0h All Entity Presence 25h Memory 0Ch Sensor Specific 6Fh Discrete 0Bh OK As – Trig Offset A – F1h All Fully redundant OK As – Trig Offset A – Degraded Non-red: suff res from redund Non-red: suff res from insuff res Non-red: Insuff res Critical OK As – Trig Offset A – B1 DIMM Sparing Enabled F2h All Entity Presence 25h Sensor Specific 6Fh Entity present 98 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables Sensor Name B1 DIMM Sparing Redundancy Sensor Number F3h System Applicability All Sensor Type Memory 0Ch Event / Reading Type Discrete 0Bh Event Offset Triggers Fully redundant Criticality Assert / De-assert As OK Readable Value / Offsets – Event Data Rearm Standby Trig Offset A – Non-red: suff Degraded res from redund Non-red: suff res from insuff res Non-red: insuff res Critical OK As – Trig Offset A – B01 DIMM Mirroring Enabled B01 DIMM Mirroring Redundancy F4h All Entity Presence 25h Memory 0Ch Sensor Specific 6Fh Discrete 0Bh Entity present F5h All Fully redundant OK As – Trig Offset A – Non-red:suff res Degraded from redund Non-red:suff res from insuff res Non-red: insuff res Critical Note 1: Not supported except for ESB-2 embedded NICs Revision 1.7 Intel order number: D31979-010 99 Appendix C: POST Code Diagnostic LEDs Intel® Server Board S5000PAL / S5000XAL TPS Appendix C: POST Code Diagnostic LED Decoder During the system boot process, BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, BIOS will display the given POST code to the POST Code Diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the Diagnostic LEDs can be used to identify the last POST process to be executed. Each POST code will be represented by a combination of colors from the four LEDs. The LEDs are capable of displaying three colors: green, red, and amber. The POST codes are divided into two nibbles, an upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red LED and each bit in the lower nibble is represented by a green LED. If both bits are set in the upper and lower nibbles then both red and green LEDs are lit, resulting in an amber color. If both bits are clear, then the LED is off. In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: • red bits = 1010b = Ah green bits = 1100b = Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated to be ACh. Table 44: POST Progress Code LED Example 8h LEDs ACh Result Red 1 Amber MSB 1 Green 0 Green Red 1 4h Green 1 Red Red 0 2h Green 0 Off LSB Red 0 1h Green USB Port USB Port Diagnostic LEDs Back edge of baseboard MSB LSB Figure 28. Diagnostic LED Placement Diagram 100 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix C: POST Code Diagnostic LEDs Table 45. Diagnostic LED POST Code Decoder Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB Host Processor Checkpoint 0x10h 0x11h 0x12h 0x13h Chipset 0x21h Memory 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h 0x28h PCI Bus 0x50h 0x51h 0x52h 0x53h 0x54h 0x55h 0x56h 0x57h USB 0x58h 0x59h 0x5Ah 0x5Bh SMBUS 0x5Ch 0x5Dh Local Console 0x70h 0x71h 0x72h 0x78h 0x79h 0x7Ah 0x90h 0x91h OFF OFF OFF G G G R R R R R R R R OFF OFF R R A R R A OFF OFF R A R R A R R A Resetting the video controller (VGA) Disabling the video controller (VGA) Enabling the video controller (VGA) Resetting the console controller Disabling the console controller Enabling the console controller Resetting the keyboard Disabling the keyboard G G A A OFF OFF R A Resetting SMBUS Reserved for SMBUS G G G G R R R R OFF OFF G G R A R A Resetting USB bus Reserved for USB devices Resetting PATA / SATA bus and all devices Reserved for ATA OFF OFF OFF OFF OFF OFF OFF OFF R R R R A A A A OFF OFF G G OFF OFF G G R A R A R A R A Enumerating PCI busses Allocating resources to PCI busses Hot Plug PCI controller initialization Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus OFF OFF OFF OFF OFF OFF G OFF OFF G G G G OFF A A R R A A R OFF G OFF G OFF G OFF Reading configuration data from memory (SPD on DIMM) Detecting presence of memory Programming timing parameters in the memory controller Configuring memory parameters in the memory controller Optimizing memory controller settings Initializing memory, such as ECC init Testing memory OFF OFF R G Initializing a chipset component OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF G G R A R A Description Power-on initialization of the host processor (bootstrap processor) Host processor cache initialization (including AP) Starting application processor initialization SMM initialization ATA / ATAPI / SATA Remote Console Keyboard (PS2 or USB) Revision 1.7 Intel order number: D31979-010 101 Appendix C: POST Code Diagnostic LEDs Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB R OFF G R R R R A A A A R R R R A A A A R R R R R R R R A A A A A A A R R R R R R R OFF G G OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF G R R R R A A A A R R R R A A A R R R R A A A G OFF OFF OFF OFF G G R R A A R R A R OFF OFF G G OFF OFF G G OFF OFF G G OFF G G R A R A R R A A R A R A R A R A R A R A R R R A R A R A R A R A R A R R A OFF OFF G G OFF G OFF Intel® Server Board S5000PAL / S5000XAL TPS Description Checkpoint 0x92h 0x93h 0x94h 0x95h 0x98h 0x99h 0x9Ah 0x9Bh Fixed Media 0xB0h 0xB1h 0xB2h 0xB3h 0xB8h 0xB9h 0xBAh 0xBCh 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0XDA 0xDB 0xDC 0xDE 0xDF 0xE0h 0xE2h 0xE1h 0xE3h 0xE4h 0xE5h 0xE6h DXE Drivers Detecting the presence of the keyboard Enabling the keyboard Clearing keyboard input buffer Instructing keyboard controller to run Self Test (PS2 only) Resetting the mouse Detecting the mouse Detecting the presence of mouse Enabling the mouse Resetting fixed media device Disabling fixed media device Detecting presence of a fixed media device (IDE hard drive detection, etc.) Enabling / configuring a fixed media device Resetting removable media device Disabling removable media device Detecting presence of a removable media device (IDE CDROM detection, etc.) Enabling / configuring a removable media device Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Started dispatching early initialization modules (PEIM) Initial memory found, configured, and installed correctly Reserved for initialization module use (PEIM) Reserved for initialization module use (PEIM) Entered EFI driver execution phase (DXE) Started dispatching drivers Started connecting drivers Mouse (PS2 or USB) Removable Media Boot Device Selection Pre-EFI Initialization (PEI) Core Driver Execution Environment (DXE) Core 102 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB R A A G A A A A A R R A A A R R R A A A A R R R R R A A A R R R R A OFF G OFF OFF G R A R A R Appendix C: POST Code Diagnostic LEDs Description Checkpoint 0xE7h 0xE8h 0xE9h 0xEAh 0xEEh 0xEFh 0xF4h 0xF5h 0xF8h 0xF9h 0xFAh Waiting for user input Checking password Entering BIOS setup Flash Update Calling Int 19. One beep unless silent boot is enabled. Unrecoverable boot failure / S3 resume failure Entering Sleep state Exiting Sleep state Operating system has requested EFI to close boot services (ExitBootServices ( ) has been called) Operating system has switched to virtual address mode (SetVirtualAddressMap ( ) has been called) Operating system has requested the system to reset (ResetSystem () has been called) Crisis recovery has been initiated because of a user request Crisis recovery has been initiated by software (corrupt flash) Loading crisis recovery capsule Handing off control to the crisis recovery capsule Unable to complete crisis recovery. Runtime Phase / EFI Operating System Boot Pre-EFI Initialization Module (PEIM) / Recovery 0x30h 0x31h 0x34h 0x35h 0x3Fh OFF OFF OFF OFF G OFF OFF G G G R R R R A R A R A A Revision 1.7 Intel order number: D31979-010 103 Appendix D: POST Error Messages and Handling Intel® Server Board S5000PAL / S5000XAL TPS Appendix D: POST Error Messages and Handling Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs. The Response section in the following table is divided into two types: Pause: The message is displayed in the Error Manager screen, an error is logged to the SEL, and user input is required to continue. The user can take immediate corrective action or choose to continue booting. Halt: The message is displayed in the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system. Table 46. POST Error Messages and Handling Error Code 004C 0012 5220 5221 5223 0048 0141 0146 8110 8111 8120 8121 8130 8131 8160 8161 8190 8198 0192 0194 0195 0197 8300 8306 8305 84F2 84F3 84F4 Error Message Keyboard / interface error CMOS date / time not set Configuration cleared by jumper Passwords cleared by jumper Configuration default loaded Password check failed PCI resource conflict Insufficient memory to shadow PCI ROM Processor 01 internal error (IERR) on last boot Processor 02 internal error (IERR) on last boot Processor 01 thermal trip error on last boot Processor 02 thermal trip error on last boot Processor 01 disabled Processor 02 disabled Processor 01 unable to apply BIOS update Processor 02 unable to apply BIOS update Watchdog timer failed on last boot Operating system boot watchdog timer expired on last boot L3 cache size mismatch CPUID, processor family are different Front side bus mismatch Processor speeds mismatched Baseboard management controller failed self-test Front panel controller locked Hot swap controller failed Baseboard management controller failed to respond Baseboard management controller in update mode Sensor data record empty Response Pause Pause Pause Pause Pause Halt Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Halt Halt Pause Pause Pause Pause Pause Pause Pause Pause 104 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Error Code 84FF 8500 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C 852D 852E 852F 8540 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 858A 858B 858C 858D 858E 858F 8600 8601 8602 8603 Appendix D: POST Error Messages and Handling Response Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Error Message System event log full Memory Component could not be configured in the selected RAS mode. DIMM_A1 failed Self Test (BIST). DIMM_A2 failed Self Test (BIST). DIMM_A3 failed Self Test (BIST). DIMM_A4 failed Self Test (BIST). DIMM_B1 failed Self Test (BIST). DIMM_B2 failed Self Test (BIST). DIMM_B3 failed Self Test (BIST). DIMM_B4 failed Self Test (BIST). DIMM_C1 failed Self Test (BIST). DIMM_C2 failed Self Test (BIST). DIMM_C3 failed Self Test (BIST). DIMM_C4 failed Self Test (BIST). DIMM_D1 failed Self Test (BIST). DIMM_D2 failed Self Test (BIST). DIMM_D3 failed Self Test (BIST). DIMM_D4 failed Self Test (BIST). Memory Component lost redundancy during the last boot. DIMM_A1 Correctable ECC error encountered. DIMM_A2 Correctable ECC error encountered. DIMM_A3 Correctable ECC error encountered. DIMM_A4 Correctable ECC error encountered. DIMM_B1 Correctable ECC error encountered. DIMM_B2 Correctable ECC error encountered. DIMM_B3 Correctable ECC error encountered. DIMM_B4 Correctable ECC error encountered. DIMM_C1 Correctable ECC error encountered. DIMM_C2 Correctable ECC error encountered. DIMM_C3 Correctable ECC error encountered. DIMM_C4 Correctable ECC error encountered. DIMM_D1 Correctable ECC error encountered. DIMM_D2 Correctable ECC error encountered. DIMM_D3 Correctable ECC error encountered. DIMM_D4 Correctable ECC error encountered. Primary and secondary BIOS IDs do not match. Override jumper is set to force boot from lower alternate BIOS bank of flash ROM WatchDog timer expired (secondary BIOS may be bad!) Secondary BIOS checksum fail Revision 1.7 Intel order number: D31979-010 105 Appendix D: POST Error Messages and Handling Intel® Server Board S5000PAL / S5000XAL TPS POST Error Beep Codes The following table lists POST error beep codes. Prior to system Video initialization, BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user visible code on POST Progress LEDs. Table 47. POST Error Beep Codes Beeps 3 6 Error Message Memory error BIOS rolling back error POST Progress Code Description System halted because a fatal error related to the memory was detected. The system has detected a corrupted BIOS in the flash part, and is rolling back to the last good BIOS. The BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously. Codes that are common across all Intel® Server Boards and systems that use the Intel® S5000 chipset are listed in Table 48. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit. Table 48. BMC Beep Codes Code 1-5-2-1 1-5-2-2 1-5-2-3 1-5-2-4 1-5-4-2 1-5-4-3 1-5-4-4 Reason for Beep CPU: Empty slot / population error – Processor slot 1 is not populated. CPU: No processors (terminators only) CPU: Configuration error (e.g., VID mismatch) CPU: Configuration error (e.g., BSEL mismatch) Power fault: DC power unexpectedly lost (power good dropout) Chipset control failure Power control fault Associated Sensors CPU Population Error N/A N/A N/A Power Unit – power unit failure offset N/A Power Unit – soft power control failure offset Supported? Yes No No No Yes No Yes 106 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix E: Supported Intel® Server Chassis Appendix E: Supported Intel® Server Chassis The Intel® Server Board S5000PAL / S5000XAL is supported in the following Intel high density rack mount server chassis: • • • Intel® Server Chassis SR1500 Intel® Server Chassis SR1550 Intel® Server Chassis SR2500 This section provides a high level descriptive overview of each chassis. For more detail, please reference the appropriate Technical Product Specification (TPS) available for each. F E D C B A G H I P O K L N A M TP02154 J A B C D E F G H Rack handles Backplane – Passive SAS/SATA or Active SAS/SAS RAID Air baffle Power supply fans 600 Watt Power supply Intel® Server Board S5000PAL / S5000XAL PCI card bracket (full height) – PCI-X* or PCIe* PCI add-in riser assembly I J K L M N O P PCI card bracket (low profile) – PCIe* Processor air duct Fan module Bridge board Control panel (standard control panel shown) Hard drive bays (drives not included) Slimline drive bay (drive not included) Front bezel (optional) Figure 29. 1U – Intel® Server Chassis SR1500 Overview Revision 1.7 Intel order number: D31979-010 107 Appendix E: Supported Intel® Server Chassis Intel® Server Board S5000PAL / S5000XAL TPS A B C D E F G H I J K Rack Handles SAS/SATA Backplane SAS RAID Battery Pack (Optional) Power Supply Air Duct Power Distribution Board 1+1 650 Watt Power Supply Modules Intel® Server Board S5000PAL / S5000XAL Bridge Board Intel RMM Module (Optional) Intel RMM NIC(Optional) IO Module (Optional) ® ® L M N O P Q R S T U V Riser Card Assembly System Memory Processor and Heat Sink Processor Air Duct System Fan Bank Mid-plane Board (Active - SAS/SAS RAID shown) Front Bezel (Optional; Standard Control Panel shown) ® Standard Control Panel or Intel Local Control Panel (Optional) Mini Control Panel Bay – required option to support eight hard drives Slimline Optical Drive Bay Up to Eight 2.5” Hard Drive Bays Figure 30. 1U – Intel® Server Chassis SR1550 Overview 108 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Appendix E: Supported Intel® Server Chassis E F D C B A N H M I L K J A G TP02094 A. B. C. D. E. F. G. Rack Handles SAS/SATA Backplane Air Baffles Power Distribution Module 1+1 750 Watt Power Supply Modules Riser Card Assembly System Memory Mid-pane – Passive SAS/SATA or Active SAS/SAS RAID (Not shown) H. I. J. K. L. M. N. CPU Air Duct System Fan Assembly Standard Control Panel Flex Bay – 6 HDD or Tape (Optional) Five SATA/SAS Hard Drive Bays Slim-Line Optical Drive Bay Front Bezel (Optional) th Figure 31. 2U – Intel® Server Chassis SR2500 Overview Revision 1.7 Intel order number: D31979-010 109 Glossary Intel® Server Board S5000PAL / S5000XAL TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following. Term ACPI AP APIC ASIC ASMI BIOS BIST BMC Bridge BSP byte CBC CEK CHAP CMOS DPC EEPROM EHCI EMP EPS ESB-2 FBD FMB FRB FRU FSB GB GPIO GTL HSC Hz I2C IA IBF ICH ICMB IERR IFB INTR IP IPMB Definition Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Application Specific Integrated Circuit Advanced Server Management Interface Basic Input/Output System Built-In Self Test Baseboard Management Controller Circuitry connecting one computer bus to another, allowing an agent on one to access the other Bootstrap Processor 8-bit quantity. Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis. Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. Direct Platform Control Electrically Erasable Programmable Read-Only Memory Enhanced Host Controller Interface Emergency Management Port External Product Specification Enterprise South Bridge 2 Fully Buffered DIMM Flexible Mother Board Fault Resilient Booting Field Replaceable Unit Front Side Bus 1024MB General Purpose I/O Gunning Transceiver Logic Hot-Swap Controller Hertz (1 cycle/second) Inter-Integrated Circuit Bus Intel Architecture Input Buffer I/O Controller Hub Intelligent Chassis Management Bus Internal Error I/O and Firmware Bridge Interrupt Internet Protocol Intelligent Platform Management Bus ® 110 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Term IPMI IR ITP KB KCS LAN LCD LED LPC LUN MAC MB MCH MD2 MD5 ms MTTR Mux NIC NMI OBF OEM Ohm PEF PEP PIA PLD PMI POST PSMI PWM RAM RASUM RISC ROM RTC SDR SECC SEEPROM SEL SIO SMI SMM SMS SNMP TBD TIM UART Definition Intelligent Platform Management Interface Infrared In-Target Probe 1024 bytes Keyboard Controller Style Local Area Network Liquid Crystal Display Light Emitting Diode Low Pin Count Logical Unit Number Media Access Control 1024KB Memory Controller Hub Message Digest 2 – Hashing Algorithm Message Digest 5 – Hashing Algorithm – Higher Security milliseconds Memory Type Range Register Multiplexor Network Interface Controller Nonmaskable Interrupt Output Buffer Original Equipment Manufacturer Unit of electrical resistance Platform Event Filtering Platform Event Paging Platform Information Area (This feature configures the firmware for the platform hardware) Programmable Logic Device Platform Management Interrupt Power-On Self Test Power Supply Management Interface Pulse-Width Modulation Random Access Memory Reliability, Availability, Serviceability, Usability, and Manageability Reduced Instruction Set Computing Read Only Memory Real-Time Clock (Component of ICH peripheral chip on the server board) Sensor Data Record Single Edge Connector Cartridge Serial Electrically Erasable Programmable Read-Only Memory System Event Log Server Input/Output Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) Server Management Mode Server Management Software Simple Network Management Protocol To Be Determined Thermal Interface Material Universal Asynchronous Receiver/Transmitter Glossary Revision 1.7 Intel order number: D31979-010 111 Glossary Term UDP UHCI UTC VID VRD Word ZIF Intel® Server Board S5000PAL / S5000XAL TPS Definition User Datagram Protocol Universal Host Controller Interface Universal time coordinate Voltage Identification Voltage Regulator Down 16-bit quantity Zero Insertion Force 112 Revision 1.7 Intel order number: D31979-010 Intel® Server Board S5000PAL / S5000XAL TPS Reference Documents Reference Documents See the following documents for additional information: Intel® S5000 Series Chipsets Server Board Family Datasheet Intel® S5000 Server Board Family BIOS Core External Product Specification (Yellow Cover) Intel® S5000 Server Board Family BMC Core External Product Specification (Yellow Cover) Intel® 5000P Memory Controller Hub External Design Specification (Yellow Cover) Intel® Enterprise South Bridge-2 (ESB-2) External Design Specification (Yellow Cover) TEB 2.11 – Thin Electronics Bay (1U/2U Rack Optimized) EPS 1U Rev. 2.93 – Entry Level Power Supply – 1U non-redundant – Intel® S5000 Server Board Family ERP 2U – Rev. 2.31 – Entry Redundant Power Supply 2U form factor – Intel® S5000 Server Board Family Note: Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel representative. Revision 1.7 Intel order number: D31979-010 113