5962D0823001VXC

Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver ISL7457SRH The ISL7457SRH is a radiation hardened, SEE hardened, high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A typical peak drive capability and a nominal on-resistance of just 3.5Ω. The ISL7457SRH is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to level-shifting and clock-driving applications. Each output of the ISL7457SRH can be switched to either the high (VH) or low (VL) supply pins, depending on the related input pin. The inputs are compatible with both 3.3V and 5V CMOS logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. The ISL7457SRH also features very fast rise and fall times which are typically matched to within 1ns. The propagation delay is also matched between rising and falling edges to typically within 1.5ns. The ISL7457SRH is available in a 16 lead ceramic flatpack package and specified for operation over the full -55°C to +125°C ambient temperature range. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-08230. A “hot-link” is provided on our website for downloading. ISL7457SRH Features • Electrically Screened to SMD 5962-08230 • QML Qualified per MIL-PRF-38535 Requirements • Full Mil-temp Range Operation . TA = -55°C to +125°C • Radiation Hardness - TID [50-300 rad(Si)/s] . . . . . . . .10krad(Si) min • SEE Hardness - LET (SEL and SEB Immunity)40MeV/mg/cm2 min - LET [SET = ΔVOUT < 15V, Δt < 500ns] . . . . . . . 40MeV/mg/cm2 • 4 Channels • Clocking Speeds up to 40MHz • 11ns/12ns Typical tR/tF with 1nF Load (15V bias) • 1ns Typical Rise and Fall Time Match (15V bias) • 1.5ns Typical Prop Delay Match (15V bias) • Low Quiescent Current - < 1mA Typical • Fast Output Enable Function - 12ns Typical (15V bias) • Wide Output Voltage Range - 0V ≤ VL ≤ 8V - 2.5V ≤ VH ≤ 16.5V • 2A Typical Peak Drive Current (15V Bias) • 3.5Ω Typical ON-Resistance (15V bias) • Input Level Shifters • 3.3V/5V CMOS Compatible Inputs Applications • CCD Drivers, Clock/line Drivers, Level-Shifters Pin Configuration ISL7457SRH (16 LD FLATPACK) TOP VIEW INA OE INB VL GND NC INC IND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VS+ OUTA OUTB NC VH OUTC OUTD VS- May 16, 2011 FN6874.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL7457SRH Ordering Information ORDERING NUMBER 5962D0823001QXC 5962D0823001VXC 5962D0823001V9A ISL7457SRHF/PROTO ISL7457SRHX/SAMPLE PART NUMBER ISL7457SRHQF ISL7457SRHVF ISL7457SRHVX ISL7457SRHF/PROTO ISL7457SRHX/SAMPLE TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE 16 Ld Flatpack 16 Ld Flatpack Die 16 Ld Flatpack Die K16.A PKG. DWG. # K16.A K16.A 2 FN6874.1 May 16, 2011 ISL7457SRH Electrical Specifications PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROH ROL ILEAK+ ILEAKON Resistance VH to OUTx ON Resistance VL to OUTx Positive Output Leakage Current Negative Output Leakage Current INx = VS+, IOUTx = -100mA INx = 0V, IOUTx = +100mA INx = VS+, OE = 0V, OUTx = VS+ INx = VS+, OE = 0V, OUTx = VS8 6 5 -5 Ω Ω nA nA Logic “1” Input Voltage Logic “1” Input Current Logic “0” Input Voltage Logic “0” Input Current Input Capacitance Input Resistance INx = 0V INx = VS+ 1.3 10 1.23 -5 5.7 500 V nA V nA pF MΩ Typical values reflect VS+ = VH = 5V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION POWER SUPPLY IS+ ISIH IL VS+ Supply Current VS- Supply Current VH Supply Current VL Supply Current INx = 0V and VS+ INx = 0V and VS+ INx = 0V and VS+ INx = 0V and VS+ 0.2 -0.2 0.1 0.1 mA mA µA µA SWITCHING CHARACTERISTICS tR tF tRFΔ tD+ tDtDD tENABLE tDISABLE Rise Time Fall Time tR, tF Mismatch Turn-On Delay Time Turn-Off Delay Time tD+, tD- Mismatch Enable Delay Time Disable Delay Time INx = 0V to 4.5V step, CL = 1nF INx = 4.5V to 0V step, CL = 1nF CL = 1nF INx = 0V to 4.5V step, CL = 1nF INx = 4.5V to 0V step, CL = 1nF CL = 1nF INx = VS+, OE = 0V to 4.5V step, RL = 1kΩ INx = VS+, OE = 4.5V to 0V step, RL = 1kΩ 23 20 3 20 22 2 21 46 ns ns ns ns ns ns ns ns 3 FN6874.1 May 16, 2011 ISL7457SRH Electrical Specifications PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROH ROL ILEAK+ ILEAKON Resistance VH to OUTx ON Resistance VL to OUTx Positive Output Leakage Current Negative Output Leakage Current INx = VS+, IOUTx = -100mA INx = 0V, IOUTx = +100mA INx = VS+, OE = 0V, OUTx = VS+ INx = VS+, OE = 0V, OUTx = VS3.5 3 15 -15 Ω Ω nA nA Logic “1” Input Voltage Logic “1” Input Current Logic “0” Input Voltage Logic “0” Input Current Input Capacitance Input Resistance INx = 0V INx = VS+ 1.63 10 1.4 -5 5.7 1.5 V nA V nA pF GΩ Typical values reflect VS+ = VH = 15V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION POWER SUPPLY IS+ ISIH IL VS+ Supply Current VS- Supply Current VH Supply Current VL Supply Current INx = 0V and VS+ INx = 0V and VS+ INx = 0V and VS+ INx = 0V and VS+ 0.8 -0.8 0.1 0.1 mA mA µA µA SWITCHING CHARACTERISTICS tR tF tRFΔ tD+ tDtDD tENABLE tDISABLE Rise Time Fall Time tR, tF Mismatch Turn-On Delay Time Turn-Off Delay Time tD+, tD- Mismatch Enable Delay Time Disable Delay Time INx = 0V to 5V step, CL = 1nF INx = 5V to 0V step, CL = 1nF CL = 1nF INx = 0V to 5V step, CL = 1nF INx = 5V to 0V step, CL = 1nF CL = 1nF INx = VS+, OE = 0V to 5V step, RL = 1kΩ INx = VS+, OE = 5V to 0V step, RL = 1kΩ 11 12 1 11.5 13 1.5 12 27 ns ns ns ns ns ns ns ns 4 FN6874.1 May 16, 2011 ISL7457SRH Typical Performance Curves (Pre-rad) 1.8 TA = +25°C HIGH LIMIT = 2.4V SUPPLY CURRENT (mA) 2.0 1.6 1.2 0.8 0.4 0 5 TA = +25°C ALL INPUTS = 0V INPUT VOLTAGE (V) 1.6 HYSTERESIS 1.4 1.2 LOW LIMIT = 0.8V 7.0 10 12 15 ALL INPUTS = VS+ 1.0 5.0 7 10 12 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 25 RISE/FALL TIME (ns) 9 “ON” RESISTANCE (Ω) 8 7 6 5 4 3 2 5 IOUT = 100mA TA = +25°C 20 tR VH TO OUT 15 tF VL TO OUT 10 CL = 1nF TA = +25°C 5 5 7 10 12 15 7 10 12 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 3. “ON”-RESISTANCE vs SUPPLY VOLTAGE 16 RISE/FALL TIME (ns) 14 12 10 tR 8 6. -50 FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE 25 PROPAGATION DELAY TIME (ns) CL = 1nF VS+ = 15V CL = 1nF TA = +25°C 20 tF 15 tD+ 10 tD- -25 0 25 50 75 100 125 5.0 5 7 10 12 15 TEMPERATURE (°C) SUPPLY VOLTAGE (V) FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 5 FN6874.1 May 16, 2011 ISL7457SRH Typical Performance Curves (Pre-rad) (Continued) PROPAGATION DELAY TIME (ns) 18 16 14 12 10 8 6 -50 tD+ CL = 1nF VS+ = 15V RISE/FALL TIME (ns) 140 VS+ = 15V 120 TA = +25°C 100 80 60 40 20 0 100 470 1k 2.2k tF tR tD- -25 0 25 50 75 100 125 4.7k 10k TEMPERATURE (°C) LOAD CAPACITANCE (pF) FIGURE 7. PROPAGATION DELAY TIME vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE OPERATING FREQUENCY (MHz) 12 SUPPLY CURRENT (mA) 10 8 6 4 2 VS+ = VH = 10V VS- = VL = 0V f = 100kHz TA = +25°C 50 40 30 20 10 0 0 VS+ = 15V . TJ = +125°C . . . TJ = +150°C 200 400 . . 600 800 . . . 1000 0 100 1k LOAD CAPACITANCE (pF) 10k LOAD CAPACITANCE (pF) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs LOAD CAPACITANCE FIGURE 10. OPERATING FREQUENCY vs LOAD CAPACITANCE DERATING CURVES 6 FN6874.1 May 16, 2011 ISL7457SRH TABLE 1. OPERATING VOLTAGE RANGE PIN VS+ to VSVS- to GND VH VL VH to VL VL to VSMIN 4.5V 0V VS- + 2.5V VS0V 0V MAX 16.5V 0V VS+ VS+ 16.5V 8V INPUT Timing Diagram 5V 2.5V 0 OUTPUT 90% 10% tD+ tR tDtF Standard Test Configuration VS+ 10kΩ INA OE INB VL 4.7µF 1 2 3 4 0.1µF 5 6 INC IND 7 8 12 11 1nF 10 9 1nF OUTD OUTC 16 1nF 15 14 1nF 13 0.1µF VH 4.7µF OUTB 0.1µF 4.7µF VS+ OUTA 7 FN6874.1 May 16, 2011 ISL7457SRH Pin Descriptions 16 LD FLATPACK 1 NAME INA FUNCTION Input Channel A VS+ EQUIVALENT CIRCUIT VS+ INx VS- VS- CIRCUIT 1 2 3 4 5 6, 13 7 8 9 10 OE INB VL GND NC INC IND VSOUTD Output enable Input Channel B Low voltage input pin Input logic ground No connection Input Channel C Input Channel D Negative supply voltage Output Channel D (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 1) VH VS+ OUTx VSVSVL CIRCUIT 2 11 12 14 15 16 OUTC VH OUTB OUTA VS+ Output Channel C High voltage input pin Output Channel B Output Channel A Positive supply voltage (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 2) Block Diagram OE VS+ VH INx GND LEVEL SHIFTER 3-STATE CONTROL OUTx VSVL 8 FN6874.1 May 16, 2011 ISL7457SRH Application Information Product Description The ISL7457SRH is a high performance, high speed quad CMOS driver. Each channel of the ISL7457SRH consists of a single P-channel high side driver and a single N-Channel low side driver. These 3.5Ω devices will pull the output (OUTx) to either the high or low voltage, on VH and VL respectively, depending on the input logic signal (INx). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the ISL7457SRH. When this pin is pulled low, it will put all outputs in a high impedance state. Power dissipation may be calculated as shown in Equation 1: 4 PD = ( VS × IS ) + 2 ∑ ( CINT × VS × f ) + ( CL × VOUT × f ) 1 2 (EQ. 1) where: PD is the power dissipated in the device. VS is the total power supply to the ISL7457SRH (from VS+ to VS-). IS is the quiescent supply current. CINT is the internal load capacitance (80pF max). f is the operating frequency. CL is the load capacitance. VOUT is the swing on the output (VH - VL). Supply Voltage Range and Input Compatibility The ISL7457SRH is designed to operate on nominal 5V to 15V supplies with ±10% tolerance. Table 1 on page 7 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. The ISL7457SRH does not contain a true analog switch and therefore VL should always be less than VH. All input pins are compatible with both 3.3V and 5V CMOS signals. Junction Temperature Calculation Once the power dissipation for the application is determined, the maximum junction temperature can be calculated as shown in Equation 2: T JMAX = T SMAX + ( Θ JC + Θ CS ) × P D (EQ. 2) PCB Layout Guidelines 1. A ground plane must be used, preferably located on layer #2 of the PCB. 2. Connect the GND and VS- pins directly to the ground plane. 2. The VS+, VH and VL pins should be bypassed directly to the ground plane using a low-ESR, 4.7µF solid tantalum capacitor in parallel with a 0.1µF ceramic capacitor. Locate all bypass capacitors as close as possible to the respective pins of the IC. 3. Keep all input and output connections to the IC as short as possible. 4. For high frequency operation above 1MHz, consider use of controlled impedance traces terminated into 50Ω on all inputs and outputs. where: TJMAX is the maximum operating junction temperature (+150°C). TSMAX is the maximum operating sink temperature of the PCB. θJC is the thermal resistance, junction-to-case, of the package. θCS is the thermal resistance, case-to-sink, of the PCB. PD is the power dissipation calculated in Equation 1. PCB Thermal Management To minimize the case-to-sink thermal resistance, it is recommended that multiple vias be placed on the top layer of the PCB directly underneath the IC. The vias should be connected to the ground plane, which functions as a heatsink. A gap filler material (i.e. a Sil-Pad or thermally conductive epoxy) may be used to insure good thermal contact between the bottom of the IC and the vias. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the ISL7457SRH drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (+150°C). 9 FN6874.1 May 16, 2011 ISL7457SRH Die Characteristics DIE DIMENSIONS: 2390µm x 2445µm (94.1 mils x 96.3 mils) Thickness:13.0 mils ±0.5 mil INTERFACE MATERIALS Glassivation Type: PSG and Silicon Nitride Thickness: 0.5µm ± 0.05µm to 0.7 µm ±0.05µm Top Metallization Type: AlCuSi (1%/0.5%) Thickness: 1.0 µm ±0.1µm Substrate: Type: Silicon Isolation: Junction Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: VsADDITIONAL INFORMATION Worst Case Current Density: < 2 x 105 A/cm2 (See Figure 10) Transistor Count: 1142 Metallization Mask Layout ISL7457SRH INA VS+ OE OUTA INB OUTB VL VH GND OUTC DELAY OUTD INC IND VS- 10 FN6874.1 May 16, 2011 ISL7457SRH Layout Characteristics Step and Repeat: 2390µm x 2445µm The DELAY pad is not bonded. TABLE 1. LAYOUT X-Y COORDINATES PAD NAME IND VSOUTD OUTC VH X (µm) 675 995 2118 2118 2118 2118 OUTB OUTA VS+ INA OE INB VL 2118 2118 1015 608 213 213 213 213 GND DELAY INC 213 213 213 Y (µm) 190 190 490 795 1039 1211 1554 1861 2140 2140 1993 1673 1331 1159 864 585 213 140 140 140 140 140 140 1 0 1 122 122 140 140 140 140 140 133 133 140 140 140 140 345 1 1 1 1 1 1 2 DX (µm) 140 140 122 122 122 DY (µm) 140 140 133 133 345 PROBES PER PAD 1 1 1 1 2 For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6874.1 May 16, 2011 ISL7457SRH Ceramic Metal Seal Flatpack Packages (Flatpack) A K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B) 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE SYMBOL INCHES MIN 0.045 0.015 0.015 0.004 0.004 0.245 0.130 0.030 0.008 0.250 0.026 0.005 16 MAX 0.115 0.022 0.019 0.009 0.006 0.440 0.285 0.315 0.015 0.370 0.045 0.0015 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.22 3.30 0.76 0.20 6.35 0.66 0.13 16 MAX 2.92 0.56 0.48 0.23 0.15 11.18 7.24 8.00 0.38 9.40 1.14 0.04 NOTE S 3 3 7 2 8 6 Rev. 1 2-20-95 e PIN NO. 1 ID AREA A -A- -B- D A b b1 c c1 D S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS E E1 E2 E3 e k L Q S1 M N 0.050 BSC 1.27 BSC BASE METAL b1 M M (b) SECTION A-A (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH 12 FN6874.1 May 16, 2011