5962D9569301VXC

® HS-0546RH, HS-0547RH Data Sheet March 13, 2006 FN3544.4 Radiation Hardened Single 16/Differential 8 Channel CMOS Analog Multiplexers with Active Overvoltage Protection The HS-0546RH and HS-0547RH are radiation hardened analog multiplexers with Active Overvoltage Protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70V peak-to-peak levels with ±15V supplies and digital inputs will sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur: each input presents 1kΩ of resistance under this condition. These features make the HS-0546RH and HS-0547RH ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. Both devices are fabricated with 44V dielectrically isolated CMOS technology. The HS-0546 is a 16 channel device and the HS-0547 is an 8 channel differential version. If input overvoltage protection is not needed, the HS-0506 and HS-0507 multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95693. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com Features • Electrically Screened to SMD # 5962-95693 • QML Qualified per MIL-PRF-38535 Requirements • Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si) • No Latch-Up • No Channel Interaction During Overvoltage • Guaranteed rON Matching • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . .44V • Break-Before-Make Switch • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs Applications • Data Acquisition Systems • Control Systems • Telemetry Ordering Information ORDERING NUMBER INTERNAL MKT. NUMBER PART MARKING Q-5962D9569301V9A TEMP. RANGE (°C) 25 -55 to 125 25 5962D9569301V9A HS0-0546RH-Q 5962D9569301VXC HS1B-0546RH-Q Q-5962D9569301VXC 5962D9569302V9A HS0-0547RH-Q Q-5962D9569302V9A 5962D9569302VXC HS1B-0547RH-Q Q-5962D9569302VXC -55 to 125 Pinouts HS-0546RH GDIP1-T28 (CERDIP) OR CDIP2-T28 (SBDIP) TOP VIEW VSUPPLY 1 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 VREF 13 ADDRESS A3 14 28 OUT 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 HS-0547RH GDIP1-T28 (CERDIP) OR CDIP2-T28 (SBDIP) TOP VIEW +VSUPPLY 1 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 VREF 13 NC 14 28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-0546RH, HS-0547RH Functional Diagrams HS-0546RH HS-0547RH IN1 1K IN2 1K DECODER/ DRIVER OUT IN1A 1K IN8A 1K IN1B 1K IN8B DECODER/ DRIVER OUT A OUT B 1K IN16 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION ††††† † DIGITAL INPUT PROTECTION ††† † VREF A0 A1 A2 A3 EN VREF A0 A1 A2 EN HS-0546RH TRUTH TABLE A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H “ON” CHANNEL NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 L L H H H H H H L L H H A2 X L L A1 X L L HS-0547RH TRUTH TABLE A0 X L H L H L H L H EN L H H H H H H H H “ON” CHANNEL PAIR NONE 1 2 3 4 5 6 7 8 2 FN3544.4 March 13, 2006 HS-0546RH, HS-0547RH Switching Waveforms VAH = 4.0 ADDRESS DRIVE (VA) 50% +10V -8V tA 0V OUTPUT A -10V VA A3 A2 A1 A0 ±10V IN 1 IN 2 THRU IN 15 IN 16 ± 10V VA INPUT 2V/DIV. CH1 ON EN GND VAH OUT VOUT 10K OUTPUT A 5V/DIV. CH16 ON 200ns/DIV FIGURE 1. ACCESS TIME VAH = 4.0 0V ADDRESS DRIVE (VA) VA OUTPUT EN VAH 1K tOPEN 100ns/DIV GND A3 A2 A1 A0 50% 50% IN 16 OUT VOUT OUTPUT 1V/DIV. +5V IN 1 IN 2 THRU IN 15 VA INPUT 2V/DIV. FIGURE 2. BREAK-BEFORE-MAKE DELAY (tOPEN) VAH = 4.0 50% 0V OUTPUT 90% 90% tON(EN) tOFF (EN) 100ns/DIV VA EN GND OUT 1K CH1 OFF OUTPUT 4V/DIV. A3 A2 A1 A0 IN 1 IN 2 THRU IN 16 +10V CH1 ON FIGURE 3. ENABLE DELAY tON(EN), tOFF(EN) 3 FN3544.4 March 13, 2006 HS-0546RH, HS-0547RH Schematic Diagrams V+ R9 Q1 Q4 D3 LEVEL SHIFTER V+ P P P P P P P P P LEVEL SHIFTED ADDRESS TO DECODE LEVEL SHIFTED ADDRESS TO DECODE R10 TTL REFERENCE CIRCUIT P OVERVOLTAGE PROTECTION V+ ADD IN. D2 R1 200Ω D1 VN N R2 R5 R3 N R4 R6 N N N N N R8 N N R7 V- FIGURE 4. ADDRESS INPUT BUFFER AND LEVEL SHIFTER FROM DECODE +V P P P P P P OVERVOLTAGE V+ P PROTECTION N N A0 OR A0 A1 OR A1 A2 OR A2 N N N R11 IN 1K D6 D7 Q5 D4 D5 N N Q6 OUT N N V ENABLE VTO N-CHANNEL DEVICE OF THE SWITCH PAIR TO P-CHANNEL DEVICE OF THE SWITCH PAIR FROM DECODE P FIGURE 5. ADDRESS DECODER FIGURE 6. MULTIPLEX SWITCH 4 FN3544.4 March 13, 2006 HS-0546RH, HS-0547RH Burn-In/Life Test Circuits V1 1 C1 D1 R1 2 3 4 5 6 7 8 9 10 11 12 13 F3 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 F4 F0 F1 F2 V1 D2 C2 C1 D1 R1 R2 V2 V2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D2 C2 R2 V3 DYNAMIC AND LIFE TEST NOTES: 1. The Dynamic Test Circuit is utilized for all life testing. 2. V1 = +15V minimum, +16V maximum. 3. V2 = -15V maximum, -16V minimum. 4. R1, R2 = 10kΩ, ±5%, 1/4 or 1/2W (per socket). 5. C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row). 6. D1, D2 = 1N4002 or equivalent (per board). 7. F0 = 100kHz, 10%; F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 40% - 60% duty cycle; VIL = 0.8V maximum; VIH = 4.0V minimum. NOTES: STATIC 8. V1 = +5V minimum, +6V maximum. 9. V2 = +15V minimum, +16V maximum. 10. V3 = -15V maximum, -16V minimum. 11. R1, R2 = 10kΩ, ± 5%, 1/4 or 1/2W (per socket). 12. C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row). 13. D1, D2 = 1N4002 or equivalent (per board). Irradiation Circuit +15V 10kΩ NC +1V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 -15V 10kΩ +5V 5 FN3544.4 March 13, 2006 HS-0546RH, HS-0547RH Die Characteristics DIE DIMENSIONS: 83.9 mils x 159 mils x 19 mils INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kÅ ±0.7kÅ Top Metallization: Type: Al Thickness: 16kÅ ±2kÅ Substrate: CMOS, DI ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: 1.4 x 105 A/cm2 Transistor Count: HS-0546 - 485 HS-0547 - 485 Metallization Mask Layout HS-0546RH EN A0 A1 A2 A3 VREF GND EN A0 HS-0547RH A1 A2 NC VREF GND IN 1 IN 2 IN 9 IN 10 IN 1A IN 2A IN 1B IN 2B IN 3 IN 4 IN 11 IN 12 IN 3A IN 4A IN 3B IN 4B IN 5 IN 6 IN 13 IN 14 IN 5A IN 6A IN 5B IN 6B IN 7 IN 8 IN 15 IN 16 IN 7A IN 8A IN 7B IN 8B -V OUT +V NC -V OUT A +V OUT B All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN3544.4 March 13, 2006