5962F9563003QYC

Rad-Hard 16 Channel CMOS Analog Multiplexer with High-Z Analog Input Protection HS-1840ARH, HS-1840BRH The HS-1840ARH, HS-1840BRH are radiation hardened, monolithic 16 channel multiplexers constructed with the Intersil Rad-Hard Silicon Gate, bonded wafer, Dielectric Isolation process. They are designed to provide a high input impedance to the analog source if device power fails (open), or the analog signal voltage inadvertently exceeds the supply by up to ±35V, regardless of whether the device is powered on or off. Excellent for use in redundant applications, since the secondary device can be operated in a standby unpowered mode affording no additional power drain. More significantly, a very high impedance exists between the active and inactive devices preventing any interaction. One of sixteen channel selections is controlled by a 4-bit binary address plus an Enable-Inhibit input which conveniently controls the ON/OFF operation of several multiplexers in a system. All inputs have electrostatic discharge protection. The HS-1840ARH, HS-1840BRH are processed and screened in full compliance with MIL-PRF-38535 and QML standards. The devices are available in a 28 Ld SBDIP and a 28 Ld Ceramic Flatpack. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95630. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm HS-1840ARH, HS-1840BRH Features • Electrically Screened to SMD # 5962-95630 • QML Qualified per MIL-PRF-38535 Requirements • Pin-to-Pin for Intersil’s HS-1840RH and HS-1840/883S • Improved Radiation Performance - Gamma Dose (γ) 3x105RAD(Si) • Improved rDS(ON) Linearity • Improved Access Time 1.5µs (Max) Over Temp and Post Rad • High Analog Input Impedance 500MΩ During Power Loss (Open) • ±35V Input Overvoltage Protection (Power On or Off) • Dielectrically Isolated Device Islands • Excellent in Hi-Rel Redundant Systems • Break-Before-Make Switching • No Latch-Up Ordering Information ORDERING NUMBER 5962F9563002QXC 5962F9563002QYC 5962F9563002VXC 5962F9563002VYC HS1-1840ARH/PROTO HS9-1840ARH/PROTO HS1-1840ARH-T 5962F9563002V9A 5962F9563003QXC INTERNAL MKT. NUMBER HS1-1840ARH-8 HS9-1840ARH-8 HS1-1840ARH-Q HS9-1840ARH-Q HS1-1840ARH/PROTO HS9-1840ARH/PROTO HS1-1840ARH-T HS0-1840ARH-Q HS1-1840BRH-8 TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 Q 5962F95 63003QXC 28 Ld SBDIP PART MARKING NO. Q 5962F95 63002QXC Q 5962F95 63002QYC Q 5962F95 63002VXC Q 5962F95 63002VYC HS1- 1840ARH /PROTO HS9- 1840ARH /PROTO Q 5962R95 63002TXC PACKAGE 28 Ld SBDIP 28 Ld Flatpack 28 Ld SBDIP 28 Ld Flatpack 28 Ld SBDIP 28 Ld Flatpack 28 Ld SBDIP September 14, 2010 FN4355.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-1840ARH, HS-1840BRH Ordering Information (Continued) ORDERING NUMBER 5962F9563003QYC 5962F9563003VXC 5962F9563003VYC HS1-1840BRH/PROTO HS9-1840BRH/PROTO 5962F9563003V9A INTERNAL MKT. NUMBER HS9-1840BRH-8 HS1-1840BRH-Q HS9-1840BRH-Q HS1-1840BRH/PROTO HS9-1840BRH/PROTO HS0-1840BRH-Q TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PART MARKING NO. Q 5962F95 63003QYC Q 5962F95 63003VXC Q 5962F95 63003VYC HS1- 1840BRH /PROTO HS9- 1840BRH /PROTO PACKAGE 28 Ld Flatpack 28 Ld SBDIP 28 Ld Flatpack 28 Ld SBDIP 28 Ld Flatpack Pin Configurations HS1-1840ARH, HS1-1840BRH (28 LD SBDIP) CDIP2-T28 TOP VIEW +VS 1 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 (+5VS) VREF 13 ADDR A3 14 28 OUT 27 -VS 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDR A0 16 ADDR A1 15 ADDR A2 +VS NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5VS) VREF ADDR A3 HS9-1840ARH, HS9-1840BRH (28 LD FLATPACK) CDFP3-F28 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OUT -VS IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 2 FN4355.3 September 14, 2010 HS-1840ARH, HS-1840BRH Functional Diagram VDD A0 IN1 1 A1 DIGITAL ADDRESS A2 MAINSWITCH 1 A3 OUT IN16 EN 16 MAINSWITCH 16 ADDRESS INPUT BUFFER AND LEVEL SHIFTER DECODERS MULTIPLEX SWITCHES NOTE: MAINSWITCH INXX: SWITCH ON, BODY TIED TO SOURCE SWITCH OFF, BODY TIED TO VCC-0.7V TABLE 1. TRUTH TABLE A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN H L L L L L L L L L L L L L L L L “ON” CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3 FN4355.3 September 14, 2010 HS-1840ARH, HS-1840BRH Burn-In/Life Test Circuits R +VS R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 F3 F5 F1 F2 GND VR R -VS +VS R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R -VS R GND F4 R NOTE: VS+ = +15.5V ±0.5V, VS- = -15.5V ±0.5V. R = 1kΩ ±5%. C1 = C2 = 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM. D1 = D2 = 1N4002, 1 EACH PER BOARD, MINIMUM. INPUT SIGNALS: SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%. F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16. NOTE: R = 1kΩ ±5%, 1/4W. C1 = C2 = 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM. VS+ = 15.5V ±0.5V, VS- = -15.5V ±0.5V, VR = 15.5 ±0.5V FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT NOTES: 1. The above test circuits are utilized for all package types. 2. The Dynamic Test Circuit is utilized for all life testing. FIGURE 2. .STATIC BURN-IN TEST CIRCUIT Irradiation Circuit HS-1840ARH, HS-1840BRH +15V NC NC +1V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +5V 28 27 26 25 24 23 22 21 20 19 18 17 16 15 -15V 1kΩ NOTE: 3. All irradiation testing is performed in the 28 lead CERDIP package. 4 FN4355.3 September 14, 2010 HS-1840ARH, HS-1840BRH Die Characteristics DIE DIMENSIONS: (2820µmx4080µm x 483µm ±25.4μm) 111 milsx161 milsx19 mils ±1 mil INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorus Silicon Glass) Thickness: 8.0kÅ ±1kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ±2kÅ Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: Modified SEM Transistor Count: 407 Process: Radiation Hardened Silicon Gate, Bonded Wafer, Dielectric Isolation Metallization Mask Layout HS-1840ARH, HS-1840BRH IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN8 ENABLE A0 -V A1 OUT A2 +V A3 VREF IN16 GND IN15 IN14 IN13 IN12 IN11 IN10 IN9 5 FN4355.3 September 14, 2010 HS-1840ARH, HS-1840BRH Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C) 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 5/18/94 E eA e eA/2 c D E e eA eA/2 L Q S1 S2 0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038 ccc M C A - B S D S aaa M C A - B S D S NOTES: 4. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 5. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 6. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 7. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 8. Dimension Q shall be measured from the seating plane to the base plane. 9. Measure dimension S1 at all four corners. 10. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 11. N is the maximum number of terminal positions. 12. Braze fillets shall be concave. 13. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 14. Controlling dimension: INCH. α aaa bbb ccc M N For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN4355.3 September 14, 2010 HS-1840ARH, HS-1840BRH Ceramic Metal Seal Flatpack Packages (Flatpack) A K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B) 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.460 0.180 0.030 MAX 0.115 0.022 0.019 0.009 0.006 0.740 0.520 0.550 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 11.68 4.57 0.76 1.27 BSC 0.20 6.35 0.66 0.00 28 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 18.80 13.21 13.97 NOTES 3 3 7 2 8 6 Rev. 0 5/18/94 e PIN NO. 1 ID AREA A -A- -B- D A b S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS b1 c c1 D E E1 E2 E3 e k L 0.050 BSC 0.008 0.250 0.026 0.00 28 0.015 0.370 0.045 0.0015 BASE METAL b1 M M (b) SECTION A-A (c) Q S1 M N NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 7 FN4355.3 September 14, 2010