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5962F9568901VEC

5962F9568901VEC

  • 厂商:

    INTERSIL(Intersil)

  • 封装:

  • 描述:

    5962F9568901VEC - Radiation Hardened Quad Differential Line Receiver - Intersil Corporation

  • 数据手册
  • 价格&库存
5962F9568901VEC 数据手册
® HS-26C32RH Data Sheet August 1, 2008 FN3402.4 Radiation Hardened Quad Differential Line Receiver The Intersil HS-26C32RH is a differential line receiver designed for digital data transmission over balanced lines and meets the requirements of EIA Standard RS-422. Radiation hardened CMOS processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. The HS-26C32RH has an input sensitivity typically of 200mV over the common mode input voltage range of ±7V. The receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic “1” when the inputs are open. Enable and Disable functions are common to all four receivers. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the “Ordering Information” table must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95689. A “hot-link” is provided on our homepage for downloading .www.intersil.com/military/ Features • Electrically Screened to SMD # 5962-95689 • QML Qualified per MIL-PRF-38535 Requirements • 1.2 Micron Radiation Hardened CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) • Latch-up Free • EIA RS-422 Compatible Inputs • CMOS Compatible Outputs • Input Fail Safe Circuitry • High Impedance Inputs when Disabled or Powered Down • Low Power Dissipation 138mW Standby (Max) • Single 5V Supply • Full -55°C to +125°C Military Temperature Range Applications • Line Receiver for MIL-STD-1553 Serial Data Bus Logic Diagram ENABLE ENABLE DIN DIN CIN CIN BIN BIN AIN AIN + - + - + - + - DOUT COUT BOUT AOUT Ordering Information ORDERING NUMBER 5962F9568901QEC 5962F9568901QXC 5962F9568901V9A 5962F9568901VEC 5962F9568901VXC HS1-26C32RH/PROTO HS9-26C32RH/PROTO INTERNAL MKT. NUMBER HS1-26C32RH-8 HS9-26C32RH-8 HS0-26C32RH-Q HS1-26C32RH-Q HS9-26C32RH-Q HS1-26C32RH/PROTO HS9-26C32RH/PROTO Q 5962F95 68901VEC Q 5962F95 68901VXC HS1- 26C32RH /PROTO HS9- 26C32RH /PROTO PART MARKING Q 5962F95 68901QEC Q 5962F95 68901QXC TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 16 Ld SBDIP D16.3 PACKAGE 16 Ld SBDIP PKG. DWG. # D16.3 16 Ld FLATPACK K16.A 16 Ld FLATPACK K16.A 16 Ld SBDIP D16.3 16 Ld FLATPACK K16.A 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-26C32RH Pinouts HS1-26C32RH (16 LD SBDIP) MIL-STD-1835: CDIP2-T16 TOP VIEW AIN 1 AIN 2 AOUT 3 ENABLE 4 COUT 5 CIN 6 CIN 7 GND 8 16 VDD 15 BIN 14 BIN 13 BOUT 12 ENABLE 11 DOUT 10 DIN 9 DIN AIN AIN AOUT ENABLE COUT CIN CIN GND HS9-26C32RH (16 LD FLATPACK) MIL-STD-1835: CDFP4-F16 TOP VIEW 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD BIN BIN BOUT ENABLE DOUT DIN DIN Propagation Delay Timing Diagram Propagation Delay Load Circuit DUT TEST POINT -VIN INPUT +VIN = 0V tPLH VOH VS = 50% VOL OUTPUT tPHL 0V +2.5V CL RL -2.5V CL = 50pF RL = 1000Ω Three-State Low Timing Diagram VIH VS VSS tPZL VOZ VT VOL OUTPUT VW tPLZ INPUT Three-State High Timing Diagrams VIH VS VSS tPZH VOH VT VOZ OUTPUT VW tPHZ INPUT 2 FN3402.4 August 1, 2008 HS-26C32RH TABLE 1. THREE-STATE LOW VOLTAGE LEVELS PARAMETER VDD VIH VS VT VW GND HS-26C32RH 4.50 4.50 2.25 50 VOL + 0.5 0 UNITS V V V % V V TABLE 2. THREE-STATE HIGH VOLTAGE LEVELS PARAMETER VDD VIH VS VT VW GND HS-26C32RH 4.50 4.50 2.25 50 VOH - 0.5 0 UNITS V V V % V V Three-State Low Load Circuit VDD Three-State High Load Circuit DUT TEST POINT RL DUT CL TEST POINT CL RL CL = 50pF RL = 1000Ω CL = 50pF RL = 1000Ω All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN3402.4 August 1, 2008 HS-26C32RH Die Characteristics DIE DIMENSIONS: 84 mils x 130 mils (2140µm x 3290µm) INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 10kÅ ± 1kÅ Top Metallization: M1: Mo/Tiw Thickness: 5800Å M2: Al/Si/Cu Thickness: 5800Å Worst Case Current Density:
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