5962R0922501V9A

Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs ISL70001SRH The ISL70001SRH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145°C. The ISL70001SRH utilizes peak current-mode control with integrated compensation and switches at a fixed frequency of 1MHz. Two ISL70001SRH devices can be synchronized 180° out-of-phase to reduce input RMS ripple current. These attributes reduce the number and size of external components required, while providing excellent output transient response. The internal synchronous power switches are optimized for high efficiency and good thermal performance. The chip features a comparator type enable input that provides flexibility. It can be used for simple digital on/off control or, alternately, can provide undervoltage lockout capability by using two external resistors to precisely sense the level of an external supply voltage. A power-good signal indicates when the output voltage is within ±11% typical of the nominal output voltage. Regulator start-up is controlled by an analog soft-start circuit, which can be adjusted from approximately 2ms to 200ms by using an external capacitor. The ISL70001SRH incorporates fault protection for the regulator. The protection circuits include input undervoltage, output undervoltage, and output overcurrent. High integration makes the ISL70001SRH an ideal choice to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the Ordering Information table on page 2 must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-09225. This link is also available on the ISL70001SRH device information page on the Intersil web site. Features • Electrically Screened to DSCC SMD 5962-09225 • QML Qualified per MIL-PRF-38535 Requirements • Full Mil-Temp Range Operation (TA = -55°C to +125°C) • Radiation Hardness - Total Dose [50-300rad(Si)/s] . . . . . . . . . . .100krad(Si) min • SEE Hardness - SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min - SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2 max - SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min • High Efficiency > 90% • Fixed 1MHz Operating Frequency • Operates from 3V to 5.5V Supply • ±1% Reference Voltage over Line, Load, Temperature and Radiation • Adjustable Output Voltage - Two External Resistors Set VOUT from 0.8V to ~85% of VIN • Excellent Dynamic Response • Bi-directional SYNC Pin Allows Two Devices to be Synchronized 180° Out-of-Phase • Device Enable with Comparator Type Input • Power-Good Output Voltage Monitor • Adjustable Analog Soft-Start • Input Undervoltage, Output Undervoltage and Output Overcurrent Protection • Starts Into Pre-Biased Load Applications • FPGA, CPLD, DSP, CPU Core or I/O Voltages • Low-Voltage, High-Density Distributed Power Systems May 23, 2011 FN6947.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL70001SRH Functional Block Diagram AVDD AGND DVDD DGND EN PORSEL POWER-ON RESET (POR) PVINx CURRENT SENSE SS SOFT START SLOPE COMPENSATION PWM CONTROL LOGIC FB EA GM GATE DRIVE LXx COMPENSATION PGNDx PGOOD UV POWER-GOOD REF PWM REFERENCE 0.6V TDI BIT TDO TRIM ZAP SYNC M/S Ordering Information ORDERING NUMBER 5962R0922501QXC 5962R0922501VXC 5962R0922501V9A ISL70001SRHF/PROTO ISL70001SRHX/SAMPLE ISL70001SRHEVAL1Z PART NUMBER (Note 2) ISL70001SRHQF (Note 1) ISL70001SRHVF (Note 1) ISL70001SRHVX ISL70001SRHF/PROTO (Note 1) ISL70001SRHX/SAMPLE Evaluation Board TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE 48 Ld CQFP (Pb-Free) 48 Ld CQFP (Pb-Free) Die 48 Ld CQFP (Pb-Free) Die NOTE: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SRH. For more information on MSL, please see Tech Brief TB363. 2 FN6947.1 May 23, 2011 ISL70001SRH Pin Configuration ISL70001SRH (48 LD CQFP) TOP VIEW PGND1 PGND1 PGND2 PGND2 PVIN1 PVIN1 PVIN2 PVIN2 PVIN3 SYNC LX1 LX2 6 M/S ZAP TDI TDO PGOOD SS DVDD DVDD DGND DGND AGND AGND 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PVIN3 LX3 PGND3 PGND3 PGND4 PGND4 LX4 PVIN4 PVIN4 PVIN5 PVIN5 LX5 31 18 19 20 21 22 23 24 25 26 27 28 29 30 PORSEL AVDD REF LX6 PGND6 PGND6 PGND5 Pin Descriptions PIN NUMBER 1, 2, 27, 28, 29, 30, 37, 38, 39, 40, 47, 48 3, 26, 31, 36, 41, 46 PIN NAME PGNDx DESCRIPTION These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins directly to the ground plane. These pins should also connect to the negative terminals of the input and output capacitors. Locate the input and output capacitors as close as possible to the IC. These pins are the outputs of the corresponding internal power blocks and should be connected to the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The Schottky diode should be located as close as possible to the IC. These pins are the power supply inputs to the corresponding internal power blocks. These pins must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock. Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 1MHz ±20%. This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND. This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND. This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND. This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND. This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE. LXx 4, 5, 24, 25, 32, 33, 34, 35, 42, 43, 44, 45 6 PVINx SYNC 7 8 9 10 11 M/S ZAP TDI TDO PGOOD 3 PGND5 PVIN6 PVIN6 FB EN FN6947.1 May 23, 2011 ISL70001SRH Pin Descriptions (Continued) PIN NUMBER 12 PIN NAME SS DESCRIPTION This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation 1: t SS = C SS ⋅ V REF ⁄ I SS (EQ. 1) Where: tSS = Soft-start output ramp time CSS = Soft-start capacitor VREF = Reference voltage (0.6V typical) ISS = Soft-start charging current (23µA typical) Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive. 13, 14 DVDD These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. These pins are the digital ground associated with the internal digital control circuitry. Connect these pins directly to the ground plane. These pins are the analog ground associated with the internal analog control circuitry. Connect these pins directly to the ground plane. This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available from this pin. This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2: V OUT = V REF ⋅ [ 1 + ( R T ⁄ R B ) ] (EQ. 2) 15, 16 17, 18 19 20 DGND AGND AVDD REF 21 FB Where: VOUT = Output voltage VREF = Reference voltage (0.6V typical) RT = Top divider resistor (Must be 1kΩ) RB = Bottom divider resistor The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to improve stability margins. 22 EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF ceramic capacitor to mitigate SEE. This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND. 23 PORSEL 4 FN6947.1 May 23, 2011 ISL70001SRH Typical Application Schematic PVIN1 5V PVIN2 100µF 1µF PVIN3 LX3 LX2 LX1 PVIN4 LX4 PVIN5 1µF PVIN6 LX5 1µH LX6 20V 3A FB ISL70001SRH 0V TO 5.5V 499Ω 470µF 1kΩ 4.7nF 1.8V 6A 1 DVDD 1µF DGND 1 AVDD 1µF AGND PGOOD 10nF VSENSE SYNC EN REF 220nF 10nF M/S PORSEL TDI TDO ZAP SS 100nF PGND4 PGND1 FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION 5 PGND2 PGND3 PGND5 PGND6 FN6947.1 May 23, 2011 ISL70001SRH Typical Application Schematic (Continued) PVIN1 3.3V PVIN2 100µF 1µF PVIN3 LX3 LX2 LX1 PVIN4 LX4 PVIN5 1µF PVIN6 LX5 1µH LX6 20V 3A FB ISL70001SRH 0V TO 5.5V 499Ω 470µF 1kΩ 4.7nF 1.8V 6A 1 DVDD 1µF DGND 1 AVDD 1µF AGND PGOOD 10nF VSENSE SYNC EN REF 220nF 10nF M/S PORSEL TDI TDO ZAP SS 100nF PGND4 PGND1 FIGURE 2. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION 6 PGND2 PGND3 PGND5 PGND6 FN6947.1 May 23, 2011 ISL70001SRH Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 3) PARAMETER TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS Electrical Specifications POWER SUPPLY Operating Supply Current VIN = 5.5V VIN = 3.6V Shutdown Supply Current VIN = 5.5V, EN = GND VIN = 3.6V, EN = GND 40 25 6 3 mA mA mA mA OUTPUT VOLTAGE Reference Voltage Tolerance Output Voltage Tolerance VOUT = 0.8V to 2.5V for VIN = 4.5V to 5.5V, VOUT = 0.8V to 2.5V for VIN = 3V to 3.6V, IOUT = 0A to 6A (Notes 5, 6) VIN = 5.5V, VFB = 0.6V 0.6 0 V % Feedback (FB) Input Leakage Current 0 µA PWM CONTROL LOGIC Oscillator Accuracy External Oscillator Range Minimum LXx On Time Minimum LXx Off Time Minimum LXx On Time Minimum LXx Off Time Master/Slave (M/S) Input Voltage VIN = 5.5V, Test Mode VIN = 5.5V, Test Mode VIN = 3V, Test Mode VIN = 3V, Test Mode Input High Threshold Input Low Threshold Master/Slave (M/S) Input Leakage Current VIN = 5.5V, M/S = GND or VIN Synchronization (SYNC) Input Voltage Input High Threshold, M/S = GND Input Low Threshold, M/S = GND Synchronization (SYNC) Input Leakage Current Synchronization (SYNC) Output Voltage VIN = 5.5V, M/S = GND, SYNC = GND or VIN VIN - VOH @ IOH = -1mA VOL@ IOL = 1mA 1 1 110 40 150 50 1.3 1.2 0 1.7 1.5 0 0.15 0.15 MHz MHz ns ns ns ns V V µA V V µA V V POWER BLOCKS Upper Device rDS(ON) Lower Device rDS(ON) LXx Output Leakage VIN = 3V, 0.4A Per Power Block, Test Mode (Note 6) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 6) VIN = 5.5V, EN = LXx = GND, Single LXx Output VIN = 5.5V, EN = GND, LXx = VIN, Single LXx Output Deadtime Efficiency Within a Single Power Block or between Power Blocks (Note 6) VIN = 3.3V, VOUT = 1.8V, IOUT = 3A VIN = 5V, VOUT = 2.5V, IOUT = 3A 215 146 0 0 5 90 92 mΩ mΩ µA µA ns % % 7 FN6947.1 May 23, 2011 ISL70001SRH Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 3) (Continued) PARAMETER TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS Electrical Specifications POWER-ON RESET POR Select (PORSEL) Input High Threshold Input Low Threshold POR Select (PORSEL) Input Leakage Current VIN POR VIN = 5.5V, PORSEL = GND or VIN Rising Threshold, PORSEL = VIN Hysteresis, PORSEL = VIN Rising Threshold, PORSEL = GND Hysteresis, PORSEL = GND Enable (EN) Input Voltage Enable (EN) Input Leakage Current Enable (EN) Sink Current Rising/Falling Threshold VIN = 5.5V, EN = GND or VIN EN = 0.3V 1.4 1.2 0 4.25 325 2.8 175 0.6 0 11 V V µA V mV V mV V µA µA SOFT-START Soft-Start Source Current Soft-Start Discharge ON-Resistance Soft-Start Discharge Time POWER-GOOD SIGNAL Rising Threshold Rising Hysteresis Falling Threshold Falling Hysteresis Power-Good Drive Power-Good Leakage VFB as a % of VREF, Test Mode VFB as a % of VREF, Test Mode VFB as a % of VREF, Test Mode VFB as a % of VREF, Test Mode VIN = 3V, PGOOD = 0.4V, EN = GND VIN = PGOOD = 5.5V 111 3.5 89 3.5 8.2 0.001 % % % % mA µA SS = GND 23 2.2 256 µA Ω Clock Cycles PROTECTION FEATURES Undervoltage Monitor Undervoltage Trip Threshold Undervoltage Recovery Threshold Overcurrent Monitor Overcurrent Trip Level Overcurrent or Short-Circuit Duty-Cycle NOTES: 3. Typical values shown are not guaranteed. Guaranteed min/max values are provided in the SMD. 4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications. 6. Limits established by characterization or analysis and are not production tested. 7. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by up to 3A. With all six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A) + 3A = 18A. The output inductor must support this peak current without saturating. LX4 Power Block, Test Mode, (Note 7) VIN = 3V, SS interval = 200µs, Test Mode, Fault interval divided by hiccup interval 1.9 0.8 A % VIN = 3V, VFB as a % of VREF, Test mode VIN = 3V, VFB as a % of VREF, Test mode 75 88 % % 8 FN6947.1 May 23, 2011 ISL70001SRH Functional Description The ISL70001SRH is a monolithic, fixed frequency, current-mode synchronous buck regulator with user configurable power blocks. Two ISL70001SRH devices can be used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs and CPUs. PVIN1 LX1 PGND1 PVIN2 LX2 PGND2 PVIN6 LX6 PGND6 PVIN5 LX5 PGND5 Output Voltage Selection VREF = 0.6V CREF = 220nF R T = 1k CC = 4.7nF ERROR AMPLIFIER - L LXx OUT COUT VOUT POWER BLOCK 1 POWER BLOCK 6 RT FB CC POWER BLOCK 2 POWER BLOCK 5 + VREF REF CREF RB PVIN3 LX3 PGND3 POWER BLOCK 3 POWER BLOCK 4 PVIN4 LX4 PGND4 FIGURE 4. OUTPUT VOLTAGE SELECTION FIGURE 3. POWER BLOCK DIAGRAM Power Blocks The power output stage of the regulator consists of six 1A capable power blocks that are paralleled to provide full 6A output current capability. The block diagram in Figure 3 shows a top level view of the individual power blocks. Each power block has a power supply input pin, PVINx, a phase output pin, LXx, and a power supply ground pin, PGNDx. All PVINx pins must be connected to a common power supply rail and all PGNDx pins must be connected to a common ground. LXx pins should be connected to the output inductor based on the required load current, but must include the LX4 pin. For example, if 3A of output current is needed, any three LXx pins can be connected to the inductor as long as one of them is the LX4 pin. The unused LXx pins should be left unconnected. Connecting all six LXx pins to the output inductor provides a maximum 6A of output current. See the “Typical Application Schematic” on page 5 for pin connection guidance. A scaled pilot device associated with each power block provides current feedback. Power block 4 contains the master pilot device and this is why it must be connected to the output inductor. The output voltage of the ISL70001SRH can be adjusted using an external resistor divider as shown in Figure 4. RT should be selected as 1kΩ to mitigate SEE. RT should be shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to improve loop stability margins. The REF pin should be bypassed to AGND with a 220nF ceramic capacitor to mitigate SEE. It should be noted that no current (sourcing or sinking) is available from the REF pin. RB can be determined from Equation 3. The designer can configure the output voltage from 0.8V to 85% of the input voltage. V REF R B = R T ⋅ ------------------------------V OUT – V REF (EQ. 3) Switching Frequency/Synchronization The ISL70001SRH features an internal oscillator running at a fixed frequency of 1MHz ±15% over recommended operating conditions. The regulator can be configured to run from the internal oscillator or can be synchronized to another ISL70001SRH or an SEE hardened external clock with a frequency range of 1MHz ±20%. To run the regulator from the internal oscillator, connect the M/S pin to DVDD. In this case, the output of the internal oscillator appears on the SYNC pin. To synchronize the regulator to the SYNC output of another ISL70001SRH regulator or to an SEE hardened external clock, connect the M/S pin to DGND. In this case, the SYNC pin is an input that accepts an external synchronizing signal. When synchronizing multiple devices, Slave regulators are synchronized 180° out-of-phase with respect to the SYNC output of a Master regulator or to an external clock. Main Control Loop During normal operation, the internal top power switch is turned on at the beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top power MOSFET. The bottom power MOSFET turns on and the inductor current ramps down for the rest of the cycle. The current comparator compares the output current at the ripple current peak to a current pilot. The error amplifier monitors VOUT and compares it with an internal reference voltage. The output voltage of the error amplifier drives a proportional current to the pilot. If VOUT is low, the current level of the pilot is increased and the trip off current level of the output is increased. The increased output current raises VOUT until it is in agreement with the reference voltage. Operation Initialization The ISL70001SRH initializes based on the state of the power-on reset (POR) monitor of the PVINx inputs and the state of the EN input. Successful initialization prompts a soft-start interval, and the regulator begins slowly ramping the output voltage. Once the commanded output voltage is within the proper window of operation, the power-good signal changes state from low to high, indicating proper regulator operation. Power-On Reset The POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at the PVINx pins. 9 FN6947.1 May 23, 2011 ISL70001SRH The POR threshold of the PVINx pins is controlled by the PORSEL pin. For a nominal 5V supply voltage, PORSEL should be connected to DVDD. For a nominal 3.3V supply voltage, PORSEL should be connected to DGND. For nominal supply voltages between 5V and 3.3V, PORSEL should be connected to DGND. The POR rising and falling thresholds are shown in the “Electrical Specifications” table on page 8. Hysteresis between the rising and falling thresholds ensures that small perturbations on PVINx seen during turn-on/turn-off of the regulator do not cause inadvertent turn-off/turn-on of the regulator. When the PVINx pins are below the POR rising threshold, the internal synchronous power MOSFET switches are turned off, and the LXx pins are held in a high-impedance state. To mitigate SEE, the EN pin should be bypassed to the AGND pin with a 10nF ceramic capacitor. VR = 0.6V IEN = 11µA CEN = 10nF VIN1 PVINx VIN2 ENABLE COMPARATOR + POR LOGIC VR EN CEN R2 R1 Enable and Disable After the POR input requirement is met, the ISL70001SRH remains in shutdown until the voltage at the enable input rises above the enable threshold. As shown in Figure 5, the enable circuit features a comparator type input. In addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. An internal IEN current sink with a typical value of 11µA is only active when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. As VIN2 rises, the enable level is not set exclusively by the resistor divider from VIN2. With the current sink active, the enable level is defined by Equation 4. R1 is the resistor from the EN pin to VIN2 and R2 is the resistor from the EN pin to the AGND pin. R1 V ENABLE = V R ⋅ 1 + ------- + I EN ⋅ R1 R2 (EQ. 4) IEN FIGURE 5. ENABLE CIRCUIT Soft-Start Once the POR and enable circuits are satisfied, the regulator initiates a soft-start. Figure 6 shows that the soft-start circuit clamps the error amplifier reference voltage to the voltage on an external soft-start capacitor connected to the SS pin. The soft-start capacitor is charged by an internal ISS current source. As the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. Once the voltage on the SS pin is equal to the internal reference voltage, the soft-start interval is complete. The controlled ramp of the output voltage reduces the inrush current during start-up. The soft-start output ramp interval is defined in Equation 6 and is adjustable from approximately 2ms to 200ms. The value of the soft-start capacitor, CSS, should range from 8.2nF to 8.2µF, inclusive. The peak inrush current can be computed from Equation 7. The soft-start interval should be long enough to ensure that the peak inrush current plus the peak output load current does not exceed the overcurrent trip level of the regulator. V REF t SS = C SS ⋅ -----------I SS Once the voltage at the EN pin reaches the enable threshold, the IEN current sink turns off. With the part enabled and the IEN current sink off, the disable level is set by the resistor divider. The disable level is defined by Equation 5. R1 V DISABLE = V R ⋅ 1 + ------R2 (EQ. 5) The difference between the enable and disable levels provides adjustable hysteresis so that noise on VIN2 does not interfere with the enabling or disabling of the regulator. (EQ. 6) V OUT I INRUSH = C OUT ⋅ -----------t SS (EQ. 7) The soft-start capacitor is immediately discharged by a 2.2Ω resistor whenever POR conditions are not met or EN is pulled low. The soft-start discharge time is equal to 256 clock cycles. 10 FN6947.1 May 23, 2011 ISL70001SRH VREF = 0.6V ISS = 23µA RD = 2.2Ω FB ERROR AMPLIFIER + + RB SS REF VREF RD ISS CSS CREF VOUT RT 3-bit undervoltage counter increments. The counter is reset if the feedback voltage rises back above the undervoltage threshold, plus a specified amount of hysteresis outlined in the “Electrical Specifications” table on page 8. If the 3-bit counter overflows, the undervoltage protection logic shuts down the regulator. After the regulator shuts down, it enters a delay interval equivalent to the soft-start interval, which allows the device to cool. The undervoltage counter is reset when the device enters the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the power-good signal goes high, and normal operation continues. If undervoltage conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. This hiccup mode continues indefinitely until the output soft-starts successfully. PWM LOGIC Overcurrent Protection FIGURE 6. SOFT-START CIRCUIT Power-Good The power-good (PGOOD) pin is an open-drain logic output that indicates when the output voltage of the regulator is within regulation limits. The power-good pin pulls low during shutdown and remains low when the controller is enabled. After a successful soft-start, the PGOOD pin releases, and the voltage rises with an external pull-up resistor. The power-good signal transitions low immediately when the EN pin is pulled low. The power-good circuitry monitors the FB pin and compares it to the rising and falling thresholds shown in the “Electrical Specifications” table on page 8. If the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. If the feedback voltage drops below a typical of 89% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. The PGOOD pin then releases and signals the return of the output voltage to within the power-good window. The PGOOD pin can be pulled up to any voltage from 0V to 5.5V, independently from the supply voltage. The pull-up resistor should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should be bypassed to DGND, with a 10nF ceramic capacitor to mitigate SEE. A pilot device integrated into the PMOS transistor of Power Block 4 samples current each cycle. This current feedback is scaled and compared to an overcurrent threshold based on the number of power blocks connected. Each additional power block connected beyond Power Block 4 increases the overcurrent limit by 2A. For example, if three power blocks are connected, the typical current limit threshold would be 3 x 2A = 6A. If the sampled current exceeds the overcurrent threshold, a 3-bit overcurrent counter increments by one LSB. If the sampled current falls below the threshold before the counter overflows, the counter is reset. Once the overcurrent counter reaches 111, the regulator shuts down. After the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, which allows the device to cool. The overcurrent counter is reset when the device enters the delay interval. The protection logic initiates a normal soft-start once the delay interval ends. If the output successfully soft-starts, the power-good signal goes high, and normal operation continues. If overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shut downs the output again. This hiccup mode continues indefinitely until the output soft-starts successfully. Note: To prevent severe negative ringing that can disturb the overcurrent counter, it is recommended that a Schottky diode of appropriate rating be added from the LXx pins to the PGNDx pins. Component Selection Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides a complete evaluation board that includes schematic, BOM, and an example PCB layout (see Ordering Information table on page 2). Fault Monitoring and Protection The ISL70001SRH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device. Undervoltage Protection A hysteretic comparator monitors the FB pin of the regulator. The feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. Once the comparator trips, indicating a valid undervoltage condition, a 11 Output Filter Design The output inductor and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage FN6947.1 May 23, 2011 ISL70001SRH at the phase node. The filter must also provide the transient energy until the regulator can respond. Since the filter has low bandwidth relative to the switching frequency, it limits the system transient response. The output capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand. OUTPUT INDUCTOR SELECTION Once the output capacitors are selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance as shown in Equation 11. ( V IN – V OUT ) V OUT L OUT ≥ ESR × ------------------------------------------------f s × V IN × V P-P(MAX) (EQ. 11) OUTPUT CAPACITOR SELECTION The critical load parameters in choosing the output capacitors are the maximum size of the load step (ΔISTEP), the load-current slew rate (di/dt), and the maximum allowable output voltage deviation under transient loading (ΔVMAX). Capacitors are characterized according to their capacitance, ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). At the beginning of a load transient, the output capacitors supply all of the transient current. The output voltage initially deviates by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in Equation 8. di Δ V MAX ≈ ESL × ---- + [ ESR × Δ I STEP ] dt (EQ. 8) Since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. Equation 12 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. Equation 13 addresses the leading edge. Normally, the trailing edge dictates the inductance selection because duty cycles are usually