5962R9582001VXC

® HS-82C85RH Data Sheet April 20, 2007 FN3044.3 Radiation Hardened CMOS Static Clock Controller/Generator The Intersil HS-82C85RH is a high performance, radiation hardened CMOS Clock Controller/Generator designed to support systems utilizing radiation hardened static CMOS microprocessors such as the HS-80C86RH. The HS-82C85RH contains a crystal controlled oscillator, reset pulse conditioning, halt/restart logic, and divide-by-256 circuitry. These features provide the means to stop the system clock, stop the clock oscillator, or run the system at a low frequency (CLK/256), enhancing control of static system power dissipation and allowing system shut-down during periods of external stress. Static CMOS circuit design insures low operating power and permits operation with an external frequency source from DC to 15MHz. Crystal controlled operation to 15MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. Outputs are guaranteed compatible with both CMOS and TTL specifications. The Intersil hardened field CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95820. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/military/ Features • Electrically Screened to SMD # 5962-95820 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . . . .>108 rad(Si)/s - Latch Up Free EPI-CMOS • Very Low Power Consumption • Pin Compatible with NMOS 8285 and Intersil 82C85 • Generates System Clocks for Microprocessors and Peripherals • Complete Control Over System Clock Operation for Very Low System Power - Stop-Oscillator - Stop-Clock - Low Frequency (Slo) Mode - Full Speed Operation • DC to 15MHz Operation (DC to 5MHz System Clock) • Generates Both 50% and 33% Duty Cycle Clocks (Synchronized) • Uses Either Parallel Mode Crystal Circuit or External Frequency Source • Hardened Field, Self-Aligned, Junction Isolated CMOS Process • Single 5V Supply • Military Temperature Range . . . . . . . . . . . -55°C to +125°C Ordering Information ORDERING NUMBER 5962R9582001VJC 5962R9582001VXC 5962R9582001QJC 5962R9582001QXC INTERNAL MKT. NUMBER HS1-82C85RH-Q HS9-82C85RH-Q HS1-82C85RH-8 HS9-82C85RH-8 PART MARKING Q 5962R95 82001VJC Q 5962R95 82001VXC Q 5962R95 82001VJC Q 5962R95 82001VXC TEMP. RANGE (°C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE 24 Ld SBDIP 24 Ld Flatpack 24 Ld SBDIP 24 Ld Flatpack PKG. DWG. # D24.6 K24.A D24.6 K24.A 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-82C85RH Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW CSYNC 1 PCLK 2 AEN1 3 RDY1 4 READY 5 RDY2 6 AEN2 7 CLK 8 GND 9 CLK50 10 START 11 SLO/FST 12 24 VDD 23 X1 22 X2 21 ASYNC 20 EFI 19 F/C 18 OSC 17 RES 16 RESET 15 S2/STOP 14 S1 13 S0 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND CLK50 START SLO/FST 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD X1 X2 ASYNC EFI F/C OSC RES RESET S2/STOP S1 S0 Pin Descriptions PIN X1 X2 EFI PIN NUMBER 23 22 20 TYPE I O I DESCRIPTION CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency must be three times the maximum desired processor clock frequency. X1 is the oscillator circuit input and X2 is the output of the oscillator circuit. EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This input signal should be a square wave with a frequency of three times the maximum desired CLK output frequency. FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the main frequency source. When F/C is LOW, the HS-82C85RH clocks are derived from the crystal oscillator circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched during normal operation. A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appropriate restart sequence is completed. When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be restarted when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal (X1) reaches the Schmitt trigger input threshold and an 8K internal counter reaches terminal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized. The HS-82C85RH will restart in the same mode (SLO/FST) in which it stopped. A high level on START disables the STOP mode. S2/STOP, S1, S0 are used to stop the HS-82C85RH clock outputs (CLK, CLK50, PCLK) and are sampled by the rising edge of CLK. CLK, CLK50 and PCLK are stopped by S2/STOP, S1, S0 being in the LHH state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state. PCLK stops in it’s current state (high or low). When in the crystal mode (F/C) low and a STOP command is issued, the HS-82C85RH oscillator will stop along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK outputs will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock is restarted by the START input signal going true (HIGH) or the reset input (RES) going low. F/C 19 I START 11 I S0 S1 S2/STOP 13 14 15 I I I 2 FN3044.3 April 20, 2007 HS-82C85RH Pin Descriptions PIN SLO/FST PIN NUMBER 12 (Continued) TYPE I DESCRIPTION SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are equal to the crystal or EFI frequency divided by 768. SLO/FST mode changes are internally synchronized to eliminate glitches on the CLK and CLK50. START and STOP control of the oscillator or EFI is available in either the SLOW or FAST frequency modes. The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it will be recognized. This eliminates unwanted frequency changes which could be caused by glitches or noise transients. The SLO/FST input must be held HIGH for at least 6 OSC/EFI clock pulses to guarantee a transition to FAST mode operation. PROCESSOR CLOCK: CLK is the clock output used by the HS-80C86RH processor and other peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crystal or EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency which is equal to the crystal or EFI input frequency divide by 768. CLK has a 33% duty cycle. 50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output frequency equal to the crystal or EFI input frequency divided by 768. PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the crystal or EFI input frequency divided by six and has a 50% duty cycle. PCLK frequency is unaffected by the state of the SLO/FST input. OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input. When the HS-82C85RH is in the crystal mode (F/C LOW) and a STOP command is issued, the OSC output will stop in the HIGH state. When the HS-82C85RH is in the EFI mode (F/C HIGH), the oscillator (if operational) will continue to run when a STOP command is issued and OSC remains active. RESET IN: RES is an active LOW signal which is used to generate RESET. The HS-82C85RH provides a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper duration. RES starts crystal oscillator operation. RESET: RESET is an active HIGH signal which is used to reset the HS-80C86RH processor. Its timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK pulses after the rising edge of RES. CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple HS-82C85RHs to be synchronized to provide multiple in-phase clock signals. When CSYNC is HIGH, the internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must be externally synchronized to EFI. ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processor to access two Multi-Master System Buses. BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a device located on the system data bus that data has been received, or is available. RDY1 is qualified by AEN1 while RDY2 is qualified by AEN2. READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are provided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided. READY: READY is an active HIGH signal which is used to inform the HS-80C86RH that it may conclude a pending data transfer. Ground +5V power supply CLK 8 O CLK50 10 O PCLK 2 O OSC 18 O RES 17 I RESET 16 O CSYNC 1 I AEN1 AEN2 RDY1 RDY2 ASYNC 3 7 4 6 21 I I I I I READY GND VDD 5 9 24 O I I 3 FN3044.3 April 20, 2007 HS-82C85RH Functional Diagram RES (17) RESTART LOGIC RESET PULSE CONDITIONING LOGIC RESTART (16) RESET START (11) CSYNC (1) SYNC LOGIC SYNC CLOCK LOGIC (÷ 3) (8) CLK SLO/FST (12) F/C (19) EFI (20) X2 (22) X1 (23) S2/STOP (15) S1 (14) SO (13) RDY1 (4) AEN1 (3) AEN2 (7) RDY2 (6) ASYNC (21) READY SELECT STOP LOGIC HALT OSCILLATOR EXTERNAL FREQUENCY SELECT OSC SPEED SELECT ÷ 256 OR ÷ 1 MASTER OSC PERIPHERAL CLOCK (÷ 6) (10) CLK50 SELECTED OSC (2) PCLK (18) OSC READY SYNC (24) VDD (9) GND (5) READY AC Test Circuit VDD R (NOTES 1, 2) FROM OUTPUT UNDER TEST CL (NOTE 4) NOTES: 1. R = 370Ω at V = 2.25 for CLK and CLK50 outputs. 2. R = 494Ω at V = 2.87 for all other outputs. 3. CL = 50pF. 4. CL Includes probe and jig capacitance. 4 FN3044.3 April 20, 2007 HS-82C85RH Waveforms tELEL EFI I tELEH tEHEL OSC O tOHCL tOHCH CLK O tCHCL tCLCH tCLCL tCLC50L CLK50 O t5CHCL TCLPH PCLK O tYHEH CSYNC I tYHYL tEHYL tPHPL tPLPH tCLPL t5CLCH 3.5V 1.0V tCL2CL1 tOLCH CLK AND CLK50 tCH1CH2 FIGURE 1. WAVEFORMS FOR CLOCKS NOTE: All timing measurements are made at 1.5V, unless otherwise noted. CLK tCLR1X tR1VCH RDY1, 2 tA1VR1V AEN1, 2 tCLA1X tCLR1X tR1VCL tAYVCL ASYNC tCLAYX READY tRYHCH tRYLCL FIGURE 2. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES) 5 FN3044.3 April 20, 2007 HS-82C85RH Waveforms CLK tR1VCL (Continued) tCLR1X tR1VCL RDY1, 2 tA1VR1V AEN1, 2 tCLA1X tCLR1X tAYVCL ASYNC tCLAYX READY tRYHCH tRYLCL FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES) EFI CLK tSTOP CLK50 PCLK S0 tCHSX tSVCH S1 tSVCH tCHSX S2/STOP RES tRSVCH START FIGURE 4. CLOCK STOP (F/C HIGH OR F/C LOW) 6 FN3044.3 April 20, 2007 HS-82C85RH Waveforms (Continued) EFI CLK CLK50 tSTART PCLK S0 S1 S2/STOP RES START FIGURE 5. CLOCK START (F/C HIGH) tSHSL START tOST OSC CRYSTAL OSCILLATOR STARTUP TIME CLK 8192 CYCLES CLK50 PCLK FIGURE 6. CLOCK START (F/C LOW) tSHSL RES tI1HCL CLK tCLIL RESET tRST tCLIL tI1HCL FIGURE 7. RESET TIMING (CLK RUNNING WITH F/C LOW - OSC MODE; CLK RUNNING - OR STOPPED WITH F/C HIGH EFI MODE) 7 FN3044.3 April 20, 2007 HS-82C85RH Waveforms (Continued) tSHSL RES CLK tCLIL RESET OSC STARTUP TIME OSC tOST tRST 8192 CYCLES FIGURE 8. RESET TIMING OSCILLATOR STOPPED (F/C LOW) NOTE: CLK, CLK50, PCLK remain in the high state until RES goes high and 8192 valid oscillator cycles have been registered by the HS-82C85RH internal counter tOST time period). After RES goes high and CLK, CLK50, PCLK become active, the RESET output will remain high for a minimum of 16 CLK cycles (tRST). EFI OR OSC PCLK SLO/FST CLK CLK50 FIGURE 9. SLO/FST TIMING OVERVIEW 195 EFI OR OSC CYCLES EFI OR OSC PCLK tSFPC (NOTE) SLO/FST tSFPC (NOTE) CLK CLK50 FIGURE 10. FAST TO SLOW CLOCK MODE TRANSITION NOTE: If tSFPC is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK. 8 FN3044.3 April 20, 2007 HS-82C85RH Waveforms (Continued) EFI OR OSC PCLK tSFPC (NOTE) SLO/FST 3 EFI PULSES CLK tSFPC (NOTE) CLK50 FIGURE 11. SLOW TO FAST CLOCK MODE TRANSITION NOTE: If tSFPC is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK. X1 15MHz C1 X2 C2 CLK LOAD † PULSE GENERATOR EFI CLK LOAD † CLK50 LOAD † VDD F/C CLK50 LOAD † F/C CSYNC CSYNC FIGURE 12. CLOCK HIGH AND LOW TIME (USING X1, X2) FIGURE 13. CLOCK HIGH AND LOW TIME (USING EFI) VDD C1 AEN1 X1 CLK LOAD † PULSE GENERATOR VDD EFI CLK LOAD † 15MHz F/C X2 AEN1 READY RDY2 F/C AEN2 CSYNC OSC LOAD † TRIGGER PULSE GENERATOR RDY2 AEN2 CSYNC READY LOAD † C2 TRIGGER PULSE GENERATOR FIGURE 14. READY TO CLOCK (USING X1, X2) FIGURE 15. READY TO CLOCK (USING EFI) † CL = 50pF 9 FN3044.3 April 20, 2007 HS-82C85RH Burn-In Circuits VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 F4 LOAD F3 F1 LOAD 1 F0 F0 F2 LOAD LOAD 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 2.7kΩ LOAD F5 F4 2.7kΩ LOAD LOAD F6 VDD LOAD F3 VDD F0 STATIC CONFIGURATION NOTES: 5. R = 10kΩ ±10%. 6. VDD = 6.0V ±5%. 7. TA = 125°C Min. 8. Package Code: SZ (24 Lead DIP). 9. F0 is 50% duty cycle square wave pulse burst. F0 is left low after pulse burst. NOTES: 10. R = 10kΩ ±10%. DYNAMIC CONFIGURATION 11. VDD = 6.0V ±5% (Burn-In); VDD = 5.5V ±5% (Life Test). 12. TA = 125°C Min. 13. Package Code: SZ (24 Lead DIP). 14. F0 = 10kHz, 50% duty cycle. 15. F1 = F0/2; F2 = F1/2; F3 = F2/2, F4 = F3/2; F5 = F4/2. Irradiation Circuit 1 LOAD 2 3 4 LOAD 5 6 7 LOAD 8 9 LOAD 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 LOAD 2.7kΩ LOAD LOAD LOAD 5.5V 2.7kΩ 5.5V NOTES: 16. R = 47kΩ ±10%. 17. Pins tied to VSS (0V): Pin 9. 18. Pins with loads: 2, 5, 8, 10, 16, 18, 22. 19. Pins tied to VDD: 1, 3, 4, 6, 7, 11 - 15, 17, 19 - 21, 23, 24. 20. VDD = 5.5V ±0.5V. 10 FN3044.3 April 20, 2007 HS-82C85RH Functional Description The HS-82C85RH Static Clock Controller/Generator provides simple and complete control of static CMOS system operating modes. The HS-82C85RH can operate with either an external crystal or an external frequency source and can support full speed, slow, stop-clock and stop-oscillator operation. While it is directly compatible with the Intersil HS-80C86RH CMOS 16-bit static microprocessor, the HS-82C85RH can also be used for general purpose system clock control. Separate signals are provided on the HS-82C85RH for stop and start control of the crystal oscillator and clock outputs. A single control line determines fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI frequency divided by 768) mode operation. A clock synchronization input is provided to allow the use of multiple HS-82C85RHs in the same system. The HS-82C85RH generates the proper HS-80C86RH reset pulse, and it also handles all data transfer timing by generating the HS-80C86RH ready signal. Automatic maximum mode HS-80C86RH software HALT instruction decode logic is present to ease the design of software-based clock control systems and provides complete software control of STOP mode operation. Automatic minimum mode software HALT instruction decoding can be easily implemented with a single 74HC74 device. Restart logic insures valid clock start-up and complete synchronization of CLK, CLK50 and PCLK. mode or a specific combination of modes. The appropriate operating mode can be matched to the power-performance level needed at a specific time or in a particular circumstance. Reset Logic The HS-82C85RH reset logic provides a Schmitt trigger input (RES) and a synchronizing flip-flop to generate there set timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the HS-82C85RH. When in the crystal oscillator (F/C = LOW) or the EFI (F/C = HIGH) mode, a LOW state on the RES input will set the RESET output to the HIGH state. It will also restart the oscillator circuit if it is in the idle state. The RESET output is guaranteed to stay in the HIGH state for a minimum of 16 CLK cycles after a low-to-high transition of the RES input. An oscillator restart count sequence will not be disturbed by RESET if this count is already in progress. After the restart counter expires, the RESET output will stay HIGH at least for 16 periods of CLK before going LOW. RESET can be kept high beyond this time by a continuing low input on the RES input. If F/C is low (crystal oscillator mode), a low state on RES starts the crystal oscillator circuit. The stopped outputs remain inactive, until the oscillator signal amplitude reaches the X1 Schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. After this count is complete, the stopped outputs (CLK, CLK50, PCLK) start cleanly with the proper phase relationships. This 8192 count requirement insures that the CLK, CLK50 and PCLK outputs will meet minimum clock requirements and will not be affected by unstable oscillator characteristics which may exist during the oscillator start-up sequence. This sequence is also followed when a START command is issued while the HS-82C85RH oscillator is stopped. Static Operating Modes The HS-82C85RH Static Clock Controller can be dynamically set to operate in any one of four modes at any one time: FAST, SLOW, STOP-CLOCK and STOP-OSCILLATOR. Each mode has distinct power and performance characteristics which can be matched to the needs of a particular system at a specific time (see Table 1). Keep in mind that a single system may require all of these operating modes at one time or another during normal operation. A design need not be limited to a single operating TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS OPERATING MODE Stop-Oscillator DESCRIPTION All system clocks and main clock oscillator are stopped POWER LEVEL Maximum savings PERFORMANCE Slowest response due to oscillator restart time Fast restart - no oscillator restart time Stop-Clock System CPU and peripherals clocks stop Reduced system power but main clock oscillator continues to run at rated frequency Power dissipation slightly higher than System CPU clocks are slowed while peripheral clock and main clock oscillator Stop-Clock run at rated frequency All clocks and oscillators run at rated frequency Highest power Slow Continuous operation at low frequency Fast Fastest response 11 FN3044.3 April 20, 2007 HS-82C85RH Oscillator/Clock Start Control Once the oscillator is stopped (or committed to stop) or at power-on, the restart sequence is initiated by a HIGH state on START or LOW state on RES. If F/C is HIGH, then restart occurs immediately after the START or RES input is synchronized internally. This insures that stopped outputs (CLK, PCLK, OSC and CLK50) start cleanly with the proper phase relationship. If F/C is low (crystal oscillator mode), a HIGH state on the START input or a low state on RES causes the crystal oscillator to be restarted. The stopped outputs remain stopped, until the oscillator signal amplitude reaches the X1 Schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. After this count is complete, the stopped outputs (CLK, CLK50, PCLK) start cleanly with the proper phase relationships. Typically, any input signal which meets the START input timing requirements can be used to start the HS-82C85RH. In many cases, this would be the INT output from an HS-82C59A CMOS Priority Interrupt Controller (see Figure 16). This output, which is active high, can be connected to both the HS-82C85RH START pin and to the INTR input on the microprocessor. When the INT output becomes active (as a result of a “restart” IRQ or a system reset), the oscillator/clock circuit on the HS-82C85RH will restart. Upon completion of the appropriate restart sequence, the CLK signal to the CPU will become active. The CPU can then respond to the stillpending interrupt request. Oscillator/Clock Stop Control The S0, S1, and S2/STOP control lines determine when the HS-82C85RH clock outputs or oscillator will stop. These three lines are designed to connect directly to the MAXimum mode HS-80C86RH status lines as shown in Figure 17. When used in this configuration, the HS-82C85RH will automatically recognize a software HALT command from the HS-80C86RH and stop the system clocks or oscillator. This allows complete software control of the STOP function. If the HS-80C86RH is used in the MINimum mode, the HS-82C85RH can be controlled using the S2/STOP input (with S0 and S1 held high). This can be done using the circuit shown in Figure 18. Since the HS-80C86RH, when executing a halt instruction in minimum mode, issues a single ALE pulse with no corresponding bus signals (DEN remains high), the ALE pulse will be clocked through the 74HC74 and put the HS-82C85RH into stop mode. HS-82C59A HS-82C85RH HS-80C86RH S2 INTR S2/STOP S1 S0 S1 S0 CLK INT START CLK MIN/MAX HS-80C86RH HS-82C85RH FIGURE 16. START CONTROL USING HS-82C59ARH INTERRUPT CONTROLLER FIGURE 17. STOP CONTROL USING HS-80C86RH MAXIMUM MODE STATUS LINES HS-80C86RH MICROPROCESSOR ALE 74HC74 QUAD D FLIP-FLOP WITH CLEAR 1D 1Q 2D 2Q 3D 3Q 4D 4Q CLR CLK VDD HS-82C85RH CLOCK CONTROLLER/ GENERATOR S0 S1 S2/STOP DEN RESET VDD MIN/MAX TO HS-80C86RH AND PERIPHERALS CLK RESET FIGURE 18. STOP CONTROL USING HS-80C86RH IN MINIMUM MODE 12 FN3044.3 April 20, 2007 HS-82C85RH The HS-82C85RH status inputs S2/STOP, S1, S0 are sampled on the rising edge of CLK. The oscillator (F/C LOW only) and clock outputs are stopped by S2/STOP, S1, S0 being in the LHH state on a low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on the previous low-to-high CLK transition. CLK and CLK50 will stop in the logic HIGH state after two additional complete cycles of CLK. PCLK stops in its current state (HIGH or LOW). This is true for both SLOW and FAST mode operation. or at slow speed (crystal or EFI frequency divided by 768) (see Figure 20). When in the SLOW mode, HS-82C85RH stop-clock and stop-oscillator functions operate in the same manner as in the FAST mode, and the frequency of PCLK is unaffected. X1 EFI VDD F/C S2/STOP STOP CONTROL S1 S0 X2 OSC Stop-Oscillator Mode When the HS-82C85RH is stopped while in the crystal mode (F/C LOW), the oscillator, in addition to all system clock signals (CLK, CLK50 and PCLK), are stopped. CLK and CLK50 stop in the high state. PCLK stops in its current state (high or low). With the oscillator stopped, HS-82C85RH power drops to its lowest level. All clocks and oscillators are stopped. All devices in the system which are driven by the HS-82C85RH go into the lowest power standby mode. The HS-82C85RH also goes into standby and requires a power supply current of less than 100mA. START START CONTROL FIGURE 19. STOP-CLOCK MODE IN EFI MODE WITH OSCILLATOR AS FREQUENCY SOURCE Stop-Clock Mode When the HS-82C85RH is in the EFI mode (F/C HIGH) and a STOP command is issued, all system clock signals (CLK, CLK50 and PCLK) are stopped. CLK and CLK50 stop in the high state. PCLK stops in its current state (high or low). The HS-82C85RH can also provide its own EFI source simply by connecting the OSC output to the EFI input and pulling the F/C input HIGH. This puts the HS-82C85RH into the External Frequency Mode using its own oscillator as an external source signal (see Figure 19). In this configuration, when the HS-82C85RH is stopped in the EFI mode, the oscillator continues to run. Only the clocks to the CPU and peripherals (CLK, CLK50 and PCLK) are stopped. The SLOW mode allows the CPU and the system to operate at a reduced rate which, in turn, reduces system power. For example, the operating power for the HS-80C86RH CPU is 10mA/MHz of clock frequency. When the SLOW mode is used in a typical 5MHz system, CLK and CLK50 run at approximately 20kHz. At this reduced frequency, the average operating current of the CPU drops to 200mA. Adding the HS-80C86RH 500mA standby current brings the total current to 700mA. While the CPU and peripherals run slower and the HS-82C85RH CLK and CLK50 outputs switch at a reduced frequency, the main HS-82C85RH oscillator is still running at the maximum frequency (determined by the crystal or EFI input frequency.) Since CMOS power is directly related to operating frequency, HS-82C85RH power supply current will typically be reduced by 25% - 35%. Clock Slow/Fast Operation The SLO/FST input determines whether the CLK and CLK50 outputs run at full speed (crystal or EFI frequency divided by 3) EFI OR OSC PCLK SLO/FST CLK CLK50 FIGURE 20. SLOW/FAST TIMING OVERVIEW 13 FN3044.3 April 20, 2007 HS-82C85RH Internal logic requires that the SLO/FST pin be held low for at least 195 oscillator or EFI clock pulses before the SLOW mode command is recognized. This requirement eliminates unwanted FAST-to-SLOW mode frequency changes which could be caused by glitches or noise spikes. To guarantee FAST mode recognition, the SLO/FST pin must be held high for at least 3 OSC or EFI pulses. The HS-82C85RH will begin FAST mode operation on the next PCLK edge after FAST command recognition. Proper CLK and CLK50 phase relationships are maintained and minimum pulse width specifications are met. FAST-to-SLOW or SLOW-to-FAST mode changes will occur on the next rising or falling edge of PCLK. It is important to remember that the transition time for operating frequency changes, which are dependent upon PCLK, will vary with the HS-82C85RH oscillator or EFI frequency. input connections. The output of the oscillator is buffered and available at the OSC output (pin 18) for generation of other system timing signals. TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES FAST CPU Frequency XTAL Frequency IDD HS-80C86RH HS-82C85RH HS-82C08RH 82C82 HS-82C54RH HS-82C55ARH 74HCXX + Other HS-65262RH HS-6617RH 50mA 24.7mA 1.0mA 1.7mA 943.0μA 3.2μA 2.9mA 4.0mA 6.3mA 2.5mA 16.9mA 10.0μA 6.5mA 915.0μA 1.2μA 110.0μA 50.0μA 52.5μA 250μA 14.1mA 1.0μA 1.0μA 1.0μA 1.0μA 90.0μA 10.0μA 12.0μA 250μA 24.4μA 1.0μA 1.0μA 1.0μA 1.0μA 90.0μA 10.0μA 12.0μA 5MHz 15MHz SLOW 20kHz 15MHz STOPCLOCK DC 15MHz STOPOSC DC DC Slow/Fast Mode Control The HS-82C55ARH programmable peripheral interface can be used to provide slow/fast mode control by connecting one of the port pins directly to the SLO/FST pin (see Figure 21). With the port pin configured as an output, software control of the SLO/FST pin is provided by simply writing a logical one (FAST mode) or logical zero (SLOW Mode) to the corresponding port. PORT C is well-suited for this function due to its bit set and reset capabilities. NOTE: All measurements taken at room temperature, VDD = +5.0V. Power supply current levels will be dependent upon system configuration and frequency of operation. CLK CLK HS-82C85RH CLOCK CONTROLLER GENERATOR HS-82C55RH PERIPHERAL INTERFACE HS-80C86RH μPROCESSOR For the most stable operation of the oscillator (OSC) output circuit, two capacitors (C1 = C2) are recommended. Capacitors C1 and C2 are chosen such that their combined capacitance matches the load capacitance as specified by the crystal manufacturer. This insures operation within the frequency tolerance specified by the crystal manufacturer. The crystal/capacitor configuration and the formula used to determine the capacitor values are shown in Figure 22. Crystal Specifications are shown in Table 3. For additional information on crystal operation, see Intersil publication Tech Brief 47. SLO/FST PC0 D0 - 8 FIGURE 21. SLOW/FAST MODE CONTROL USING HS-82C55RH PERIPHERAL INTERFACE Alternate Operating Modes Using alternate modes of operation (slow, stop-clock, stoposcillator) will reduce the average system operating power dissipation in a static CMOS system (see Table 2). This does not mean that system speed or throughput must be reduced. When used appropriately, the slow, stop-clock, stoposcillator modes can make your design more power-efficient while maintaining maximum system performance. C1 CRYSTAL 2.4MHz - 15MHz X1 X2 C2 Oscillator The oscillator circuit of the HS-82C85RH is designed primarily for use with an external parallel resonant, fundamental mode crystal from which the basic operating frequency is derived. The crystal frequency must be three times the required CPU clock. X1 and X2 are the two crystal 14 C1 • C2 CT = --------------------- (Including stray capacitance) C1 + C2 FIGURE 22. CRYSTAL CONNECTION FN3044.3 April 20, 2007 HS-82C85RH TABLE 3. CRYSTAL SPECIFICATIONS PARAMETER Frequency Type of Operation Load Capacitance R Series (Max) TYPICAL CRYSTAL SPECIFICATION 2.4MHz to 15MHz Parallel Resonant, Fund. Mode 20pF or 32pF 56Ω (f = 15MHz, CL = 32pF), 105Ω (f = 15MHz, CL = 20pF) causes all clocks (CLK, CLK50 and PCLK) to stop in the HIGH state. It is necessary to synchronize the CSYNC input to the EFI clock using two flip-flops as shown in Figure 23. Multiple external flip-flops are necessary to minimize the occurrence of metastable (or indeterminate) states. Ready Synchronization Two RDY inputs (RDY1, RDY2) are provided to accommodate two system buses. Each RDY input is qualified by its corresponding AEN input (AEN1, AEN2). Reception of a valid RDY signal causes the HS-82C85RH to output READY high, informing the HS-80C86RH that the pending data transfer may be concluded (see HS-80C86RH data sheet system timing). Synchronization is required for all asynchronous activegoing edges of either RDY input to guarantee that the RDY set up and hold times are met. Inactive-going edges of RDY in normally ready systems do not require synchronization but must satisfy RDY setup and hold as a matter of proper system design. The ASYNC input defines two modes of RDY synchronization operation. When ASYNC is LOW, two stages of synchronization are provided for active RDY input signals. Positive-going asynchronous RDY inputs will first be synchronized to flip-flop one at the rising edge of CLK (requiring a setup time TR1VCH) and then synchronized to flip-flop two at the next falling edge of CLK, after which time the READY output will go HIGH. Negative-going asynchronous RDY inputs will be synchronized directly to flip-flop two at the falling edge of CLK, after which time the RDY output will go inactive. This mode of operation is intended for use by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the required RDY setup timing (TR1VCL) on each bus cycle. When ASYNC is high or left open, the first RDY flip-flop is bypassed in the RDY synchronization logic. RDY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the processor. This mode is available for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system. CSYNC WITH HS-82C85RH(s) EFI CLK SYNCH EFI HS-82C85RH D > Q D Q > (TO OTHER HS-82C85RHs) CSYNC Frequency Source Selection The F/C input is a strapping pin that selects either the crystal oscillator or the EFI input as the source frequency for clock generation. If the EFI input is selected as the source, the oscillator section (OSC output) can be used independently for another clock source. If a crystal is not used, then crystal input X1 (pin 23) must be tied to VDD or GND and X2 (pin 22) should be left open. If the EFI mode is not used, then EFI (pin 20) should be tied to VDD or GND. Clock Generator The clock generator consists of two synchronous divide-bythree counters with special clear inputs that inhibit the counting. One counter generates a 33% duty cycle waveform (CLK) and the other generates a 50% duty cycle waveform (CLK50). These two counters are negative-edge synchronized, with the low-going transitions of both waveforms occurring on the same oscillator transition. The CLK and CLK50 output frequencies are one-third of the base input frequency when SLO/FST is high and are equal to the base input frequency divided by 768 when SLO/FST is low. The CLK output is a 33% duty cycle clock signal designed to drive the HS-80C86RH microprocessor directly. CLK50 has a 50% duty cycle output synchronous with CLK, designed to drive coprocessors and peripherals requiring a 50% duty cycle clock. PCLK is a peripheral clock signal with an output frequency equal to the oscillator or EFI frequency divided by 6. PCLK has a 50% duty cycle. PCLK is unaffected by SLO/FST. When the HS-82C85RH is placed in the STOP mode, PCLK will remain in its current state (logic high or logic low) until a RES or START command restarts the HS-82C85RH clock circuitry. PCLK is negative-edge synchronized with CLK and CLK50. Since PCLK continues to run at the same frequency regardless of the state of the SLO/FST pin, it can be used by other devices in the system which need a fixed high frequency clock. For example, PCLK could be used to clock an HS-82C54RH programmable interval timer to produce a real-time clock for the system or as a baud rate generator to maintain serial data communications during SLOW mode operation. Clock Synchronization The clock synchronization (CSYNC) input allows the output clocks to be synchronized with an external event (such as another HS-82C85RH clock signal). CSYNC going active FIGURE 23. CSYNC SYNCHRONIZATION METHODS 15 FN3044.3 April 20, 2007 HS-82C85RH Die Characteristics DIE DIMENSIONS: 2770μm x 3130μm x 483μm ±25μm INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kÅ ±1kÅ Top Metallization: Type: Al/Si Thickness: 11kÅ ±2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: 1.6 x 104 A/cm2 Metallization Mask Layout HS-82C85RH (21) ASYNC (20) EFI (19) F/C READY (5) RDY2 (6) AEN2 (7) M CLK (8) A S K (17) RES (18) OSC (16) RESET START (11) GND (VSS) (9) SLO/FST (12) S2/STOP (15) CLK50 (10) S0 (13) S1 (14) (1) CSYNC (2) PCLK (3) AEN1 (24) VDD (23) X1 RDY1 (4) 16 (22) X2 FN3044.3 April 20, 2007 HS-82C85RH Ceramic Metal Seal Flatpack Packages (Flatpack) A K24.A MIL-STD-1835 CDFP4-F24 (F-6A, CONFIGURATION B) 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.350 0.180 0.030 0.008 0.250 0.026 0.005 24 MAX 0.115 0.022 0.019 0.009 0.006 0.640 0.420 0.450 0.015 0.370 0.045 0.0015 A b b1 c c1 D MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 9.14 4.57 0.76 1.27 BSC 0.20 6.35 0.66 0.13 24 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 16.26 10.67 11.43 NOTES 3 3 7 2 8 6 Rev. 0 5/18/94 e PIN NO. 1 ID AREA A -A- -B- D S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS E E1 E2 E3 e k L Q S1 M N 0.050 BSC BASE METAL b1 M M (b) SECTION A-A (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 17 FN3044.3 April 20, 2007 HS-82C85RH Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH D24.6 MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C) 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.225 0.026 0.023 0.065 0.045 0.018 0.015 1.290 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.72 0.66 0.58 1.65 1.14 0.46 0.38 32.77 15.49 2.54 BSC 15.24 BSC 7.62 BSC 3.05 0.38 0.13 0.13 90o 24 5.08 1.91 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94 E eA e eA/2 c 0.100 BSC 0.600 BSC 0.300 BSC 0.120 0.015 0.005 0.005 90o 24 0.200 0.075 105o 0.015 0.030 0.010 0.0015 ccc M C A - B S D S aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN3044.3 April 20, 2007