5962R9582401QQC

CT U CT ODU E PR E P RO D ET OL UT at OBS UBSTIT H or n ter E S 0 C 8 6R r t C e m /t s c IBL Sheet Suppo SData S-8 o H PO S al s il. c h n ic in t e r r T ec o r w w w . u IL ac t o c o n t - IN T E R S 888 1® HS-80C85RH August 2000 File Number 3036.3 Radiation Hardened 8-Bit CMOS Microprocessor The HS-80C85RH is an 8-bit CMOS microprocessor fabricated using the Intersil radiation hardened self-aligned junction isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-80C85RH is a functional logic emulation of the HMOS 8085 and its instruction set is 100% software compatible with the HMOS device. The HS80C85RH is designed for operation with a single 5 volt power supply. Its high level of integration allows the construction of a radiation hardened microcomputer system with as few as three ICs (HS-80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/56RH RAM I/O. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95824. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Features • Electrically Screened to SMD # 5962-95824 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened EPI-CMOS - Parametrics Guaranteed . . . . . . . . . . . 1 x 105RAD(Si) - Transient Upset . . . . . . . . . . . . . . . . >1 x 108RAD(Si)/s - Latch-up Free . . . . . . . . . . . . . . . . . >1 x 1012RAD(Si)/s • Low Standby Current . . . . . . . . . . . . . . . . . . . . 500µA Max • Low Operating Current. . . . . . . . . . 5.0mA/MHz (X1 Input) • Electrically Equivalent to Sandia SA 3000 • 100% Software Compatible with INTEL 8085 • Operation from DC to 2MHz, Post Radiation • Single 5V Power Supply • On-Chip Clock Generator and System Controller • Four Vectored Interrupt Inputs • Completely Static Design • Self Aligned Junction Isolated (SAJI) Process • Military Temperature Range. . . . . . . . . . . -55oC to 125oC Ordering Information ORDERING NUMBER 5962R9582401QQC 5962R9582401QXC 5962R9582401VQC 5962R9582401VXC HS9-80C85RH/Proto INTERNAL MKT. NUMBER HS1-80C85RH-8 HS9-80C85RH-8 HS1-80C85RH-Q HS9-80C85RH-Q HS9-80C85RH/Proto TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HS-80C85RH Pinouts 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T40 TOP VIEW X1 1 X2 2 RESET OUT 3 SOD 4 SID 5 TRAP 6 RST 7.5 7 RST 6.5 8 RST 5.5 9 INTR 10 INTA 11 AD0 12 AD1 13 AD2 14 AD3 15 AD4 16 AD5 17 AD6 18 AD7 19 GND 20 40 VDD 39 HOLD 38 HLDA 37 CLOCK OUT 36 RESET IN 35 READY 34 IO/ M 33 S1 32 RD 31 WR 30 ALE 29 S0 28 A15 27 A14 26 A13 25 A12 24 A11 23 A10 22 A9 21 A8 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K42.A TOP VIEW X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 NC NC AD5 AD6 AD7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD HOLD HLDA CLOCK OUT RESET IN READY IO/ M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8 GND Functional Diagram INTR INTA RST 5.5 RST 6.5 RST 7.5 TRAP SID SOD INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS ACCUMULATOR (8) TEMP REG (8) FLAG (5) FLIP FLOPS INSTRUCTION REGISTER (8) B REG (8) D REG (8) H REG (8) C REG (8) REGISTER ARRAY DATA ADDRESS BUFFER (8) AD1-AD0 ADDRESS BUS E REG (8) L REG (8) ARITHMETIC LOGIC UNIT (ALU) (8) POWER SUPPLY X1 X2 VDD GND CLK GEN INSTRUCTION DECODER AND MACHINE CYCLE ENCODING STACK POINTER (16) PROGRAM COUNTER (16) INCREMENTER DECREMENTER ADDRESS LATCH (16) TIMING AND CONTROL CONTROL STATUS DMA RESET ADDRESS BUFFER (8) READY CLK OUT RD WR ALE S0 S1 IO/M HLDA HOLD RESET IN RESET OUT A15-A8 ADDRESS BUS 2 HS-80C85RH Pin Description SYMBOL A8 - A15 AD0-7 PIN NUMBER 21-28 12-19 TYPE O I/O DESCRIPTION Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address, three-stated during Hold and Halt modes and during RESET. Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge of ALE can also be used to strobe the status information. ALE is never three-stated. Machine Cycle Status: IO/M 0 0 1 1 0 1 1 T T T S1 0 1 0 1 1 1 1 0 X X S0 1 0 1 0 1 1 1 0 X X STATUS Memory write Memory write I/O write I/O read Opcode fetch Opcode fetch Interrupt acknowledge Halt Hold Reset ALE 32 O S0, S1, and IO/M 31, 35, and 36 O T = three-State (high impedance) X = Unspecified S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines. RD WR 34 33 O O Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET. Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes and during RESET. Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY to go high before completing the read or write cycle. READY must conform to specified setup and hold times. Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are 3-stated. Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus one half clock cycle after HLDA goes low. Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. READY 35 I HOLD 39 I HLDA 38 O INTR 10 I 3 HS-80C85RH Pin Description SYMBOL INTA RST 5.5 RST 6.5 RST 7.5 TRAP (Continued) TYPE O I DESCRIPTION Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port. Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. (See Table 6.) Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data and address buses and the control lines are three-stated during RESET and because of the asynchronous nature of RESET the processor’s internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper reset operation after the power-up duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset condition as long as RESET IN is applied. Reset Out: Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods. X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the processor’s internal operating frequency. Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period. Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction. Power: +5V supply. Ground: Reference. PIN NUMBER 11 9 8 7 6 I RESET IN 36 I RESET OUT X1 X2 CLK SID SOD VCC GND 3 1 2 37 5 4 40 20 O I O O I O I I RESET IN R1 VDD C1 TYPICAL POWER-ON RESET RC VALUES (NOTE) R1 = 75kΩ C1 = 1µF NOTE: Values may have to vary due to applied power supply ramp up time. FIGURE 1. POWER-ON RESET CIRCUIT 4 HS-80C85RH Waveforms X1 INPUT CLK OUTPUT tXKR tXKF t1 tr t2 tf tCYC FIGURE 2. CLOCK T1 CLK tLCK A8-15 ADDRESS tAD AD0-AD7 tLL ALE tAL RD/INTA tAC tLC ADDRESS tLA tAFR T2 T3 T1 tCA tRAE tRDH DATA IN tCL tLDR tRD tCC FIGURE 3. READ T1 CLK tLCK A8-15 ADDRESS tLDW AD0-AD7 tLL ALE tAL tLC tAC ADDRESS tLA T2 T3 T1 tCA DATA OUT tDW tWDL tCC tWD WR tCL FIGURE 4. WRITE 5 HS-80C85RH Waveforms CLK (Continued) T2 T2 THOLD THOLD T1 HOLD tHDS HLDA tHDH tHACK tHABF tHABE BUS (ADDRESS, CONTROLS) FIGURE 5. HOLD T1 CLK tLCK ADDRESS tAD AD0-AD7 tLL ALE tAL RD/INTA tAC tARY READY tRYS tRYH tRYS tRYH tLC tLRY ADDRESS tLA tAFR tLDR tRD tCC tRAE tRDH DATA IN tCL T2 TWAIT T3 T3 tCA A8-15 NOTE: READY must remain stable during setup and hold times. FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE T1 T2 T3 T4 T5 T6 THOLD T1 T2 A8-15 A0-7 CALL INST. BUS FLOATING (NOTE) RD INTR INTR tINS tINH HOLD HLDA tHDH tHDS tHACK tHABE tHABF NOTE: IO/M is also floating during this time. FIGURE 7. INTERRUPT AND HOLD 6 HS-80C85RH TABLE 1. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Input Capacitance I/O Capacitance Output Capacitance NOTE: 1. All measurements referenced to device ground. TABLE 2. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY NAME TRAP RST 7.5 RST 6.5 RST 5.5 INTR NOTES: 2. The processor pushes the PC on the stack before branching to the indicated address. 3. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged. TABLE 3. BUS TIMING SPECIFICATION AS A tCYC DEPENDENT SYMBOL tAL tLA tLL tLCK tLC tAD tRD tRAE tCA tDW tWD HS-8OC85RH (1/2)T- 175 (1/2)T- 175 (1/2)T-50 (1/2)T- 125 (1/2)T- 100 (5/2 + N)T - 375 (3/2 + N)T - 375 (1/2)T- 130 (1/2)T - 100 (3/2 + N)T - 175 (1/2)T-100 Minimum Minimum Minimum Minimum Minimum Maximum Maximum Minimum Minimum Minimum Minimum SYMBOL tCC tCL tARY tHACK tHABF tHABE tAC t1 t2 tRV tLDR HS-8OC85RH (3/2 + N)T - 175 (1/2)T - 190 (3/2)T - 500 (1/2)T - 160 (1/2)T +125 (1/2)T +125 (2/2)T - 200 (1/2)T-210 (1/2)T- 150 (3/2)T - 200 (4/2)T - 325 Minimum Minimum Maximum Minimum Maximum Maximum Minimum Minimum Minimum Minimum Maximum PRIORITY 1 2 3 4 5 ADDRESS BRANCHED TO (1) WHEN INTERRUPT OCCURS 24H 3CH 34CH 2CH See Note 2 TYPE TRIGGER Rising edge and high level until sampled. Rising edge (latched). High level until sampled. High level until sampled. High level until sampled. SYMBOL CIN CI/O COUT (NOTE 1) CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz VDD = Open, f = 1MHz TEMPERATURE (oC) T A = 25 T A = 25 T A = 25 MIN MAX 12 13 12 UNITS pF pF pF NOTE: N is equal to the total WAIT states T = tCYC. 7 HS-80C85RH TABLE 4. INSTRUCTION SET SUMMARY MNEMONIC MOVr1, r2 MOV M.r MOV r.M MVl r MVl M LXl B LXl D LXl H STAX B STAX D LDAX B LDAX D STA LDA SHLD LHLD XCHG INSTRUCTION CODE D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D 1 D D 1 0 0 1 0 0 0 0 1 1 1 1 1 D 1 D D 1 0 1 0 0 1 0 1 1 1 0 0 0 D 0 D D 0 0 0 0 0 0 1 1 0 1 0 1 1 S S 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S S 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 OPERATIONS DESCRIPTION TABLE 4. INSTRUCTION SET SUMMARY (Continued) MNEMONIC RNZ S Move register to register S Move register to memory 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 Move memory to register Move immediate register Move immediate memory Load immediate register Pair B & C Load immediate register Pair D & E Load immediate register Pair H & L Store A indirect Store A indirect Load A indirect Load A indirect Store A direct Load A direct Store H & L direct Load H & L direct Exchange D & E, H & L Registers Push register Pair B & C on stack Push register Pair D & E on stack Push register Pair H & L on stack Push A and Flags on stack Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry Return on zero JUMP JMP JC JNC JZ JNZ JP 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive DCX SP 0 0 1 1 1 0 1 1 POP B POP D POP H POP PSW XTHL SPHL LXI SP INX SP 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 RP RM RPE RPO RESTART RST IN OUT INR r DCR r INR M DCR M INX B INX D 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 A 0 0 D D 1 1 0 0 A 1 1 D D 1 1 0 1 A 1 0 D D 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 Restart Input Output Increment register Decrement register Increment memory Decrement memory Increment B & C registers Increment D & E registers Pop register Pair B & C off stack Pop register Pair D & E off stack Popregister Pair H & L off stack Pop A and Flags off stack Exchange top ot stack, H & L H & L to stack pointer Load immediate stack pointer Increment stack pointer Decrement stack pointer INPUT/OUTPUT INSTRUCTION CODE D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPERATIONS DESCRIPTION Return on no zero Return on positive Return on minus Return on parity even Return on parity odd MOVE, LOAD, AND STORE INCREMENT AND DECREMENT STACK OPS PUSH B PUSH D PUSH H PUSH PSW CZ CNZ CP CM CPE CPO RETURN RET RC RNC RZ 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 8 HS-80C85RH TABLE 4. INSTRUCTION SET SUMMARY (Continued) MNEMONIC JM JPE JPO PCHL CALL CALL CC CNC LOGICAL ANA r XRA r ORA r CMP r ANA M XRA M ORA M CMP M ANI XRI ORl CPl ROTATE RLC RRC RAL RAR INX H DCX B DCX D DCX H ADD ADD r ADC r 1 1 0 0 0 0 0 0 0 1 S S S S S Add register to A S Add register to A with carry 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Increment H & L registers Decrement B & C Decrement D & E Decrement H & L 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 S S S S 1 1 1 1 1 1 1 1 S S S S 1 1 1 1 1 1 1 1 S And register with A S Exclusive OR register with A S OR register with A S Compare register with A 0 0 0 0 0 0 0 0 And memory with A Exclusive OR memory with A OR memory with A Compare memory with A And immediate with A Exclusive OR immediate with A OR immediate with A Compare immediate with A SUBTRACT SUB r SBB r SUB M SBB M SUl SBl 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 S S 1 1 1 1 S S 1 1 1 1 S Subtract register from A S Subtract register from A with borrow 0 0 0 0 Subtract memory from A Subtract memory from A with borrow Subtract immediate from A Subtract immediate from A with borrow Complement A Set carry Complement carry Decimal adjust A Enable Interrupts Disable Interrupt No-operation Halt Read Interrupt Mask Set Interrupt Mask 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 Call unconditional Call on carry Call on no carry INSTRUCTION CODE D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 1 OPERATIONS DESCRIPTION Jump on minus Jump on parity even Jump on parity odd H & L to program counter TABLE 4. INSTRUCTION SET SUMMARY (Continued) MNEMONIC ADD M ADC M ADl ACl DAD B DAD D DAD H DAD SP INSTRUCTION CODE D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 C 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 OPERATIONS DESCRIPTION Add memory to A Add memory to A with carry Add immediate to A Add immediate to A with carry Add B & C to H & L Add D & E to H & L Add H & L to H & L Add stack pointer to H & L SPECIALS CMA STC CMC DAA CONTROL El DI NOP HLT RIM SlM NOTES: 4. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111 5. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags. 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 † All mnemonics copyrighted, Intel Corporation 1976 9 HS-80C85RH Functional Description The HS-80C85RH is a complete 8-bit parallel central processing unit implemented in a self aligned, silicon gate, CMOS technology. Its static design allows the device to be operated at any external clock frequency from a maximum of 4MHz down to DC. The processor clock can be stopped in either the high or low state and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The device is designed to fit into a minimum system of three ICs: CPU (HS-80C85RH), RAM/IO (HS-81C55/56RH) and ROM/IO Chip (HS-83C55RH). Since the HS-80C85RH is implemented in CMOS, all of the advantages of CMOS technology are inherent in the device. These advantages include low standby and operating power, high noise immunity, moderately high speed, wide operating temperature range, and designed-in radiation hardness. Thus the HS-80C85RH is ideal for weapons and space applications. The HS-80C85RH has twelve addressable 8-bit registers. Four of them can function only as two 16-bit register pairs. Six others can be used interchangeably as 8-bit registers or as 16-bit register pairs. The HS-80C85RH register set is as follows: MNEMONIC ACC or A PC BC, DE, HL REGISTER Accumulator Program Counter General-Purpose Registers; Data Pointer (HL) Stack Pointer Flag Register CONTENTS 8 bits 16-bit Address 8 bits x 6 or 16 bits x 3 16-bit Address 5 Flags (8-bit space) Interrupt and Serial I/O The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP INTR is maskable (can be enabled or disabled by El or Dl software instructions), and causes the CPU to fetch in an RST instruction, externally placed on the data bus, which vectors a branch to any one of eight fixed memory locations (Restart addresses). The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used to store the first instruction(s) of a routine designed to service the requirements of an interrupting device. Since the (RST) is a call, completion of the instruction also stores the old program counter contents on the STACK. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 9.) There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level-sensitive and are recognized with the same timing as INTR. RST 7.5 is rising edge sensitive. For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request (a normally high level signal with a low going pulse is recommended for highest system noise immunity). The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using the SlM instruction or by issuing a RESET IN to the 80C85RH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out. The status of the three RST interrupt masks can only be affected by the SIM instruction and RESET IN. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 8 illustrates SP Flags or F The HS-80C85RH uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data bus. These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for memory or I/O data. The HS-80C85RH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. HOLD and all Interrupts are synchronized with the processor’s internal clock. The HS-80C85RH also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for simple serial interface. In addition to these features, the HS-80C85RH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt, and a bus vectored interrupt, INTR. 10 HS-80C85RH the TRAP interrupt request circuitry within the HS-80C85RH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables all future interrupts (except TRAPs) until an EI instruction is executed. EXTERNAL INSIDE THE 80C85RH TRAP INTERRUPT TRAP REQUEST RESET IN TRAP SCHMITT TRIGGER RESET VDD D CLK Q D F/F CLEAR INTERRUPT REQUEST 1. A 20pF capacitor should be connected from X2 to ground to assure oscillator start-up at the correct frequency. 2. A 10MΩ resistor is required between X1 and X2 for bias point stabilization. In addition, the crystal should have the following characteristics: 1) Parallel resonance at twice the desired internal clock frequency 2) CL (load capacitance) ≤ 30pF 3) CS (shunt capacitance) ≤ 7pF 4) RS (equivalent shunt resistance) ≤ 75Ω 5) Drive level: 10mW 6) Frequency tolerance: ±0.005% (suggested) A parallel-resonant LC circuit may be used as the frequencydetermining network for the HS-80C85RH, providing that its frequency tolerance of approximately ±10% is acceptable. The components are chosen from the formula: 1 f = --------------------------------------------------2 π L ( Cext + Cint ) TRAP F.F. INTERNAL TRAP ACKNOWLEDGE FIGURE 8. TRAP AND RESET IN CIRCUIT The TRAP interrupt is special in that is disables interrupts, but preserves the previous interrupt enable status. Perform- ing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR, or RST 5.5-7.5 will provide current interrupt enable status, revealing that interrupts are disabled. The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data. To minimize variations in frequency, it is recommended that you choose a value for Cext that is at least twice that of Cint, or 30pF. The use of an LC circuit is not recommended for frequencies higher than approximately 4MHz. An RC circuit may be used as the frequency-determining network for the HS-80C85RH if maintaining a precise clock frequency is of no importance. Variations in the on-chip timing generation can cause a wide variation in frequency when using the RC mode. Its advantage is its low component cost. The driving frequency generated by the circuit shown is approximately 3MHz. It is not recommended that frequencies greatly higher or lower than this be attempted. Figure 9 shows the recommended clock driver circuits. For driving frequencies up to and including 4MHz you may supply the driving signal to X1 and leave X2 open-circuited (Figure 9D). X1 20pF 1 -6K 2 X2 80C85RH Driving the X1 and X2 Inputs You may drive the clock inputs of the HS-80C85RH with a crystal, an LC tuned circuit, an RC network, or an external clock source. The driving frequency may be any value from DC to 4MHz and must be twice the desired internal clock frequency. The following guidelines should be observed when a crystal is used to drive the HS-80C85RH clock input: X1 1 REXT = 10MΩ 2 CINT = 15pF X2 80C85RH 20pF FIGURE 9A. QUARTZ CRYSTAL CLOCK DRIVER 80C85RH FIGURE 9B. RC CIRCUIT CLOCK DRIVER LOW TIME > 60ns X1 X1 1 LEXT CEXT 2 X2 CINT = 15pF (NOTE) X2 NOTE: X2 Left Floating. FIGURE 9C. LC TUNED CIRCUIT CLOCK DRIVER FIGURE 9D. 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK DRIVER CIRCUIT FIGURE 9. CLOCK DRIVER CIRCUITS 11 HS-80C85RH HS-80C85RH Caveats 1. An important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule also applies to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of regenerative latches on the following HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M. Figure 10 depicts an output and corresponding regenerative latch. When the output driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-state condition. A transient drive current of approximately ±1.0mA at 0.5VDD for 10ns is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions. 2. The RD and WR pins of the HS-80C85RH contain internal dynamic pull-up transistors to avoid spurious selection of memory devices when the RD and WR pins assume the high impedance state. This eliminates the need for external resistive pull-ups on these pins. 3. The RESET IN and X1 inputs on the HS-80C85RH are schmit trigger inputs. This eliminates the possibility of internal oscillations in response to slow rise time input signals at these pins. 4. A high frequency bypass capacitor of approximately 0.1µF should be connected between VDD and GND to shunt power supply transients. 5. The HS-80C85RH is functional within 10 input clock cycles after application of power (assuming that reset has been asserted from power-on). Start up conditions in the crystal controlled oscillator mode must also account for the characteristics of the oscillator. Generating An HS-80C85RH Wait State If your system requirements are such that slow memories or peripheral devices are being used, the circuit shown in Figure 11 may be used to insert one WAIT state in each HS-80C85RH machine cycle. The D flip-flops should be chosen so that: 1. CLK is rising edge-triggered 2. CLEAR is low-level active The READY line is used to extend the read and write pulse lengths so that the 80C85RH can be used with slow memory. HOLD causes the CPU to relinquish the bus when it is through with it by floating the Address and Data Buses. 80C85RH CLK OUTPUT Q TO 80C85RH READY INPUT Q ALE (NOTE) VDD CLEAR CLK “D” F/F D CLK D “D” F/F NOTE: ALE and CLK (OUT) should be buffered if CLK input of latch exceeds 80C85RH IOL or IOH. FIGURE 11. GENERATION OF A WAIT STATE FOR HS-80C85RH CPU System Interface The HS-80C85RH family includes memory components, which are directly compatible to the HS-8OC8SRH CPU. For example, a system consisting of the three radiationhardened chips, HS-80C85RH, HS-81C56RH, and HS-83C55RH will have the following features: 1. 2K Bytes ROM 2. 256 Bytes RAM 3. 1 Timer/Counter OUTPUT DRIVER REGENERATIVE LATCH OUTPUT PIN 4. 4 8-bit I/O Ports 5. 1 6-bit I/O Port 6. 4 Interrupt Levels 7. Serial In/Serial Out Ports This minimum system, using the standard I/O technique is as shown in Figure 12. In addition to standard 1/0, the memory mapped I/O offers an efficient I/O addressing technique. With this technique, an area of memory address space is assigned for I/O address, thereby, using the memory address for I/O manipulation. Figure 13 shows the system configuration of Memory Mapped I/O using HS-80C85RH. The HS-80C85RH CPU can also interface with the standard radiation-hardened memory that does not have the multiplexed address/data bus. It will require use of the HS-82C12RH (8-bit latch) as shown in Figure 14. FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS AD0-AD7, A8-A15 AND IO/M 12 HS-80C85RH VSS VDD RESET IN X1 X2 TRAP HOLD RST 7.5 HLDA RST 6.5 SOD HS-80C85RH RST 5.5 SID INTR S1 RESET S0 INTA ADDR/ OUT ADDR DATA ALE RD WR IO/M RDY CLK (8) (8) VSS VDD CE WR RD ALE DATA/ ADDR IO/M RESET IOW RD ALE CE A0-10 PORT A HS-81C56RH PORT B PORT C IN TIMER OUT (8) (8) (6) DATA/ ADDR PORT IO/M B RESET RDY (NOTE) IOR CLK VSS VDD HS-83C55RH PORT A (8) (8) VDD VDD NOTE: Optional connection. FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O TECHNIQUE) A8-15 AD0-7 ALE HS-80C85RH RD WR IO/M CLK RESET OUT READY (NOTE) RDY RESET TIMER (NOTE) IN WR RD ALE CE AD0-7 IO/M IOW A8-10 AD0-7 IO/M CLK RST ALE RD CE VDD TIMER OUT HS-81C56RH (RAM + I/O + COUNTER/TIMER) (6) (8) (8) HS-83C55RH (ROM +I/O) (8) (8) NOTE: Optional connection. FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O) 13 HS-80C85RH VSS VDD TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA ADDR (8) X1 HOLD HLDA SOD HS-80C85RH SID S1 RESET S0 ADDR/ DATA ALE RD WR IO/M OUT RDY CLK (8) IO/M (CS) WR RD STANDARD MEMORY DATA X2 RESET IN HS-82C12RH ADDR (CS) CLK RESET (16) IO/M (CS) WR RD I/O PORTS, CONTROLS DATA STANDARD I/O ADDR VDD VDD VDD FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES) 14 HS-80C85RH Basic System Timing The HS-80C85RH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 15 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address. There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (lO/M, S1, S0) and the three control signals (RD, WR, and INTA). (See Table 10.) The status lines can be used as advanced controls (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR are used as command lines since they become active when the transfer of data is to take place. TABLE 5. HS-80C85RH MACHINE CYCLE CHART STATUS MACHINE CYCLE Opcode Fetch (OF) Memory Read (MR) Memory Write (MW) I/O Read I/O Write (IOR) (IOW) 0 0 0 1 1 1 DAD Ack. of RST, TRAP HALT 0 1 TS 1 1 0 1 0 1 1 1 0 M1 CLK T1 T2 T3 T4 T1 A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 11. TABLE 6. HS-80C85RH MACHINE STATE CHART STATUS AND BUSES CONTROL MACHINE STATE S1, S0 IO/M A8-15 AD0-7 RD, WR INTA ALE T1 T2 TWAIT T3 T4 T5 T6 TRESET THALT THOLD 0 = Logic “0” 1 = Logic “1” instruction. X X X X 1 1 1 X 0 X X X X X 0†† 0†† 0†† TS TS TS X X X X X X X TS TS TS X X X X TS TS TS TS TS TS 1 X X X 1 1 1 TS TS TS 1 X X X 1 1 1 1 1 1 1† 0 0 0 0 0 0 0 0 0 CONTROL 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 M2 T2 IO/M S1 S0 RD WR INTA TS = High Impedance X = Unspecified † ALE not generated during 2nd and 3rd machine cycles of DAD †† IO/M = 1 during T4, T6 of INA machine cycle. Acknowledge (INA) of INTR Bus Idle (BI) TS TS M3 T3 T1 T2 T3 T A8-A15 PCH (HIGH ORDER ADDRESS) (PC + 1)H IO PORT AD0-7 PCL (LOW ORDER ADDRESS) DATA FROM MEMORY (INSTRUCTION) (PC+1)L DATA TO MEMORY OR PERIPHERAL IO PORT DATA FROM MEMORY (I/O PORT ADDRESS) ALE RD WR IO/M STATUS S1-S0 (FETCH) 10 (READ) 01 WRITE 11 FIGURE 15. 80C85RH BASIC SYSTEM TIMING 15 HS-80C85RH Die Characteristics DIE DIMENSIONS: 229 mils x 240 mils x 14 mils ±1 mil INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kÅ ±1kÅ Top Metallization: Type: SiAl Thickness: 11kÅ ±2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) Metallization Mask Layout (3) RESET OUT HS-80C85RH (37) CLOCK OUT (36) RESET IN (35) READY (34) IO/M (33) S1 (32) RD (31) WR (30) ALE (29) S0 (28) A15 (27) A14 (26) A13 (25) A12 A11 (24) (39) HOLD TRAP (6) RST 7.5 (7) RST 6.5 (8) RST 5.5 (9) INTR (10) INTA (11) AD0 (12) AD1 (13) AD2 (14) AD3 (15) AD4 (16) GND (20) AD5 (17) AD6 (18) AD7 (19) A10 (23) A8 (21) A9 (22) 16 (38) HLDA (40) VDD (4) SOD (5) SID (2) X2 (1) X1