5962R9676601QXC

HS-81C55RH, HS-81C56RH TM Data Sheet August 2000 File Number 3039.2 Radiation Hardened 256 x 8 CMOS RAM The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened SelfAligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-96766. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.asp Features • Electrically Screened to SMD # 5962-96766 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened EPI-CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . .>1 x 108 rad(Si)/s - Latch-Up Free . . . . . . . . . . . . . . . . . . >1 x 1012 rad(Si)/s • Electrically Equivalent to Sandia SA 3001 • Pin Compatible with Intel 8155/56 • Bus Compatible with HS-80C85RH • Single 5V Power Supply • Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max • Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz • Completely Static Design • Internal Address Latches • Two Programmable 8-Bit I/O Ports • One Programmable 6-Bit I/O Port • Programmable 14-Bit Binary Counter/Timer • Multiplexed Address and Data Bus • Self Aligned Junction Isolated (SAJI) Process • Military Temperature Range . . . . . . . . . . . -55oC to 125oC Ordering Information ORDERING NUMBER 5962R9676601QXC 5962R9676601QYC 5962R9676601VXC 5962R9676601VYC 5962R9676602QXC 5962R9676602QYC 5962R9676602VXC 5962R9676602VYC INTERNAL MKT. NUMBER HS1-81C55RH-8 HS9-81C55RH-8 HS1-81C55RH-Q HS9-81C55RH-Q HS1-81C56RH-8 HS9-81C56RH-8 HS1-81C56RH-Q HS9-81C56RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 Functional Diagram IO/M AD0 - AD7 CE OR CE † ALE RD WR RESET TIMER CLK TIMER OUT TIMER C PORT C 8 PC0 - PC5 VDD (10V) GND 256 x 8 STATIC RAM A PORT A 8 PA0 - PA7 PORT B B 8 PB0 - PB7 † 81C55RH = CE 81C56RH = CE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-81C55RH, HS-81C56RH Pinouts 40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW PC3 PC4 TIMER IN RESET PC5 TIMER OUT IO / M CE or CE† 1 2 3 4 5 6 7 8 40 VDD 39 PC2 38 PC1 37 PC0 36 PB7 35 PB6 34 PB5 33 PB4 32 PB3 31 PB2 30 PB1 29 PB0 28 PA7 27 PA6 26 PA5 25 PA4 24 PA3 23 PA2 22 PA1 21 PA0 PC3 PC4 TIMER IN RESET PC5 TIMER OUT IO/M CE OR CE RD WR ALE AD0 AD1 AD2 AD3 NC AD4 AD5 AD6 AD7 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 NC PA4 PA3 PA2 PA1 PA0 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INTERSIL OUTLINE K42.A TOP VIEW RD 9 WR 10 ALE 11 AD0 12 AD1 13 AD2 14 AD3 15 AD4 16 AD5 17 AD6 18 AD7 19 GND 20 † 81C55RH = CE 81C56RH = CE 2 HS-81C55RH, HS-81C56RH Pin Descriptions SYMBOL RESET TYPE I NAME AND FUNCTION Reset: Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT). Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET pulse should typically be two HS-80C85RH clock cycle times. Address/Data: Three-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of ALE. The address can be either for the memory section or the I/O section depending on the IO/M input. The 8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal. Chip Enable: On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE and is ACTIVE HIGH. Read Control: Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/M pin is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or command/status registers will be read to the AD bus. Write Control: Input low on this line with the Chip Enable active causes the data on the Address/Data bus to be written to the RAM or I/O ports and command/status register, depending on IO/M. Address Latch Enable: This control signal latches both the address on the AD0 - AD7 lines and the state of the Chip Enable and IO/M into the chip at the falling edge of ALE. I/O Memory: Selects memory if low and I/O and command/status registers if high. Port A: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. Port B: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. Port C: These 6 pins can function as either input port, output port, or as control signals for PA and PB. Programming is done through the command register. When PC0 - PC5 are used as control signals, they will provide the following: PC0 - A INTR (Port A Interrupt) PC1 - ABF (Port A Buffer Full) PC2 - A STB (Port A Strobe) PC3 - B INTR (Port B Interrupt) PC4 - B BF (Port B Buffer Full) PC5 - B STB (Port B Strobe) Timer Input: Input to the counter-timer. Timer Output: This output can be either a square wave or a pulse, depending on the timer mode. Voltage: +5V. Ground: Ground reference. AD0 - AD7 I/O CE or CE RD I I WR ALE IO/M PA0 - PA7 (8) PB0 - PB7 (8) PC0 - PC7 (8) I I I I/O I/O I/O TIMER IN TIMER OUT VDD GND I O I I 3 HS-81C55RH, HS-81C56RH Waveforms READ CE (81C55RH) OR CE (81C56RH) IO/M tAD AD0-7 tAL ALE tLL RD tLC tCC tRV tRIDE tRD tCL tRDF ADDRESS tLA DATA VALID WRITE CE (81C55RH) OR CE (81C56RH) IO/M AD0-7 tAL ALE tLL WR ADDRESS tLA tDW DATA VALID tCL tLC tCL tCC tWD tRV 4 HS-81C55RH, HS-81C56RH Waveforms (Continued) STROBED INPUT BF tSBF STROBED tSS INTR tRDI tSI tRBE RD tPSS INPUT DATA FROM PORT tPHS STROBED OUTPUT BF tSBE STROBE tWBF INTR tWI WR tWP OUTPUT DATA TO PORT tSI 5 HS-81C55RH, HS-81C56RH Waveforms (Continued) BASIC INPUT tRP RD tPR INPUT BASIC INPUT RD tWP INPUT DATA BUS DATA BUS TIMER OUTPUT COUNTDOWN FROM 5 TO 1 LOAD COUNTER CLR 2 1 tF 5 4 t2 3 RELOAD COUNTER CLR 2 1 5 TIMER IN tR TIMER OUT (PULSE) (NOTE 1) tTL TIMER OUT (SQUARE WAVE) (NOTE 1) tTL NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC RELOAD MODE (M, MODE BIT = 1) tTH tTH t1 tCYC Functional Description The HS-81C55RH and 81C56RH contains the following: • 2K Bit Static RAM Organized as 256 x 8 • Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port (PC) • 14-Bit Timer-Counter The IO/M (IO/Memory Select) pin selects either the five register (Command, Status, PA0 - PA7, PB0 - PB7, PC0 PC5) or the memory (RAM) portion. The 8-bit address on the Address/Data lines, Chip Enable input CE or CE and IO/M are all latched on-chip at the falling edge of ALE. 8-BIT INTERNAL DATA BUS COMMAND STATUS PC PB PA TIMER MSB TIMER LSB 6 8 8 TIMER MODE FIGURE 1. INTERNAL REGISTERS 6 HS-81C55RH, HS-81C56RH Reading the Status Register CE (81C55RH) OR CE (81C56RH) The status register consists of seven latches, one for each bit six (0-5) for the status of the ports and one (6) for the status of the timer. The status of the timer and the I/O section can be polled by reading the Status Register (Address XXXXX000). Status word format is shown in Figure 4. Note that you may never write to the status register since the command register shares the same I/O address and the command register is selected when a write to that address is issued. AD7 AD6 AD5 AD4 B BF AD3 AD2 AD1 A BF AD0 INTR A PORT A INTERRUPT REQUEST PORT A BUFFER FULL/EMPTY (INPUT/OUTPUT) PORT A INTERRUPT ENABLE PORT B INTERRUPT REQUEST PORT B BUFFER FULL/EMPTY (INPUT/OUTPUT) PORT B INTERRUPT ENABLE TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED, AND IS RESET TO LOW READING OF THE C/S REGISTER & BY HARDWARE RESET). IO/M AD0 - AD7 ALE ADDRESS DATA VALID RD OR WR FIGURE 2. ON-BOARD MEMORY READ/WRITE CYCLE INTE TIMER B INTR INTE B A Programming of the Command Register The command register consists of eight latches. Four bits (03) define the mode of the ports, two bit (4-5) enable or disable the interrupt from port C when it acts as control port, and the last two bits (6-7) are for the timer. The command register contents can be altered at anytime by using the I/O address XXXXX000 during a WRITE operation with the Chip Enable active and IO/M = 1. The meaning of each bit of the command byte is defined in Figure 3. The contents of the command register may never be read. 7 6 5 4 3 2 1 0 PA FIGURE 4. STATUS REGISTER BIT ASSIGNMENT Input/Output Section The I/O section of the HS-81C55RH and HS-81C56RH consists of five registers: (See Figure 5) DEFINES PA0 - PA7 DEFINES PB0 - PB7 DEFINES PC0 - PC5 0 = INPUT 1 = OUTPUT 00 = ALT1 11 = ALT2 01 = ALT3 10 = ALT4 0 = INPUT 1 = OUTPUT TM2 TM1 IEB IEA PC2 PC1 PB • Command/Status Register (C/S) - Both register are assigned the address XXXXX000. The C/S address serves the dual purpose. When the C/S registers are selected during WRITE operation, a command is written into the command register. The contents of this register are not accessible through the pins. When the C/S (XXXXX000) is selected during a READ operation, the status information of the I/O ports and the timer becomes available on the AD0 - AD7 lines. • PA Register - This register can be programmed to be either input or output ports depending on the status of the contents of the C/S Register. also depending on the command, this port can operate in either the basic mode or the strobed mode (See timing diagram). the I/O pins assigned in relation to this register are PA0 PA7. The address of this register is XXXXX001. • PB Register - This register functions the same as PA Register. the I/O pins assigned are PB0 - PB7. The address of this register is XXXXX010 • PC Register - This register has the address XXXXX011 and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as ENABLE PORT A INTERRUPT ENABLE PORT B INTERRUPT 00 = NOP - DO NOT AFFECT COUNTER OPERATION 01 = STOP - NOP IF TIMER HAS NOT STARTED; STOP COUNTING IF THE TIMER IS RUNNING 10 = STOP AFTER TC - STOP IMMEDIATELY AFTER PRESENT TC IS REACHED (NOP IF TIMER HAS NOT STARTED) 11 = START - LOAD MODE AND CNT LENGTH AND START IMMEDIATELY AFTER LOADING (IF TIMER IS NOT PRESENTLY RUNNING). IF TIMER IS RUNNING, START THE NEW MODE AND CNT LENGTH IMMEDIATELY AFTER PRESENT TC IS REACHED. TIMER COMMAND FIGURE 3. COMMAND REGISTER BIT ASSIGNMENT 7 HS-81C55RH, HS-81C56RH control signals for PA and PB by properly programming the AD2 and AD3 bits of the C/S register. When PC0 - PC5 is used as a control port, 3 bits are assigned for Port A and 3 for Port B. The first bit is an Interrupt that the HS-81C55RH and HS-81C56RH sends out. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. (See Table 1). When the ‘C’ port is programmed to either ALT3 or ALT4, the control signals for PA and PB are initialized as follows: CONTROL BF INTR STB INPUT MODE Low Low Input Control OUTPUT MODE Low High Input Control When in the ALT1 or ALT2 modes, the bits of Port C are structured like the diagram above in the simple input or output mode, respectively. Reading from an input port with nothing connected to the pins will provide unpredictable results. I/O ADDRESS† A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 SELECTION Interval Command/ Status Register General Purpose I/O Port A General Purpose I/O Port B General Purpose I/O or Control Port C Low-Order 8 Bits of Timer Count High 6 Bits of Timer Count and 2 Bits of Timer Mode † I/O Address must be qualified by CE = 1(81C56RH) or CE = 0(81C55RH) and IO/M = 1 in order to select the appropriate register. X = Don’t Care FIGURE 5. I/O PORT AND TIMER ADDRESSING SCHEME Figure 6 shows how I/O Ports A and B are structured within the HS-81C55RH and HS-81C56RH. Note in the diagram that when the I/O ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation when appropriately addressed. The outputs of the HS-81C55/56RH are “glitch-free” meaning that you can write a “1” to a bit position that was previously “1” and the level at the output pin will not change. Note also that the output latch is cleared when the port enters the input mode. the output latch cannot be loaded by writing to the port if the port is in the input mode. The result is that each time a port mode is changed from input to output, the output pins will go low. When the HS81C55/56RH is RESET, the output latches are all cleared and all 3 ports enter the input mode. 8 HS-81C55RH, HS-81C56RH HS-81C55RH AND HS-81C56RH ONE BIT OF PORT A OR PORT B OUTPUT LATCH CLK INTERNAL DATA BUS CLR (1) (2) (3) (4) OUTPUT MODE MULTIPLEXER SIMPLE INPUT CONTROL STROBED INPUT = 1 FOR OUTPUT MODE = 0 FOR INPUT MODE D Q PA/PB PIN WRITE PORT MUX (1) (2) (3) MODE (4) LATCH READ PORT Q CLK D NOTES: 1. READ Port = (IO/M = 1)(RD = 0)(CE Active) (Port Address Selected) 2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active) (Port Address Selected) STB FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION Figure 7 shows how the HS-81C55/56RH I/O ports might be configured in a typical system. PORT A OUTPUT PORT A TO HS-80C85RH RST INPUT Timer Section The timer is a 14-bit down counter that counts the TIMER IN pulses and provides either a square wave or pulse when terminal count (TC) is reached. The timer has the I/O address XXXXX100 for the low order byte of the register and the I/O address XXXXX101 for the high order byte of the register. (See Figure 5). To program the timer, the COUNT LENGTH REG is loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 of the high order count register will specify the length of the next count and bits 14-15 of the high order register will specify the timer output mode (see Figure 8). The value loaded into the count length register can have any value from 2H through 3FFH in Bits 0-13. PORT C A INTR (SIGNAL DATA RECEIVED) A BF (SIGNALS DATA READY) A STB (ACKNOWL. DATA RCV’D) B STB (LOAD PORT B LATCH) B BF (SIGNALS BUFFER IS FULL) B INTR (SIGNALS BUFFER READY FOR READING) PORT B INPUT TO INPUT PORT (OPTIONAL) TO HS-80C85RH RST INPUT TO/FROM PERIPHERAL INTERFACE FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001 7 M2 6 M1 5 T13 4 T12 3 T11 2 T10 1 T9 0 T8 TIMER MODE 7 T7 6 T6 5 T5 4 T4 MSB OF CNT LENGTH 3 T3 2 T2 1 T1 0 T0 LSB OF CNT LENGTH FIGURE 8. TIMER FORMAT There are four modes to choose from: M2 and M1 define the timer mode, as shown in Figure 9. 9 HS-81C55RH, HS-81C56RH TIMER OUT WAVEFORMS: MODE BITS M2 M1 0 0 1. SINGLE SQ. WAVE 2. CONTINUOUS SQ. WAVE 3. SINGLE PULSE ON TERM. COUNT 4. CONTINUOUS PULSES START TERMINAL COUNT COUNT (TERMINAL COUNT) 0 1 1 0 1 1 FIGURE 9. TIMER MODES Bits 6-7 (TM2 and TM1) of command register contents are used to start and stop the counter. there are four commands to choose from: TM2 0 0 1 TM1 0 1 0 NOP - Do not affect counter operation STOP-NOP - If timer has not started; stop counting if the timer is running STOP AFTER TC - Stop immediately after present TC is reached (NOP if timer has not started) START - Load mode and CNT length and start immediately after loading (if timer is not presently running). If timer is running, start the new mode and CNT length immediately after present TC is reached. Please note that the timer circuit on the HS-81C55/56RH chip is designed to be a square-wave timer, not an event counter. To achieve this, it counts down by twos twice in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN pulses received. You cannot load an initial value of 1 into the count register and cause the timer to operate, as its terminal count value is 10 (binary) or 2 (decimal). (For the detection of single pulses, it is suggested that one of the hardware interrupt pins on the HS-80C85RH be used.) After the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining count, perform the following operations in order: 1. Stop the count 2. Read in the 16-bit value from the count length registers 3. Reset the upper two mode bits 4. Reset the carry and rotate right one position all 16 bits through carry 5. If carry is set, add 1/2 of the full original count (1/2 full count - 1 if full count is odd). NOTE: If you started with an odd count and you read the count length register before the third count pulse occurs, you will not be able to discern whether one or two counts has occurred. Regardless of this, the HS-81C55/56RH always counts out the right number of pulses in generating the TIMER OUT waveforms. 1 1 Note that while the counter is counting, you may load a new count and mode into the count length registers. Before the new count and mode will be used by the counter, you must issue a START command to the counter. This applies even thought you may only want to change the count and use the previous mode. In case of an odd-numbered count, the first half-cycle of the squarewave output, which is high, is one count longer than the second (low) half-cycle, as shown in Figure 10. 4 5 FIGURE 10. ASYMMETRICAL SQUARE-WAVE OUTPUT RESULTING FROM COUNT OF 9 The counter in the HS-81C55/56RH is not initialized to any particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore, counting cannot begin following RESET until a START command is issued via the C/S register. 10 HS-81C55RH, HS-81C56RH Die Characteristics DIE DIMENSIONS: 222mils x 202mils x 14mils ± 1mil (Die Thickness) INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kÅ ± 1kÅ Top Metallization: Type: AlSi Thickness: 11kÅ ± 2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) Metallization Mask Layout HS-81C55RH, HS-81C56RH (3) TIMER IN (4) RESET (40) VDD (39) PC2 (38) PC1 (37) PC0 (36) PB7 TIMER OUT (6) IO/M (7) (34) PB5 CE OR CE (8) RD (9) WR (10) ALE (11) (35)PB6 (33) PB4 (32) PB3 (31) PB2 (30) PB1 (29) PB0 (28) PA7 (27) PA6 PA5 (26) (5) PC5 (2) PC4 AD0 (12) AD1 (13) AD2 (14) AD3 (15) AD4 (16) AD5 (17) AD6 (18) AD7 (19) (1) PC3 GND (20) PA0 (21) PA1 (22) PA2 (23) PA3 (24) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 11 PA4 (25)