7612BCPA

® ICL7611, ICL7612 Data Sheet September 27, 2006 FN2919.8 1.4MHz, Low Power CMOS Operational Amplifiers The ICL761X series is a family of CMOS operational amplifiers. These devices provide the designer with high performance operation at low supply voltages and selectable quiescent currents, and are an ideal design tool when ultra low input current and low power dissipation are desired. The basic amplifier will operate at supply voltages ranging from ±1V to ±8V, and may be operated from a single Lithium cell. A unique quiescent current programming pin allows setting of standby current to 1mA, 100μA, or 10μA, with no external components. This results in power consumption as low as 20μW. The output swing ranges to within a few millivolts of the supply voltages. Of particular significance is the extremely low (1pA) input current, input noise current of 0.01pA/√Hz, and 1012Ω input impedance. These features optimize performance in very high source impedance applications. The inputs are internally protected. Outputs are fully protected against short circuits to ground or to either supply. AC performance is excellent, with a slew rate of 1.6V/μs, and unity gain bandwidth of 1MHz at IQ = 1mA. Because of the low power dissipation, junction temperature rise and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages. Features • Wide Operating Voltage Range . . . . . . . . . . . ±1V to ±8V • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1012Ω • Programmable Power Consumption . . . . . Low as 20μW • Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ) • Output Voltage Swing . . . . . . . . . . . . . . . . . . . V+ and V• Input Common Mode Voltage Range Greater Than Supply Rails (ICL7612) • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Portable Instruments • Telephone Headsets • Hearing Aid/Microphone Amplifiers • Meter Amplifiers • Medical Instruments • High Impedance Buffers Pinouts ICL7611, ICL7612 (PDIP, SOIC) TOP VIEW BAL -IN +IN V1 2 3 4 + 8 IQ SET V+ OUT BAL - 7 6 5 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7611, ICL7612 Ordering Information PART NUMBER ICL7611DCBA ICL7611DCBAZ (Note) ICL7611DCBA-T ICL7611DCBAZ-T (Note) ICL7611DCPA ICL7611DCPAZ (Note) ICL7612BCPA ICL7612DCBA ICL7612DCBAZ (Note) ICL7612DCBA-T ICL7612DCBAZ-T (Note) ICL7612DCPA ICL7612DCPAZ (Note) PART MARKING 7611DCBA 7611DCBAZ 7611DCBA 7611DCBAZ 7611DCPA 7611DCPAZ 7612BCPA 7612DCBA 7612DCBAZ 7612DCBA 7612DCBAZ 7612DCPA 7612DCPAZ TEMP. RANGE (°C) 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) PACKAGE PKG. DWG. # M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN2919.8 September 27, 2006 ICL7611, ICL7612 Absolute Maximum Ratings Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V Differential Input Voltage (Note 1) . . . . . . . . [(V+ +0.3) - (V- -0.3)]V Duration of Output Short Circuit (Note 2). . . . . . . . . . . . . . Unlimited Thermal Information Thermal Resistance (Typical, Note 3) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICL761XC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time. 2. The outputs may be shorted to ground or to either supply, for VSUPPLY ≤10V. Care must be taken to insure that the dissipation rating is not exceeded. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Offset Voltage VSUPPLY = ±5V, Unless Otherwise Specified TEST CONDITIONS RS ≤ 100kΩ RS ≤ 100kΩ ICL7612B TEMP (°C) +25 Full MIN ±5.3 +5.3, -5.1 +5.3, -4.5 ±4.9 ±4.8 ±4.9 ±4.8 ±4.5 ±4.3 80 75 80 75 76 72 TYP 15 0.5 1.0 104 102 83 MAX 5 7 30 300 50 400 ICL7611D, ICL7612D MIN ±4.4 ±4.2 ±3.7 ±5.3 +5.3, -5.1 +5.3, -4.5 ±4.9 ±4.8 ±4.9 ±4.8 ±4.5 ±4.3 80 75 80 75 76 72 TYP 25 0.5 1.0 104 102 83 MAX 15 20 30 300 50 400 UNITS mV mV μV/°C pA pA pA pA V V V V V V V V V V V V dB dB dB dB dB dB SYMBOL VOS ΔVOS/ΔT IOS Temperature Coefficient of VOS Input Offset Current +25 Full Input Bias Current IBIAS I Q = 1 0μ A IQ = 100μA IQ = 1mA I Q = 1 0μ A IQ = 100μA IQ = 1mA IQ = 10μA, RL = 1MΩ IQ = 100μA, RL = 100kΩ IQ = 1mA, RL = 10kΩ VO = ±4.0V, RL = 1MΩ, I Q = 1 0μ A VO = ±4.0V, RL = 100kΩ, IQ = 100μA VO = ±4.0V, RL = 10kΩ, IQ = 1mA +25 Full Common Mode Voltage Range (ICL7611 Only) Extended Common Mode Voltage Range (ICL7612 Only) Output Voltage Swing VCMR +25 +25 +25 +25 +25 +25 +25 Full +25 Full +25 Full VCMR VOUT Large Signal Voltage Gain AVOL +25 Full +25 Full +25 Full 3 FN2919.8 September 27, 2006 ICL7611, ICL7612 Electrical Specifications PARAMETER Unity Gain Bandwidth VSUPPLY = ±5V, Unless Otherwise Specified (Continued) TEST CONDITIONS I Q = 1 0μ A IQ = 100μA IQ = 1mA Input Resistance Common Mode Rejection Ratio RIN CMRR RS ≤ 100kΩ, IQ = 10μA RS ≤ 100kΩ, IQ = 100μA RS ≤ 100kΩ, IQ = 1mA Power Supply Rejection Ratio (VSUPPLY = ±8V to ±2V) Input Referred Noise Voltage Input Referred Noise Current Supply Current (No Signal, No Load) PSRR RS ≤ 100kΩ, IQ = 10μA RS ≤ 100kΩ, IQ = 100μA RS ≤ 100kΩ, IQ = 1mA eN iN ISUPPLY RS = 100Ω, f = 1kHz RS = 100Ω, f = 1kHz IQ SET = +5V, Low Bias IQ SET = 0V, Medium Bias IQ SET = -5V, High Bias Channel Separation Slew Rate (AV = 1, CL = 100pF, VIN = 8VP-P) Rise Time (VIN = 50mV, CL = 100pF) Overshoot Factor (VIN = 50mV, CL = 100pF) VO1/VO2 SR AV = 100 IQ = 10μA, RL = 1MΩ IQ = 100μA, RL = 100kΩ IQ = 1mA, RL = 10kΩ tr IQ = 10μA, RL = 1MΩ IQ = 100μA, RL = 100kΩ IQ = 1mA, RL = 10kΩ OS IQ = 10μA, RL = 1MΩ IQ = 100μA, RL = 100kΩ IQ = 1mA, RL = 10kΩ ICL7612B TEMP (°C) +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 MIN 70 70 60 80 80 70 TYP 0.044 0.48 1.4 1012 96 91 87 94 86 77 100 0.01 0.01 0.1 1.0 120 0.016 0.16 1.6 20 2 0.9 5 10 40 MAX 0.02 0.25 2.5 ICL7611D, ICL7612D MIN 70 70 60 80 80 70 TYP 0.044 0.48 1.4 1012 96 91 87 94 86 77 100 0.01 0.01 0.1 1.0 120 0.016 0.16 1.6 20 2 0.9 5 10 40 MAX 0.02 0.25 2.5 UNITS MHz MHz MHz Ω dB dB dB dB dB dB nV/√Hz pA/√Hz mA mA mA dB V/μs V/μs V/μs μs μs μs % % % SYMBOL GBW Electrical Specifications PARAMETER Input Offset Voltage VSUPPLY = ±1V, IQ = 10μA, Unless Otherwise Specified TEST CONDITIONS RS ≤ 100kΩ TEMP (°C) +25 Full ICL7612B MIN +0.6 to -1.1 ±0.98 ±0.96 TYP 15 0.5 1.0 MAX 5 7 30 300 50 500 UNITS mV mV μV/°C pA pA pA pA V V V SYMBOL VOS Temperature Coefficient of VOS Input Offset Current ΔVOS/ΔT RS ≤ 100kΩ IOS +25 Full Input Bias Current IBIAS +25 Full Extended Common Mode Voltage Range Output Voltage Swing VCMR VOUT RL = 1M Ω +25 +25 Full 4 FN2919.8 September 27, 2006 ICL7611, ICL7612 Electrical Specifications PARAMETER Large Signal Voltage Gain VSUPPLY = ±1V, IQ = 10μA, Unless Otherwise Specified (Continued) TEST CONDITIONS VO = ±0.1V, RL = 1MΩ TEMP (°C) +25 Full Unity Gain Bandwidth Input Resistance Common Mode Rejection Ratio Power Supply Rejection Ratio Input Referred Noise Voltage Input Referred Noise Current Supply Current Slew Rate Rise Time Overshoot Factor GBW RIN CMRR PSRR eN iN ISUPPLY SR tr OS RS ≤ 100kΩ RS ≤ 100kΩ RS = 100Ω , f = 1kHz RS = 100Ω , f = 1kHz No Signal, No Load AV = 1, CL = 100pF, VIN = 0.2VP-P, RL = 1MΩ VIN = 50mV, CL = 100pF RL = 1MΩ VIN = 50mV, CL = 100pF, RL = 1MΩ +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 ICL7612B MIN TYP 90 80 0.044 1012 80 80 100 0.01 6 0.016 20 5 MAX 15 UNITS dB dB MHz Ω dB dB nV/√Hz pA/√Hz μA V/μs μs % SYMBOL AVOL Schematic Diagram IQ INPUT STAGE SETTING STAGE OUTPUT STAGE V+ 3k BAL QP1 V+ +INPUT QN1 QN2 QP1 3k 900k QP5 BAL QP3 100k QP4 QP9 CFF = 9pF OUTPUT VV+ CC = 33pF QP6 QP7 QP8 6.3V -INPUT QN7 VQN3 QN4 QN5 QN8 VQN6 QN9 QN10 6.3V QN11 V+ IQ SET 5 FN2919.8 September 27, 2006 ICL7611, ICL7612 Application Information Static Protection All devices are static protected by the use of input diodes. However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction characteristics, which may result in increased input leakage currents. IQ = 10μA, nulling may not be possible with higher values of VOS . Frequency Compensation The ICL7611 and ICL7612 are internally compensated, and are stable for closed loop gains as low as unity with capacitive loads up to 100pF. Latchup Avoidance Junction-isolated CMOS circuits employ configurations which produce a parasitic 4-layer (PNPN) structure. The 4-layer structure has characteristics similar to an SCR, and under certain circumstances may be triggered into a low impedance state resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails may be applied to any pin. In general, the op amp supplies must be established simultaneously with, or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to 2mA to prevent latchup. Extended Common Mode Input Range The ICL7612 incorporates additional processing which allows the input CMVR to exceed each power supply rail by 0.1V for applications where VSUPP ≥ ±1.5V. For those applications where VSUPP ≤ ±1.5V the input CMVR is limited in the positive direction, but may exceed the negative supply rail by 0.1V in the negative direction (e.g., for VSUPPLY = ±1V, the input CMVR would be +0.6V to -1.1V). Operation At VSUPPLY = ±1V Operation at VSUPPLY = ±1V is guaranteed at IQ = 10μA for A and B grades only. Output swings to within a few millivolts of the supply rails are achievable for RL ≥ 1MΩ. Guaranteed input CMVR is ±0.6V minimum and typically +0.9V to -0.7V at VSUPPLY = ±1V. For applications where greater common mode range is desirable, refer to the description of ICL7612 above. Choosing the Proper IQ The ICL7611 and ICL7612 have a similar IQ set-up scheme, which allows the amplifier to be set to nominal quiescent currents of 10μA, 100μA or 1mA. These current settings change only very slightly over the entire supply voltage range. The ICL7611 and ICL7612 have an external IQ control terminal, permitting user selection of quiescent current. To set the IQ connect the IQ terminal as follows: IQ = 10μA - IQ pin to V+ IQ = 100μA - IQ pin to ground. If this is not possible, any voltage from V+ - 0.8 to V- +0.8 can be used. IQ = 1mA - IQ pin to VNOTE: The output current available is a function of the quiescent current setting. For maximum peak-to-peak output voltage swings into low impedance loads, IQ of 1mA should be selected. Typical Applications The user is cautioned that, due to extremely high input impedances, care must be exercised in layout, construction, board cleanliness, and supply filtering to avoid hum and noise pickup. Note that in no case is IQ shown. The value of IQ must be chosen by the designer with regard to frequency response and power dissipation. Output Stage and Load Driving Considerations Each amplifiers’ quiescent current flows primarily in the output stage. This is approximately 70% of the IQ settings. This allows output swings to almost the supply rails for output loads of 1MΩ, 100kΩ, and 10kΩ, using the output stage in a highly linear class A mode. In this mode, crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AB for higher output currents. (See graphs under Typical Operating Characteristics). During the transition from Class A to Class B operation, the output transfer characteristic is non-linear and the voltage gain decreases. VIN + ICL7612 - VOUT RL ≥10k FIGURE 1. SIMPLE FOLLOWER (NOTE 4) VIN 100k +5 + +5 VOUT TO CMOS OR LPTTL LOGIC ICL7612 Input Offset Nulling Offset nulling may be achieved by connecting a 25k pot between the BAL terminals with the wiper connected to V+. At quiescent currents of 1mA and 100μA the nulling range provided is adequate for all VOS selections; however with NOTE: 1M 4. By using the ICL7612 in this application, the circuit will follow rail to rail inputs. FIGURE 2. LEVEL DETECTOR (NOTE 4) 6 FN2919.8 September 27, 2006 ICL7611, ICL7612 1 μF + ICL7611 + 1M VOUT 1M ICL7611 + λ ICL7611 + 1M VV+ DUTY CYCLE 680kΩ WAVEFORM GENERATOR NOTE: Low leakage currents allow integration times up to several hours. FIGURE 3. PHOTOCURRENT INTEGRATOR NOTE: Since the output range swings exactly from rail to rail, frequency and duty cycle are virtually independent of power supply variations. FIGURE 4. PRECISE TRIANGLE/SQUARE WAVE GENERATOR 1M VOH 0.5μF 10k VIN 2.2M 20k TO SUCCEEDING INPUT STAGE VOL +8V + ICL7611 10μF 1.8k = 5% SCALE ADJUST + V+ OUT IQ TA = +125°C 20k - - V- COMMON ICL7611 + -8V V+ FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D CONVERTERS SUCH AS ICL7106, ICL7107, ICL7109, ICL7116, ICL7117 FIGURE 6. BURN-IN AND LIFE TEST CIRCUIT VIN + BAL 25k BAL VOUT V+ FIGURE 7. VOS NULL CIRCUIT 7 FN2919.8 September 27, 2006 ICL7611, ICL7612 0.2μF 30k 160k + ICL7611 680k 100k 51k + ICL7611 0.2μF 0.2μF 360k INPUT 0.1μF 0.2μF 0.1μF 1M OUTPUT 1M (NOTE 5) 360k (NOTE 5) NOTES: 5. Note that small capacitors (25pF to 50pF) may be needed for stability in some cases. 6. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4, Passband ripple = 0.1dB. FIGURE 8. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER Typical Performance Curves 10k TA = +25°C NO LOAD NO SIGNAL SUPPLY CURRENT (μA) 1k IQ = 100μA 100 IIQ = 10μA Q = 1mA 10 IQ = 1mA SUPPLY CURRENT (μA) 103 104 V+ - V- = 10V NO LOAD NO SIGNAL IQ = 1mA 102 IQ = 100μA 10 I Q = 1 0 μA 1 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14 16 1 -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE DIFFERENTIAL VOLTAGE GAIN (kV/V) 1000 VS = ±5V INPUT BIAS CURRENT (pA) 100 1000 VSUPP = 10V VOUT = 8V RL = 1 MΩ I Q = 1 0 μA RL = 100kΩ IQ = 100μA 100 RL = 10kΩ IQ = 1mA 10 10 1.0 0.1 -50 -25 0 25 50 75 FREE-AIR TEMPERATURE (°C) 100 125 1 -75 -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 12. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs FREE-AIR TEMPERATURE 8 FN2919.8 September 27, 2006 ICL7611, ICL7612 Typical Performance Curves 107 DIFFERENTIAL VOLTAGE GAIN (V/V) 106 105 104 103 102 10 1 0.1 TA = +25°C VSUPP = 15V (Continued) 105 COMMON MODE REJECTION RATIO (dB) VSUPP = 10V 100 95 90 85 80 75 70 -75 IQ = 10μA IQ = 100μA IQ = 1mA IQ = 100μA IQ = 1mA 0 45 PHASE SHIFT (°) PHASE SHIFT (IQ = 1mA) 90 135 IQ = 10μA 1.0 10 100 1k 10k FREQUENCY (Hz) 100k 180 1M -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FIGURE 13. LARGE SIGNAL FREQUENCY RESPONSE FIGURE 14. COMMON MODE REJECTION RATIO vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE REJECTION RATIO (dB) 100 IQ = 1mA 95 90 85 80 75 70 65 -75 IQ = 100μA I Q = 1 0 μA VSUPP = 10V EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) 600 500 400 300 200 100 0 10 100 1k FREQUENCY (Hz) 10k 100k TA = +25°C 3V ≤ VSUPP ≤ 16V -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE FIGURE 16. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 16 MAXIMUM OUTPUT VOLTAGE (VP-P) MAXIMUM OUTPUT VOLTAGE (VP-P) 14 12 10 8 6 4 2 0 100 VSUPP = ±2V 1k 10k 100k FREQUENCY (Hz) 1M 10M VSUPP = ±5V VSUPP = ±8V TA = +25°C IQ = 1mA IQ = 10μA IQ = 100μA 16 14 12 10 8 6 4 2 0 10k TA = -55°C TA = +25°C TA = +125°C VSUPP = 10V IQ = 1mA 100k 1M FREQUENCY (Hz) 10M FIGURE 17. OUTPUT VOLTAGE vs FREQUENCY FIGURE 18. OUTPUT VOLTAGE vs FREQUENCY 9 FN2919.8 September 27, 2006 ICL7611, ICL7612 Typical Performance Curves 16 MAXIMUM OUTPUT VOLTAGE (VP-P) MAXIMUM OUTPUT VOLTAGE (VP-P) TA = +25°C 14 12 10 8 6 4 RL = 100kΩ - 1MΩ RL = 10kΩ (Continued) 12 RL = 100kΩ 10 8 RL = 10kΩ 6 RL = 2kΩ 4 VSUPP = 10V IQ = 1mA 2 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 0 -75 -50 -25 0 25 50 75 FREE-AIR TEMPERATURE (°C) 100 125 FIGURE 19. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FIGURE 20. OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE MAXIMUM OUTPUT SOURCE CURRENT (mA) 40 IQ = 1mA 30 MAXIMUM OUTPUT SINK CURRENT (mA) 0.01 IQ = 10μA 0.1 20 IQ = 100μA 1.0 10 IQ = 1mA 10 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14 16 0 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) FIGURE 21. OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE FIGURE 22. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE 16 MAXIMUM OUTPUT VOLTAGE (VP-P) 14 12 10 8 6 4 2 0 0.1 INPUT AND OUTPUT VOLTAGE (V) TA = +25°C V+ - V- = 10V IQ = 1mA 8 6 4 2 0 -2 INPUT -4 -6 1.0 10 LOAD RESISTANCE (kΩ) 100 0 2 4 6 TIME (μs) 8 10 12 OUTPUT TA = +25°C, VSUPP = 10V RL = 10kΩ, CL = 100pF FIGURE 23. OUTPUT VOLTAGE vs LOAD RESISTANCE FIGURE 24. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 1mA) 10 FN2919.8 September 27, 2006 ICL7611, ICL7612 Typical Performance Curves 8 INPUT AND OUTPUT VOLTAGE (V) 6 4 2 OUTPUT 0 -2 INPUT -4 -6 0 20 40 60 TIME (μs) 80 100 120 INPUT AND OUTPUT VOLTAGE (V) TA = +25°C, VSUPP = 10V RL = 100kΩ, CL = 100pF (Continued) 8 6 4 2 OUTPUT 0 INPUT -2 -4 -6 TA = +25°C, VSUPP = 10V RL = 1MΩ, CL = 100pF 0 200 400 600 TIME (μs) 800 1000 1200 FIGURE 25. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100μA) FIGURE 26. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 10μA) 11 FN2919.8 September 27, 2006 ICL7611, ICL7612 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 12 FN2919.8 September 27, 2006 ICL7611, ICL7612 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A C L E E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N eA eC C A BS C MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 e A1 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN2919.8 September 27, 2006