AD7541

® AD7541 May 2002 FN3107.3 CT RO DU T LETE P TE PRODUC O BS O TITU Data Sheet BS LE SU D7521 A POSSIB 12-Bit, Multiplying D/A Converter The AD7541 is a monolithic, low cost, high performance, 12-bit accurate, multiplying digital-to-analog converter (DAC). Intersil’ wafer level laser-trimmed thin-film resistors on CMOS circuitry provide true 12-bit linearity with TTL/CMOS compatible operation. Special tabbed-resistor geometries (improving time stability), full input protection from damage due to static discharge by diode clamps to V+ and ground, large IOUT1 and IOUT2 bus lines (improving superposition errors) are some of the features offered by Intersil AD7541. Features • 12-Bit Linearity 0.01% • Pretrimmed Gain • Low Gain and Linearity Tempcos • Full Temperature Range Operation • Full Input Static Protection • TTL/CMOS Compatible • +5V to +15V Supply Range • 20mW Low Power Dissipation • Current Settling Time 1µs to 0.01% of FSR • Four Quadrant Multiplication Pinout AD7541 (PDIP) TOP VIEW IOUT1 1 IOUT2 2 GND 3 BIT 1 (MSB) 4 BIT 2 5 BIT 3 6 BIT 4 7 BIT 5 8 BIT 6 9 18 RFEEDBACK 17 VREF IN 16 V+ 15 BIT 12 (LSB) 14 BIT 11 13 BIT 10 12 BIT 9 11 BIT 8 10 BIT 7 Functional Block Diagram VREF IN (17) 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ (3) 10kΩ 10kΩ 10kΩ 10kΩ SPDT NMOS SWITCHES 10kΩ MSB (4) BIT 2 (5) BIT 3 (6) IOUT2 (2) IOUT1 (1) RFEEDBACK (18) NOTE: Switches shown for digital inputs “High”. Part Number Information PART NUMBER AD7541JN AD7541KN NONLINEARITY 0.02% (11-Bit) 0.01% (12-Bit) TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 18 Ld PDIP 18 Ld PDIP PKG. NO. E18.3 E18.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved AD7541 Absolute Maximum Ratings Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . +17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+ Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified TA = 25oC TA MIN-MAX MAX MIN MAX UNITS PARAMETER SYSTEM PERFORMANCE (Note 4) Resolution Nonlinearity J K Monotonicity Gain Error Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS Power Supply Rejection TEST CONDITIONS MIN TYP 12 -10V ≤ VREF ≤ +10V VOUT1 = VOUT2 = 0V See Figure 4 (Note 5) - - ±0.024 ±0.012 Guaranteed 12 - ±0.024 ±0.012 Bits % of FSR % of FSR -10V ≤ VREF ≤ +10V (Note 5) VOUT1 = VOUT2 = 0 - - ±0.3 ±50 - ±0.4 ±200 % of FSR nA V+ = 14.5V to 15.5V See Figure 5 (Note 5) To 0.1% of FSR See Figure 9 (Note 6) VREF = 20VP-P, 10kHz All Digital Inputs Low See Figure 8 (Note 6) - - ±0.005 - ±0.01 % of FSR/% of ∆V+ µs Output Current Settling Time - - 1 - 1 Feedthrough Error - - 1 - 1 mVP-P REFERENCE INPUTS Input Resistance All Digital Inputs High IOUT1 at Ground 5 10 20 5 20 kΩ ANALOG OUTPUT Voltage Compliance Both Outputs, See Maximum Ratings (Note 7) COUT1 COUT2 COUT1 COUT2 Output Noise (Both Outputs) See Figure 6 All Digital Inputs Low See Figure 7 (Note 6) All Digital Inputs High See Figure 7 (Note 6) -100mV to V+ Output Capacitance 200 60 60 200 - 200 60 60 200 pF pF pF pF Equivalent to 10kΩ Johnson Noise 2 AD7541 Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified (Continued) TA = 25oC PARAMETER DIGITAL INPUTS Low State Threshold, VIL High State Threshold, VIH Input Current Input Coding Input Capacitance POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range Accuracy Is Not Guaranteed Over This Range All Digital Inputs High or Low (Excluding Ladder Network) (Including Ladder Network) +5 to +16 V VIN = 0V or V+ (Note 6) See Tables 1 and 2 (Note 6) (Note 6) (Notes 2, 6) 2.4 0.8 ±1 2.4 0.8 ±1 V V µA TEST CONDITIONS MIN TYP MAX TA MIN-MAX MIN MAX UNITS Binary/Offset Binary 8 8 pF I+ 2.0 - 2.5 mA Total Power Dissipation NOTES: - 20 - - - mW 2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. 3. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK . 4. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes. 5. Using internal feedback resistor, RFEEDBACK . 6. Guaranteed by design or characterization and not production tested. 7. Accuracy not guaranteed unless outputs at ground potential. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a “best fit straight line” function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF range. Resolution: Value of the LSB. For example, a unipolar converter with n bits has a resolution of LSB = (VREF)/2N. A bipolar converter of N bits has a resolution of LSB = (VREF)/2(N-1). Resolution in no way implies linearity. Settling Time: Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, i.e., 0 to Full Scale. Gain Error: Ratio of the DAC’s operational amplifier output voltage to the nominal input voltage value. Feedthrough Error: Error caused by capacitive coupling from VREF to output with all switches OFF. Output Capacitance: Capacitance from IOUT1 , and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1, terminal when all digital inputs are LOW or on IOUT2 terminal when all inputs are HIGH. 3 Detailed Description The AD7541 is a 12-bit, monolithic, multiplying D/A converter. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit. CMOS level shifters provide low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown on page 1, (Functional Diagram). The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further eliminated by using wider metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset (leakage) errors to a negligible level. Each circuit is laser-trimmed, at the wafer level, to better than 12-bits linearity. For the first four bits of the ladder, special trim-tabbed geometries are used to keep the body of the resistors, carrying the majority of the output current, undisturbed. The resultant time stability of the trimmed circuits is comparable to that of untrimmed units. AD7541 The level shifter circuits are comprised of three inverters with a positive feedback from the output of the second to first (Figure 1). This configuration results in TTL/COMS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binary weighted for an “ON” resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistor, resulting in accurate leg currents. V+ 13 4 6 TO LADDER VREF ±10V BIT 1 (MSB) 8 9 DIGITAL INPUT 2 5 7 BIT 12 (LSB) IOUT2 IOUT1 GND 4 16 RFEEDBACK 18 IOUT1 5 AD7541 1 17 3 2 IOUT2 CR1 + Unipolar Binary Operation The circuit configuration for operating the AD7541 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The “Digital Input Code/Analog Output Value” table for unipolar mode is given in Table 1. A Schottky diode (HP5082-2811 or equivalent) prevents IOUT1 from negative excursions which could damage the device. This precaution is only necessary with certain high speed amplifiers. +15V A VOUT TTL/CMOS INPUT 15 FIGURE 1. CMOS LEVEL SHIFTER AND SWITCH FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Typical Applications General Recommendations Static performance of the AD7541 depends on IOUT1 and IOUT2 (pin 1 and pin 2) potentials being exactly equal to GND (pin 3). The output amplifier should be selected to have a low input bias current (typically less than 75nA), and a low drift (depending on the temperature range). The voltage offset of the amplifier should be nulled (typically less than ±200µV). The bias current compensation resistor in the amplifier’s non-inverting input can cause a variable offset. Noninverting input should be connected to GND with a low resistance wire. Ground-loops must be avoided by taking all pins going to GND to a common point, using separate connections. The V+ (pin 16) power supply should have a low noise level and should not have any transients exceeding +17V. Unused digital inputs must be connected to GND or V+ for proper operation. A high value resistor (~1MΩ) can be used to prevent static charge accumulation, when the inputs are open-circuited for any reason. When gain adjustment is required, low tempco (approximately 50ppm/oC) resistors or trim-pots should be selected. Zero Offset Adjustment 1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±0.5mV (Max) at VOUT . Gain Adjustment 1. Connect all digital inputs to VDD . 2. Monitor VOUT for a -VREF (1 - 1/212) reading. 3. To increase VOUT , connect a series resistor, (0Ω to 250Ω), in the IOUT1 amplifier feedback loop. 4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω), between the reference voltage and the VREF terminal. TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION DIGITAL INPUT 111111111111 100000000001 100000000000 011111111111 000000000001 000000000000 ANALOG OUTPUT -VREF (1 - 1/212) -VREF (1/2 + 1/212) -VREF/2 -VREF (1/2 - 1/212) -VREF (1/212) 0 Bipolar (Offset Binary) Operation The circuit configuration for operating the AD7541 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values Four-Quadrant multiplication can be realized. The “Digital Input Code/Analog Output Value” table for bipolar mode is given in Table 2. 4 AD7541 A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range of the DAC. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected by using an external resistive divider, from VREF to IOUT2 . 9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 10. Adjust R4 for 0V ±0.2mV at VOUT . Gain Adjustment 1. Connect all digital inputs to VDD . 2. Monitor VOUT for a -VREF (1 - 1/211) volts reading. 3. To increase VOUT , connect a series resistor, (0Ω to 250Ω), in the IOUT1 amplifier feedback loop. 4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω), between the reference voltage and the VREF terminal. TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY) OPERATION DIGITAL INPUT 111111111111 100000000001 100000000000 011111111111 000000000001 000000000000 ANALOG OUTPUT -VREF (1 - 1/211) -VREF (1/211) 0 VREF (1/211) VREF (1 - 1/211) VREF Offset Adjustment 1. Adjust VREF to approximately +10V. 2. Set R4 to zero. 3. Connect all digital inputs to “Logic 1”. 4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V ±0.1mV at IOUT2 amplifier output. 5. Connect a short circuit across R2. 6. Connect all digital inputs to “Logic 0”. 7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V ±0.1mV at IOUT1 amplifier output. 8. Remove short circuit across R2. ±10V VREF +15V BIT 1 (MSB) 4 17 16 18 1 IOUT1 6 + A1 VOUT DIGITAL INPUT AD7541 R1 10K R2 10K R5 10K 15 BIT 12 (LSB) 3 GND 2 IOUT2 R3 390K 6 + A2 R4 500Ω NOTE: R1 and R2 should be 0.01%, low-TCR resistors. FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) 5 AD7541 Test Circuits VREF BIT 1 (MSB) 4 12-BIT BINARY COUNTER BIT 12 (LSB) CLOCK VREF BIT 1 (MSB) BIT 12 BIT 13 BIT 14 14-BIT REFERENCE DAC 10K 0.01% 5 AD7541 AD7541 15 3 2 GND IOUT2 17 +15V 16 18 1 RFEEDBACK IOUT1 HA2600 + 10K 0.01% 1MΩ HA2600 + LINEARITY ERROR X 100 FIGURE 4. NONLINEARITY TEST CIRCUIT +15V UNGROUNDED SINE WAVE GENERATION 40Hz 1.0VP-P VREF +10V 5K 0.01% BIT 1 (MSB) 17 4 16 RFEEDBACK 5K 0.01% 18 IOUT1 5 1 AD7541 HA2600 IOUT2 + 15 3 2 GND 500K HA2600 + VERROR X 100 BIT 12 (LSB) FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT +11V (ADJUST FOR VOUT = 0V) +15V 1K 100Ω 15µF 17 4 5 16 2 IOUT2 10K f = 1kHz BW = 1Hz QUAN TECH MODEL 134D WAVE ANALYZER AD7541 IOUT1 15 3 1 50K 1K -50V 0.1µF 101ALN + VOUT FIGURE 6. NOISE TEST CIRCUIT 6 AD7541 Test Circuits +15V (Continued) NC +15V VREF = 20VP-P 10kHz SINE WAVE +15V BIT 1 (MSB) 17 16 4 18 5 AD7541 1 17 3 2 NC 1K BIT 1 (MSB) BIT 12 (LSB) SCOPE 100mVP-P 1MHz BIT 12 (LSB) 17 16 4 18 5 AD7541 IOUT1 3 1 IOUT2 HA2600 15 3 2 2 GND 6 VOUT FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT +10V VREF +15V EXTRAPOLATE 3t: 5% SETTLING 9t: 0.01% SETTLING BIT 1 (MSB) +5V 0V DIGITAL INPUT BIT 12 (LSB) 17 16 4 5 AD7541 1 15 3 2 GND +100mV IOUT2 100Ω OSCILLOSCOPE FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT +15V VREF +10V RFEEDBACK IOUT1 IOUT2 CC A + BIT 1 (MSB) BIT 2 17 16 4 18 5 AD7541 1 15 3 2 GND - BIT 12 (LSB) VOUT FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, CC Dynamic Performance The dynamic performance of the DAC, also depends on the output amplifier selection. For low speed or static applications, AC specifications of the amplifier are not very critical. For high-speed applications slew-rate, settling-time, openloop gain and gain/phase-margin specifications of the amplifier should be selected for the desired performance. The output impedance of the AD7541 looking into IOUT1 varies between 10kΩ (RFEEDBACK alone) and 5kΩ (RFEEDBACK in parallel with the ladder resistance). Similarly the output capacitance varies between the minimum and the maximum values depending on the input code. These variations necessitate the use of compensation capacitors, when high speed amplifiers are used. A capacitor in parallel with the feedback resistor (as shown in Figure 10) provides the necessary phase compensation to critically damp the output. A small capacitor connected to the compensation pin of the amplifier may be required for unstable situations causing oscillations. Careful PC board layout, minimizing parasitic capacitances, is also vital. 7 AD7541 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E18.3 (JEDEC MS-001-BC ISSUE D) 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.845 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.880 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 21.47 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 22.35 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 18 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 18 2.93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8