CDP1855CE

CDP1855, CDP1855C March 1997 8-Bit Programmable Multiply/Divide Unit Description The CDP1855 and CDP1855C are CMOS 8-bit multiply/divide units which can be used to greatly increase the capabilities of 8-bit microprocessors. They perform multiply and divide operations on unsigned, binary operators. In general, microprocessors do not contain multiply or divide instructions and even efficiently coded multiply or divide subroutines require considerable memory and execution time. These multiply/divide units directly interface to the CDP1800-series microprocessors via the N-lines and can easily be configured to fit in either the memory or I/O space of other 8-bit microprocessors. The multiple/divide unit is based on a method of multiplying by add and shift right operations and dividing by subtract and shift left operations. The device is structured to permit cascading identical units to handle operands up to 32 bits. The CDP1855 and CDP1855C are functionally identical. They differ in that the CDP1855 has a recommended operating voltage range of 4V to 10.5V, and the CDP1855C, a recommended operating voltage range of 4V to 6.5V. The CDP1855 and CDP1855C types are supplied in a 28 lead hermetic dual-in-line ceramic package (D suffix) and in a 28 lead dual-in-line plastic package (E suffix). The CDP1855C is also available in chip form (H suffix). Features • Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply or 64 ÷ 32-Bit Divide • 8-Bit by 8-Bit Multiply or 16 ÷ 8-Bit Divide in 5.6µs at 5V or 2.8µs at 10V • Direct Interface to CDP1800-Series Microprocessors • Easy Interface to Other 8-Bit Microprocessors • Significantly Increases Throughput of Microprocessor Used for Arithmetic Calculations Ordering Information PACKAGE TEMP. RANGE PDIP Burn-In SBDIP Burn-In 5V 10V PKG. NO. -40oC to +85oC CDP1855CE CDP1855CEX CDP1855E E28.6 E28.6 -40oC to +85oC CDP1855CD CDP1855D D28.6 CDP1855CDX D28.6 Pinout 28 LEAD DIP TOP VIEW CE 1 CLEAR 2 CTL 3 C.O./O.F. 4 YL 5 ZL 6 SHIFT 7 CLK 8 STB 9 RD/WE 10 RA2 11 RA1 12 RA0 13 VSS 14 28 VDD 27 CN0 26 CN1 25 CI 24 YR 23 ZR 22 BUS 7 21 BUS 6 20 BUS 5 19 BUS 4 18 BUS 3 17 BUS 2 16 BUS 1 15 BUS 0 Circuit Configuration +V CLEAR XTAL N0 N1 N2 TPB MRD CDP1802 YL ZR CTL EF C0 YR ZL BUS CLK RA0 RA1 RA2 STB CLEAR CE C1 CN0 CN1 RD/WE CDP1855 BUS FIGURE 1. MDU ADDRESSED AS I/O DEVICE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 1053.2 4-47 CDP1855, CDP1855C Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All voltage values referenced to VSS terminal) CDP1855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1855C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Information Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 50 12 Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTg) . . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Static Electrical Specifications At TA = -40 to +85oC, VDD ±10%, Unless Otherwise Specified CONDITIONS CDP1855 LIMITS CDP1855C MAX 50 200 0.1 0.1 1.5 3 ±1 ±1 ±1 ±10 12 7.5 15 MIN 1.6 -1.15 4.9 3.5 (NOTE1) TYP 0.02 3.2 -2.3 0 5 1.5 5 10 MAX 200 0.1 1.5 ±1 ±1 3 7.5 15 UNITS µA µA mA mA mA mA V V V V V V V V µA µA µA µA mA mA pF pF PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low Level (Note 2) Output Voltage High Level (Note 2) Input Low Voltage IDD VO (V) IOL 0.4 0.5 IOH 4.6 9.5 VOL VOH VIL 0.5, 4.5 0.5, 9.5 VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 - VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 - MIN 1.6 2.6 -1.15 -2.6 4.9 9.9 3.5 7 - (NOTE1) TYP 0.01 1 3.2 5.2 -2.3 -5.2 0 0 5 10 1.5 6 5 10 Input High Voltage VIH 0.5, 4.5 0.5, 9.5 Input Leakage Current IIN - Three-State Output Leakage Current Operating Current (Note 3) Input Capacitance Output Capacitance NOTES: IOUT 0, 5 0, 10 IDD1 - CIN COUT - 1. Typical values are for TA = +25oC and nominal VDD. 2. IOL = IOH = 1µA 3. Operating current is measured at 3.2MHz with open outputs. 4-48 CDP1855, CDP1855C Recommended Operating Conditions At TA = Full package temperature range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS VDD (V) 5 10 Minimum 8 x 8 Multiply (16 ÷ 8 Divide) Time 5 10 CE 1 RA2 RA1 RA0 11 12 13 CDP1855 MIN 4 VSS 3.2 6.4 MAX 10.5 VDD 5.6 2.8 CDP1855C MIN 4 VSS 3.2 MAX 6.5 VDD 5.6 UNITS V V MHz MHz µs µs PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Frequency SELECT CONTROL SELECT Z REGISTER SELECT LOGIC SELECT STATUS SELECT Y SELECT X X REGISTER X SEQUENCE COUNTER RESET OUT 8 CLOCK 8 CN1 26 CN0 27 NO. CHIP 8 C.O. STATUS REG SHIFT GENERATOR 8 ADD/ SUBTRACT 3 4 CTL. C.O./O.F. 25 C.I. LOAD Y SEQUENCE COUNTER RESET OUT SHIFT Y REGISTER LOAD RESET 8 5 YL 24 YR Z SEQUENCE COUNTER RESET OUT SHIFT Z REGISTER LOAD RESET 8 6 ZL 23 ZR LOAD BUS BUS BUS BUS BUS BUS BUS BUS 7 6 5 4 3 2 1 0 9 STB 2 CLEAR 7 SHIFT 10 RD/WE 22 14 VSS 28 VDD 21 20 19 18 17 16 15 FIGURE 2. BLOCK DIAGRAM OF CDP1855 AND CDP1855C 4-49 CONTROL REGISTER CDP1855, CDP1855C Functional Description The CDP1855 is a multiply-divide unit (MDU) designed to be compatible with CDP1800 series microprocessor systems. It can, in fact, be interfaced to most 8-bit microprocessors (see Figure 5). The CDP1855 performs binary multiply or divide operations as directed by the microprocessor. It can do a 16N-bit by 8N-bit divide yielding a 8N-bit result plus and 8Nbit remainder. The multiply is an 8N-bit by 8N-bit operation with a 16N-bit result. The “N” represent the number of cascaded CDP1855's and can be 1, 2, 3 or 4. All operations require 8N + 1 shift pulses (See “DELAY NEEDED WITH AND WITHOUT PRESCALER”). The CDP1855 contains three registers, X, Y, and Z, which are loaded with the operands prior to an operation and contain the results at the completion. In addition, the control register must be loaded to initiate a multiply or divide. There is also a status register which contains an overflow flag as shown in the “CONTROL REGISTER BIT ASSIGNMENT TABLE”. The register address lines (RA0-RA1) are used to select the appropriate register for loading or reading. The RD/WE and STB lines are used in conjunction with the RA lines to determine the exact MDU response (See “CONTROL TRUTH TABLE”). When multiple MDU's are cascaded, the loading of each register is done sequentially. For example, the first selection of register X for loading loads the most significant CDP1855, the second loads the next significant, and so on. Registers are also read out sequentially. This is accomplished by internal counters on each MDU which are decremented by STB during each register selection. When the counter matches the chip number (CN1, CN0 lines), the device is selected. These counters must be cleared with a clear on pin 2 or with bit 6 in the control word (See “CONTROL REGISTER BIT ASSIGNMENT TABLE”) in order to start each sequence of accesses with the most significant device. The CDP1855 has a built in clock prescaler which can be selected via bit 7 in the control register. The prescaler may be necessary in cascaded systems operating at high frequencies or in systems where a suitable clock frequency is not readily available. Without the prescaler select, the shift frequency is equal to the clock input frequency. With the prescaler selected, the rate depends on the number of MDU's as defined by bits 4 and 5 of the control word (See “CONTROL REGISTER BIT ASSIGNMENT TABLE”). 1. For one MDU, the clock frequency is divided by 2. 2. For two MDU's the clock frequency is divided by 4. 3. For 3 or 4 MDU's, the clock frequency is divided by 8. Prior to loading any other registers the control register must be loaded to specify the number of MDU's being used (See “CONTROL REGISTER BIT ASSIGNMENT TABLE”). Once the number of devices has been specified and the sequence counters cleared with a clear pulse or bit 6 of the control word, the X, Y, and Z registers can be loaded as defined in the “CONTROL TRUTH TABLE”. All bytes of the X register can be loaded, then all bytes of the Y, and then all bytes of the Z, or they can be loaded randomly. Successive loads to a given register will always proceed sequentially from the most significant byte to the least significant byte, as previously described. Resetting the sequence counters select the most significant MDU. In a four MDU system, loading all MDU's results in the sequence counter pointing to the first MDU again. In all other configurations (1, 2, or 3 MDU's), the sequence counter must be reset prior to each series of register reads or writes. 2. Divide Operation For the divide operation, the divisor is loaded in the X register. The dividend is loaded in the Y and Z registers with the more significant half in the Y register and the less significant half in the Z register. These registers may be loaded in any order, and after loading is completed, a control word is loaded to specify a divide operation and the number of MDU's and also to reset the sequence counters and Y or Z register and select the clock option if desired. Clearing the sequence counters with bit 6 will set the MDU's up for reading the results. The X register will be unaltered by the operation. The quotient will be in the Z register while the remainder will be in the Y register. An overflow will be indicated by the C.O./O.F. of the most significant MDU and can also be determined by reading the status byte. While the CDP1855 is specified to perform 16 by 8-bit divides, if the quotient of a divide operation exceeds the size of the Z register(s) (8N-bits - where N is the number of cascaded CDP1855's) the overflow bit in the Status Register will be set. Neither the quotient in Z nor the remainder in Y will represent a valid answer. This will always be the result of a division performed when the divisor (X) is equal to or less than the most significant 8N-bits of the dividend (Y). The MDU can still be used for such computations if the divide is done in two steps. The dividend is split into two parts-the more significant 8N-bits and the less significant 8N-bits-and a divide done on each part. Each step yields an 8N-bit result for a total quotient of 16N-bits. The first step consists of dividing the more significant 8Nbits by the divisor. This is done by clearing the Y register(s), loading the Z register(s) with the more significant 8N-bits of the dividend, and loading the X register(s) with the divisor. A division is performed and the resultant value in Z represents the more significant 8N-bits of the final quotient. The Z register(s) value must be unloaded and saved by the processor. Operation 1. Initialization and Controls The CDP1855 must be cleared by a low on pin 2 during power-on which prevents bus contention problems at the YL, YR and ZL, ZR terminals and also resets the sequence counters and the shift pulse generator. 4-50 CDP1855, CDP1855C A second division is performed using the remainder from the first division (in Y) as the more significant 8N-bits of the dividend and the less significant half of the original dividend loaded into the Z register. The divisor in X remains unaltered and is, by definition, larger than the remainder from the first division which is in Y. The resulting value in Z becomes the less significant 8N-bits of the final quotient and the value in Y is, as usual, the remainder. Extending this technique to more steps allows division of any size number by an 8N-bit divisor. Note that division by zero is never permitted and must be tested for and handled in software. The following example illustrates the use of this algorithm. Example: Assume three MDU's capable of a by 24-bit division. The problem is to divide 00F273, 491C06H by 0003B4H. Step 1: 000000 Y Step 2: 0001BF Y1 Result: 000041 Z1 , , , 00F273 Z(MS) 491C06 Z(LS) 78C936 Z2 / / 0003B4 X 0003B4 X R=00000E Y2 = 000041 Z1 = 78C936 Z2 R=0001BF Y1 R=00000E Y2 ZR of the least significant CDP1855 MDU. This signal is used to indicate whether the registers are to be operated on or only shifted. C.O./O.F. - Carry Out/Over Flow (Output): This is a three-state output pin. It is the CDP1855 Carry Out signal and is connected to Cl (CARRY-IN) of the next more significant CDP1855 MDU, except for on the most significant MDU. On that MDU it is an overflow indicator and is enabled when chip enables is true. A low on this pin indicates that an overflow has occurred. The overflow signal is latched each time the control register is loaded, but is only meaningful after a divide command. YL, YR - Y-Left, Y-Right: These are three-state bi-directional pins for data transfer between the Y registers of cascaded CDP1855 MDU's. The YR pin is an output and YL is an input during a multiply and the reverse is true at all other times. The YL pin must be connected to the YR pin of the next more significant MDU. An exception is that the YL pin of the most significant CDP1855 MDU must be connected to the ZR pin of the least significant MDU and to the CTL pins of all MDU's. Also the YR pin of the least significant MDU is tied to the ZL pin of the most significant MDU. ZL, ZR - Z-Left, Z-Right: These are three-state bi-directional pins for data transfers between the “Z” registers of cascaded MDU's. The ZR pin is an output and ZL is an input during a multiply and the reverse is true at all other times. The ZL pin must be tied to the YR pin of the next more significant MDU. An exception is that the ZL in of the most significant MDU must be connected to the YR pin of the least significant MDU. Also, the ZR pin of the least significant MDU is tied to the YL of the most significant MDU. Shift - Shift Clock: This is a three-state bi-directional pin. It is an output on the most significant MDU. And an input on all other MDU's. It provides the MDU system timing pulses. All SHIFT pins must be connected together for cascaded operation. A maximum of the 8N +1 shifts are required for an operation where "N" equals the number of MDU devices that are cascaded. CLK - Clock (Input): This pin should be grounded on all but the most significant MDU. There is an optional reduction of clock frequency available on this pin if so desired, controlled by bit 7 of the control byte. STB - Strobe (Input): When RD/WE is low, data is latched from bus lines on the falling edge of this signal. It may be asynchronous to the clock. Strobe also increments the selected register's sequence counter during reads and writes. TPB would be used in CDP1800 systems. The Z register can simply be reset using bit 2 of the control word and another divide can be done in order to further divide the remainder. 3. Multiply Operation For a multiply operation the two numbers to be multiplied are loaded in the X and Z registers. The result is in the Y and Z register with Y being the more significant half and Z the less significant half. The X register will be unchanged after the operation is completed. The original contents of the Y register are added to the product of X and Z. Bit 3 of the control word will reset register Y to 0 if desired. Functional Description of CDP1855 Terminals CE - Chip Enable (Input): A high on this pin enables the CDP1855 MDU to respond to the select lines. All cascaded MDU's must be enabled together. CE also controls the three-state C.O./O.F., output of the most significant MDU. Clear (Input): The CDP1855 MDU(s) must be cleared upon power-on with a low-on this pin. The clear signal resets the sequence counters, the shift pulse generator, and bits 0 and 1 of the control register. CTL - Control (Input): This is an input pin. All CTL pins must be wired together and to the YL of the most significant CDP1855 MDU and to the 4-51 CDP1855, CDP1855C RD/WE - Read/Write Enable (Input): This signal defines whether the selected register is to be read from or written to. In 1800 systems use MRD if MDU's are addressed as I/O devices, MWR is used if MDU's are addressed as memory devices. RA2, RA1, RA0 - Register Address (Input): These input signals define which register is to be read from or written to. It can be seen in the “CONTROL TRUTH TABLE” that RA2 can be used as a chip enable. It is identical to the CE pin, except only CE controls the three-state C.O./O.F. on the most significant MDU. In 1800 systems use N lines if MDU's are used as I/O devices, use address lines or function of address lines if MDU's are used as memory devices. Bus 0 - Bus 7 - Bus Lines: Three-state bi-directional bus for direct interface with CDP1800 series and other 8-bit microprocessors. ZR - Z-Right: See Pin 6. YR - Y-Right: See Pin 5. Cl- Carry In (Input): This is an input for the carry from the next less significant MDU. On the least significant MDU it must be high (VDD) on all others it must be connected to the CO pin of the next less significant MDU. CN1, CN0 - Chip Number (Input): These two input pins are wired high or low to indicate the MDU position in the cascaded chain. Both are high for the most significant MDU regardless of how many CDP1855 MDU's are used. Then CN1 = high and CN0 = low for the next MDU and so forth. VSS - Ground: Power supply line. VDD - V+: Power supply line. CONTROL TRUTH TABLE INPUTS (NOTE 1) CE 0 X 1 1 1 1 1 1 1 1 1 NOTE: 1. ( ) = 1800 System Signals. 1 = High Level, 0 = Low Level, X = High or Low Level. RA2 (N2) X 0 1 1 1 1 1 1 1 1 1 RA1 (N1) X X 0 0 1 1 0 0 1 1 X RA0 (N0) X X 0 1 0 1 0 1 0 1 X RD/WE (MRD) X X 1 1 1 1 0 0 0 0 0 STB (TPB) X X X X X X 1 1 1 1 0 RESPONSE No Action (Bus Floats) No Action (Bus Floats) X to Bus Z to Bus Y to Bus Status to Bus Load X from Bus Load Z from Bus Load Y from Bus Load Control Register No Action (Bus Floats) Increment Sequence Counter Increment Sequence Counter When STB and RD = 1 4-52 CDP1855, CDP1855C CONTROL REGISTER BIT ASSIGNMENT TABLE BUS 7 BUS 6 BUS 5 BUS 4 BUS 3 BUS 2 BUS 1 BUS 0 B1 REGISTER RESET 0 0 1 1 B2 = 1, RESET Z REGISTER B3 = 1, RESET Y REGISTER B5 1 1 0 0 B4 1 0 1 0 NO. OF MDU’s One MDU Two MDU’s Three MDU’s Four MDU’s B0 0 1 0 1 OPERATION SELECT No Operation Multiply Divide Illegal State NO. OF MDU’s 1 B6 = 1, RESET SEQUENCE COUNTER B7 = 1, SELECT SHIFT RATE OPTIONS: B7 = 0, SHIFT = CLOCK FREQUENCY RATE 2 3 4 SHIFT RATE Clock ÷ 2 Clock ÷ 4 Clock ÷ 8 Clock ÷ 8 STATUS REGISTER STATUS BYTE BIT OUTPUT NOTES: 1. O.F. = 1 if overflow (only valid after a divide has been done) 2. Bits 1 - 7 are read as 0 always. DELAY NEEDED WITH AND WITHOUT PRESCALER 8N + 1 Shifts/Operation at 1 Clock Cycle/Shift N = Number of MDU’s, S = Shift Rate WITHOUT PRESCALER (NOTE 1) MACHINE CYCLES NEEDED 2 (1 NOP) 2 (1 NOP) 3 (1 NOP) 4 (2 NOPs) WITH PRESCALER (NOTE 1) MACHINE CYCLES NEEDED 3 (1 NOP) 9 (3 NOPs) 25 (9 NOPs) 33 (11 NOPs) 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 O.F. NO. OF MDU’s 1 2 3 4 NOTE: SHIFTS = 8N +1 NEEDED 9 17 25 33 SHIFTS = S (8N +1) NEEDED 18 68 200 264 SHIFT RATE 2 4 8 8 1. NOP instruction is shown for machine cycles needed (3/NOP). Other instructions may be used. 4-53 CDP1855, CDP1855C CDP1855 Interfacing Schemes VCC 14 28 27 26 25 24 6 3 5 23 22 21 20 19 18 17 15 8085 SIGNAL 16 DATA BUS DATA BUS VSS VDD CN0 CN1 CI YR ZL CTL YL ZR BUS 7 BUS 6 BUS 5 CI CN0 CN1 RA2 BUS 4 2 8 10 YL RE/WE CE STB CO BUS ZR CTL YR ZL 1/4 CD4011 9 CLEAR CLK RD/WE BUS 3 BUS 2 BUS 1 CDP1855 MDU CLEAR XTAL MA0 MA1 MAX HIGH ADDRESS LATCH CLEAR CLOCK RA0 RA1 +VDD CDP1802 TPA MWR MRD TPB EF BUS CDP1855 STB BUS 0 RA2 RA1 RA0 CE 11 12 13 1 A8 A9 IO/M WR RD CLK (OUT) RESET OUT 1/4 CD4011 FIGURE 3. REQUIRED CONNECTION FOR MEMORY MAPPED ADDRESSING OF THE MDU FIGURE 4. INTERFACING THE CDP1855 TO AN 8085 MICROPROCESSOR AS AN I/O DEVICE Programming Example for Multiplication For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C16 by 723C0916: MEMORY LOCATION 0000 0002 0003 0005 0006 0008 0008 0008 0008 000A 000A 000C 000C 000E 000E 0010 OP CODE F830; A2; F800; B2; 6758; ; ; ; 6420; ; 641F; ; 647C; ; 6572; ; LINE NO. 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 OUT 5; DC 072H OUT 4; DC 07CH OUT 4; DC 01FH OUT 4; DC 020H LDI 030H PLO R2 LDI 00H PHI R2 OUT 7; DC 058H . . LOAD 00 INTO R2.1 (R2=0030) . . LOAD CONTROL REGISTERS . . SPECIFYING THREE MDU’s . . RESET THE Y REGISTER AND . . SEQUENCE COUNTER . . LOAD MSB OF X REGISTER . . WITH 20 . . LOAD NEXT MSB OF X REG . . WITH 1F . . LOAD LSB OF X REGISTER . . WITH 7C . . LOAD MSB OF Z REGISTER . . WITH 72 . . LOAD 30 INTO R2.0 ASSEMBLY LANGUAGE 4-54 CDP1855, CDP1855C Programming Example for Multiplication For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C16 by 723C0916: (Continued) MEMORY LOCATION 0010 0012 0012 0014 0014 0016 0016 0016 0016 OP CODE 653C; ; 6509; ; 6759; ; ; ; ; LINE NO. 0017 0018 0019 0020 0021 0022 0023 0024 0025 OUT 7; DC 059H OUT 5; DC 09H OUT 5; DC 030H ASSEMBLY LANGUAGE . . LOAD NEXT MSB OF Z REG . . WITH 3C . . LOAD LSB OF Z REGISTER . . WITH 09 . . LOAD CONTROL REGISTERS . . RESETTING Y REGISTERS . . AND SEQUENCE COUNTERS . . AND STARTING MULTIPLY . . OPERATION DELAY FOR MULTIPLY TO FINISH 0016 0017 0019 0019 001B 001D 001F 0021 0022 0022 0022 0022 0024 0000 E2; 6E60; ; 6E60; 6E60; 6D60; 6D60; 6D; ; ; ; 3022; ; 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 STOP 0038 BR STOP END INP 6; INP 6; INP 5; INP 5; INP 5 IRX IRX IRX IRX . . COMPLETE LOADING RESULT . . INTO MEMORY LOCATIONS . . 0030 TO 0035 . . RESULTS = 0E558DBA2B5C SEX R2 INP 6; IRX . . MSB OF RESULTS IS STORED . . AT LOCATION 0030 The result of 201F7C16 x 723C0916 is 0E558DBA2B5C = 1576061279727610. It will be stored in memory as follows: LOC 0030 31 32 33 34 35 BYTE 0E 55 8D BA BEFORE MULTIPLY MDU1 REGISTER X REGISTER Y REGISTER Z AFTER MULTIPLY MDU1 REGISTER X 20 0E BA MDU2 1F 55 2B MDU3 7C 8D 5C 20 00 72 MDU2 1F 00 3C MDU3 7C 00 09 2B 5C REGISTER Y REGISTER Z 4-55 CDP1855, CDP1855C Programming Example for Division MEMORY LOCATION 0000 0000 0000 0000 0004 0004 0008 0008 000C 000C 000C 000F 000F 000F 000F 0011 0011 0014 0016 0016 0016 0019 0019 0019 001C 001C 001C 001F 001F 0021 0021 0021 0021 0024 0024 0027 0027 0028 0000 OP CODE ; ; ; 68C22000; ; 68C33000; ; 68C44000; ; ; E067F0; ; ; ; E464; ; E06600; E365; ; ; E067F2; ; ; E26D60; ; ; E067F0; ; E365; ; ; ; E067F2; ; E26D60; ; 6E; ; LINE NO. 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 INP 6 SEX R2; INP 5; IRX . . Read and store the least significant . . 8 bits of the answer at 2001 hex . . Read and store the remainder at 2002 . . hex SEX R0; OUT 7; DC 0F2H . . Do the second division SEX R3; OUT 5 . . Load the 8 least significant 8 bits . . of the original dividend into the Z . . register SEX R0; OUT 7; DC 0F0H . . Reset the sequence counter SEX R2; INP 5; IRX . . Read and store the most significant . . 8 bits of the answer at 2000 hex SEX R0; OUT 7; DC 0F2H . . Do the first divide, also resets the . . sequence counter SEX R0; OUT 6; DC 0 SEX R3; OUT 5 . . Load 0 into the Y register . . Load the most significant 8 bits of . . the dividend into the Z register SEX R4; OUT 4 . . Load the divisor into the X register SEX R4; OUT 7; DC OF0H . . Write to the control register to use . . clock/2; 1MDU; reset sequence . . counter; and no operation RLDI R4, 4000H RLDI R3, 3000H RLDI R2, 2000H . . Answer is stored at 2000 hex . . Register 2 points to it . . Dividend is stored at 3000 hex . . Register 3 points to it . . Divisor is stored at 4000 hex . . Register 4 points to it ASSEMBLY LANGUAGE . . Program example for a 16-bit by 8-bit divide using 1 CDP1855 MDU . . Gives a 16-bit answer with 8-bit remainder For the divide operation (Figure 5), the formula is: 4-56 CDP1855, CDP1855C Y3 Y2 Y1 Z3 Z2 Z1 Y3 Y2 Y1 ------------------------------------------- = Z 3 Z 2 Z 1 + --------------------X3 X2 X1 X3 X2 X1 EF1 DATA BUS 8 BUS MRD TPB CLEAR N2 N1 N0 TO CPU VDD 8 BUS RD/ STB CLR WE CN1 CN0 RA0 RA1 RA2 YR ZR VDD 8 BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR VDD 8 BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR VDD CLOCK CLK SHIFT YL ZL CDP1855 CDP1855 CDP1855 O.F. CE C.I. CTL C.O. CE C.I. CTL C.O. CE C.I. CTL VDD OR I/O SELECT MOST SIGNIFICANT LEAST SIGNIFICANT FIGURE 5. CASCADING THREE MDU’s (CDP1855) IN AN 1800 SYSTEM WITH MDU’s BEING ACCESSED AS I/O PORTS IN PROGRAMMING EXAMPLE CLOCK EF1 DATA BUS BUS MRD TPB CLEAR N2 N1 N0 VDD BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR VDD BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR VDD BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR BUS RD/ STB CLR WE CN1 CN0 CLK SHIFT YL ZL RA0 RA1 RA2 YR ZR VDD CDP1855 CDP1855 CDP1855 CDP1855 O.F. CE C.I. CTL C.O. CE C.I. CTL C.O. CE C.I. CTL C.O. CE C.I. CTL MOST SIGNIFICANT LEAST SIGNIFICANT FIGURE 6. CASCADING FOUR MDU’s (CDP1855) 4-57 CDP1855, CDP1855C Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 100pF (See Figure 7) LIMITS CDP1855 (NOTE 1) PARAMETER OPERATION TIMING Maximum Clock Frequency (Note 3) Maximum Shift Frequency (1 Device) (Note 4) Minimum Clock Width tCLK0 tCLK1 tCLK 5 10 5 10 5 10 5 10 Clock to Shift Propagation Delay Minimum C.I. to Shift Setup tCSH 5 10 tSU 5 10 C.O. from Shift Propagation Delay Minimum C.I. from Shift Hold tPLH tPHL tH 5 10 5 10 Minimum Register Input Setup Register after Shift Delay tSU 5 10 tPLH tPHL tH 5 10 5 10 C.O. from C.I. Propagation Delay Register from C.I. Propagation Delay NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. 2. Typical values are for TA = 25oC and nominal voltages. 3. Clock frequency and pulse width are given for systems using the internal clock option of the CDP1855. Clock frequency equals shift frequency for systems not using the internal clock option. 4. Shift period for cascading of devices is increased by an amount equal to the C.I. to C.O. Propagation Delay for each device added. tPLH tPHL tPLH tPHL 5 10 5 10 3.2 6.4 1.6 3.2 4 8 2 4 100 50 250 125 200 100 50 25 450 225 50 25 -20 -10 400 200 50 25 100 50 80 40 150 75 312 156 300 150 67 33 600 300 75 40 10 10 600 300 100 50 150 75 120 60 3.2 1.6 4 2 100 250 200 50 450 50 -20 400 50 100 80 150 312 300 67 600 75 10 600 100 150 120 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) (NOTE 2) TYP CDP1855C (NOTE 2) TYP MIN MAX MIN MAX UNITS Minimum Clock Period Minimum Register after Shift Hold 4-58 CDP1855, CDP1855C Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 100pF (See Figure 8) LIMITS CDP1855 (NOTE 1) PARAMETER WRITE CYCLE Minimum Clear Pulse Width tCLR 5 10 Minimum Write Pulse Width tWW 5 10 Minimum Data-In-Setup tDSU 5 10 Minimum Data-In-Hold tDH 5 10 Minimum Address to Write Setup Minimum Address after Write Hold NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. 2. Typical values are for TA = 25oC and nominal voltages. tASU 5 10 tAH 5 10 50 25 150 75 -75 -40 50 25 50 25 50 25 75 40 225 115 0 0 75 40 75 40 75 40 50 150 -75 50 50 50 75 225 0 75 75 75 ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) MIN (NOTE 2) TYP MAX MIN CDP1855C (NOTE 2) TYP MAX UNITS Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 100pF (See Figure 9) LIMITS CDP1855 CDP1855C MAX MIN (NOTE 2) TYP MAX UNITS (NOTE 1) PARAMETER READ CYCLE CE to Data Out Active tCDO VDD (V) MIN (NOTE 2) TYP 5 10 50 25 50 25 - 200 100 300 150 300 150 150 75 150 75 200 100 200 100 300 150 450 225 450 225 225 115 225 115 300 150 300 150 50 50 - 200 300 300 150 150 200 200 - 300 450 450 225 225 300 300 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE to Data Access tCA 5 10 Address to Data Access tAA 5 10 Data Out Hold after CE tDOH 5 10 Data Out Hold after Read tDOH 5 10 Read to Data Out Active tRDO 5 10 Read to Data Access tRA 5 10 4-59 CDP1855, CDP1855C Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 100pF (See Figure 9) (Continued) LIMITS CDP1855 (NOTE 1) PARAMETER Strobe to Data Access tSA VDD (V) 5 10 Minimum Strobe Width tSW 5 10 NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. 2. Typical values are for TA = 25oC and nominal voltages. MIN 50 25 (NOTE 2) TYP 200 100 150 75 MAX 300 150 225 115 MIN 50 CDP1855C (NOTE 2) TYP 200 150 MAX 300 225 UNITS ns ns ns ns Timing Diagrams tCLOCK CLK 1 tCLK 0 1 tCSH tPLH, tPHL C.O., YL, YR, ZL, ZR OUT tSU CIN, YL, YR, ZL, ZR IN tH 2 9 2 9 tCLK 1 SHIFT (PRESCALER OFF) FIGURE 7. OPERATION TIMING DIAGRAM tCLR CLEAR CE RD/WE STB * tWW DIN tDSU tDH RA0-2 tASU tAH * WRITE IS OVERLAP OF CE = 1, RD/WE = 0, AND STB = 1. FIGURE 8. WRITE TIMING DIAGRAM 4-60 CDP1855, CDP1855C Timing Diagrams CE (Continued) RD/WE ADVANCE SEQUENCE COUNTER tSW STB RA0-2 tSA DOUT tCDO tCA tRDO tRA tAA tDOH tDOH FIGURE 9. READ TIMING DIAGRAM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-61