CDP1877E

CDP1877, CDP1877C March 1997 Programmable Interrupt Controller (PIC) Description The CDP1877 and CDP1877C are programmable 8-level interrupt controllers designed for use in CDP1800 series microprocessor systems. They provide added versatility by extending the number of permissible interrupts from 1 to N in increments of 8. When a high to low transition occurs on any of the PIC interrupt lines (IR0 to IR7), it will be latched and, unless the request is masked, it will cause the INTERRUPT line on the PIC and consequently the INTERRUPT input on the CPU to go low. The CPU accesses the PIC by having interrupt vector register R(1) loaded with the memory address of the PIC. After the interrupt S3 cycle, this register value will appear at the CPU address bus, causing the CPU to fetch an instruction from the PIC. This fetch cycle clears the interrupt request latch bit to accept a new high-to-low transition, and also causes the PIC to issue a long branch instruction (CO) followed by the preprogrammed vector address written into the PIC’s address registers, causing the CPU to branch to the address corresponding to the highest priority active interrupt request. If no other unmasked interrupts are pending, the INTERRUPT output of the PIC will return high. When an interrupt is requested on a masked interrupt line, it will be latched but it will not cause the PIC INTERRUPT output to go low. All pending interrupts, masked and unmasked, will be indicated by a “1” in the corresponding bit of the status register. Reading of the status register will clear all pending interrupt request latches. Several PICs can be cascaded together by connecting the INTERRUPT output of one chip to the CASCADE input of another. Each cascaded PIC provides 8 additional interrupt levels to the system. The number of units cascadable depends on the amount of memory space and the extent of the address decoding in the system. Interrupts are prioritized in descending order; IR7 has the highest and IR0 has the lowest priority. The CDP1877 and CDP1877C are functionally identical. They differ in that the CDP1877 has a recommended operating voltage range of 4V to 10.5V, and the CDP1877C has a recommended operating voltage range of 4V to 6.5V. Features • Compatible with CDP1800 Series • Programmable Long Branch Vector Address and Vector Interval • 8 Levels of Interrupt Per Chip • Easily Expandable • Latched Interrupt Requests • Hard Wired Interrupt Priorities • Memory Mapped • Multiple Chip Select Inputs to Minimize Address Space Requirements Ordering Information PACKAGE PDIP TEMP. RANGE 5V 10V PKG. NO. -40oC to CDP1877CE CDP1877E E28.6 +85oC Pinout CDP1877, CDP1877C (PDIP) TOP VIEW CASCADE 1 IR7 2 IR6 3 IR5 4 IR4 5 IR3 6 IR2 7 IR1 8 IR0 9 TPA 10 TPB 11 MWR 12 MRD 13 VSS 14 28 VDD 27 BUS 7 26 BUS 6 25 BUS 5 24 BUS 4 23 BUS 3 22 BUS 2 21 BUS 1 20 BUS 0 19 CS/Ax 18 CS/Ay 17 CS 16 CS 15 INT Programming Model PROGRAMMABLE INTERRUPT CONTROLLER (PIC) BUS 7 A15 BUS 7 B7 BUS 7 M7 BUS 7 S7 BUS 7 P7 A14 A13 PAGE REGISTER A12 A11 CONTROL REGISTER B4 B3 MASK REGISTER M4 M3 STATUS REGISTER S4 S3 POLLING REGISTER P4 P3 A10 A9 BUS 0 A8 BUS 0 B0 BUS 0 M0 BUS 0 S0 BUS 0 P0 WRITE ONLY WRITE ONLY WRITE ONLY READ ONLY READ ONLY B6 B5 B2 B1 M6 M5 M2 M1 S6 S5 S2 S1 P6 P5 P2 P1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 1319.2 4-82 CDP1877, CDP1877C Absolute Maximum Ratings DC Supply-Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Information Thermal Resistance (Typical) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Static Electrical Specifications At TA = -40 to +85oC, VDD ±5%, Unless Otherwise Specified CONDITIONS CDP1877 LIMITS CDP1877C MAX 50 200 0.1 0.1 1.5 3 ±1 ±2 ±1 ±10 1.0 3.0 7.5 15 MIN 1.6 -1.15 4.9 3.5 (NOTE1) TYP 0.02 3.2 -2.3 0 5 ±10-4 0.5 5 10 MAX 200 0.1 1.5 ±1 ±1 1.0 7.5 15 UNITS µA µA mA mA mA mA V V V V V V V V µA µA µA µA mA mA pF pF PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low Level (Note 2) Output Voltage High Level (Note 2) Input Low Voltage IDD VO (V) IOL 0.4 0.5 IOH 4.6 9.5 VOL VOH VIL 0.5, 4.5 0.5, 9.5 VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 - VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 - MIN 1.6 2.6 -1.15 -2.6 4.9 9.9 3.5 7 - (NOTE1) TYP 0.01 1 3.2 5.2 -2.3 -5.2 0 0 5 10 ±10-4 ±10-4 0.5 1.9 5 10 Input High Voltage VIH 0.5, 4.5 0.5, 9.5 Input Leakage Current IIN Any Input 0, 5 0, 10 Three-State Output Leakage Current Operating Device Current (Note 3) Input Capacitance Output Capacitance NOTES: IOUT IOPER - CIN COUT - 1. Typical values are for TA = +25oC and nominal VDD. 2. IOL = IOH = 1µA 3. Operating current is measured under worst-case conditions in a 3.2MHz CDP1802A system, one PIC access per instruction cycle. 4-83 CDP1877, CDP1877C Operating Conditions At TA = Full package temperature range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1877 PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4 VSS MAX 10.5 VDD MIN 4 VSS CDP1877C MAX 6.5 VDD UNITS V V TPA CS CS CA/AX CA/AY 4-BIT LATCH TPB MWR MRD DECODER CS WRITE PAGE REGISTER WRITE CONTROL REGISTER WRITE MASK REGISTER READ STATUS REGISTER READ POLLING REGISTER READ LONG BRANCH CASC READ STATUS REGISTER WRITE MASK REGISTER INT WRITE PAGE REGISTER READ LONG BRANCH EN CLEAR EN HIGH VECTOR ADDRESS EN IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 INTERRUPT LATCH/ STATUS REGISTER MASK REGISTER PRIORITY ENCODER/ VECTOR ADDRESS GENERATION LONG BRANCH INSTRUCTION GENERATE LOGIC READ POLLING REGISTER EN LOW VECTOR ADDRESS CLEAR CLEAR INTERVAL UPPER BITS MWR MRD BUS 0 BUS 1 DATA BUS BUFFERS BUS 2 BUS 3 BUS 4 CONTROL REGISTER WRITE CONTROL REGISTER BUS 5 BUS 6 BUS 7 FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1877 4-84 CDP1877, CDP1877C Functional Definitions for CDP1877 and CDP1877C Terminals TERMINAL VDD - VSS BUS0 - BUS7 IR0 - IR7 INTERRUPT MRD, MWR TPA, TPB CS, CS CS/AX, CS/AY CASCADE Power Data Bus - Communicates Information to and from CPU Interrupt Request Lines Interrupt to CPU Read/Write Controls from CPU Timing Pulses from CPU Chip Selects, Enable Chip if Valid during TPA Used as a Chip Select during TPA and as a Register Address During Read/Write Operations Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher Priority PIC can be Tied to this Input, or the Input can be Tied to VDD if Cascading is Not Used. Bidirectional Input Output Input Input Input Input Input USAGE TYPE PIC Programming Model INTERNAL REGISTERS The PIC has three write-only programmable registers and two read-only registers. Page Register This write only register contains the high order vector address the device will issue in response to an interrupt request. This high-order address will be the same for any of the 8 possible interrupt requests; thus, interrupt vectoring differs only in location within a specified page. BUS 0 A14 A13 PAGE REGISTER BITS A12 A11 A10 A9 A8 WRITE ONLY BUS 7 A15 Control Register The upper nibble of this write-only register contains the low order vector address the device will issue in response to an BUS 7 B7 B6 B5 CONTROL REGISTER BITS B4 B3 B2 B1 interrupt request. The lower nibble is used for a master interrupt reset, master mask reset and for interval select. BUS 0 B0 WRITE ONLY INTERVAL SELECT DETERMINES NUMBER OF BYTES ALLOCATED TO EACH INTERRUPT SERVICE ROUTINE BIT 1 BIT 0 INTERVAL 0 0 2 0 1 4 1 0 8 1 1 16 MASTER MASK RESET 0 RESETS ALL MASK REGISTER BITS 1 NO CHANGE MASTER INTERRUPT RESET 0 RESETS ALL INTERRUPT LATCHES, CLEARS ANY PENDING INTERRUPTS 1 NO CHANGE SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS A FUNCTION OF THE INTERVAL SELECT 4-85 CDP1877, CDP1877C The Low Order Vector Address will be set according to the table below: LOW ADDRESS BITS INTERVAL SELECTED NO. OF BYTES 2 4 8 16 NOTES: 1. X = Don’t Care 2. All Don’t Care addresses and addresses A0-A3 are determined by interrupt request. BIT B7 SETS A7 SETS A7 SETS A7 SETS A7 BIT B6 SETS A6 SETS A6 SETS A6 X BIT B5 SETS A5 SETS A5 X X BIT B4 SET A4 X X X Mask Register A ”1” written into any location in this write only register will mask the corresponding interrupt request line. All interrupt inputs (except CASCADE) are maskable. BUS 7 M7 M6 M5 MASK REGISTER BITS M4 M3 M2 M1 BUS 0 M0 WRITE ONLY Status Register In this read only register a “1” will be present in the corresponding bit location for every masked or unmasked pending interrupt. BUS 7 S7 S6 S5 STATUS REGISTER BITS S4 S3 S2 S1 BUS 0 S0 READ ONLY Polling Register This read only register provides the low order vector address and is used to identify the source of interrupt if a polling technique, rather than interrupt servicing, is used. BUS 7 P7 P6 P5 POLLING REGISTER BITS P4 P3 P2 P1 BUS 0 P0 READ ONLY RESPONSE TO INTERRUPT (AFTER S3 CYCLE) The PIC’s response to interrogation by the CPU is always 3 bytes long, placed on the data bus in consecutive bytes in the following format: First (Instruction) Byte: LONG BRANCH INSTRUCTION - CO (Hex) BUS 7 1 1 0 0 0 0 0 BUS 0 0 4-86 CDP1877, CDP1877C Second (High-Order Address) Byte This byte is the High-Order vector Address that was written into the PIC’s Page Register by the user. The PIC does not alter this value in any way. High-Order Vector Address BUS 7 A15 A14 A13 A12 A11 A10 A9 BUS 0 A8 Third (Low-Order Address) Bytes INTERVAL 2 BUS 7 A7 INTERVAL 4 BUS 7 A7 INTERVAL 8 BUS 7 A7 INTERVAL 16 BUS 7 A7 I2 I1 I0 0 0 0 A6 I2 I1 I0 0 0 A6 A5 I2 I1 I0 0 A6 A5 A4 I2 I1 I0 BUS 0 0 BUS 0 0 BUS 0 0 BUS 0 0 Indicates active interrupt input number (binary 0 to 7). Bits indicated by AX (x = 4 to 7) are the same as programmed into the control register. All other bits are generated by the PIC. REGISTER ADDRESSES In order to read/write or obtain an interrupt vector from any PIC in the system, all chip selects (CS/AX, CS/AY, CS, CS) must be valid during TPA. CS/AX and CS/AY are multiplexed addresses; both must be high during TPA, and set according to this table during TPB to access the proper register. CS/AX 1 1 0 0 0 0 CS/AY 0 0 1 0 0 1 RD 0 1 1 0 1 0 WR 1 0 0 1 0 1 ACTION TAKEN READ Long Branch instruction and vector for highest priority unmasked interrupt pending. WRITE to Page Register WRITE to Control Register READ Status Register WRITE to Mask Register READ Polling Register (Used to identify INTERRUPT source if Polling technique rather than INTERRUPT service is used.) Unused condition 1 1 X X 4-87 CDP1877, CDP1877C PIC Application Examples Example 1 - Single PIC Application Figure 2 shows all the connections required between CPU and PIC to handle eight levels of interrupt control. MA7 MA6 MA5 CS/AX CS/AY CS CS CASC VDD CPU CDP1802 MA4 PIC CDP1877 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 MWR MRD TPA TPB INT BUS MWR MRD TPA TPB INT BUS FIGURE 2. PIC AND CPU CONNECTION DIAGRAM Programming Programming the PIC consists of the following steps: 1. Disable interrupt at CPU 2. Reset Master Interrupt Bit, B3, of Control Register. 3. Write a “1” into the Interrupt Input bit location of the Mask Register, if masking is desired. 4. Write the High-Order Address byte into the Page Register. 5. Write the Low-Order Address and the vector interval into the Control Register. 6. Program R(1) of the CPU to point to the PIC so that the Long Branch instruction can be read from the PIC during the Interrupt Service routine. Values for Example 1 with LOCATION 84E0 arbitrarily chosen as the Vector Address with interval of eight bytes, IR4 pending, is shown in Table 1. In deriving the above addresses, all Don’t Care bits are assumed to be 0. When an INTERRUPT (IR4) is received by the CPU, it will address the PIC and will branch to the interrupt service routine. The three bytes generated by the PIC will be: 1st Byte = C0H 2nd Byte = 84H 3rd Byte = E0H TABLE 1. REGISTER ADDRESS VALUES REGISTER MASK CONTROL PAGE STATUS POLLING R(1) (IN CPU) REGISTER ADDRESS E000H E040H E080H E000H E040H E080H OPERATION WRITE WRITE WRITE READ READ DATA BYTE 00H CEH 84H 10H E0H - 4-88 CDP1877, CDP1877C Example 2 - Multi-PIC Application Figure 3 shows all the connections required between CPU and PIC’s to handle sixteen levels of interrupt control. +V MA7 MA6 MA5 CS/AX CS/AY CS CS CASC PIC 1 CDP1877 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 HIGHEST PRIORITY INTERRUPT CPU CDP1802 MA1 MA0 MWR MRD TPA TPB INT BUS MWR MRD TPA TPB INT BUS CS/AX CS/AY CS CS MWR MRD TPA TPB INT BUS CASC PIC 2 IR7 CDP1877 IR6 IR5 IR4 IR3 IR2 IR1 IR0 LOWEST PRIORITY INTERRUPT FIGURE 3. PICs AND CPU CONNECTION DIAGRAM Register Address Assignments The low-byte register address for any WRITE or READ operation is the same as shown in Table 1. The High-Byte register differs for each PIC because of the linear addressing technique shown in the example: PIC 1 = 111XXX01 (E1H for X = 0) PIC 2 = 111XXX10 (E2H for X = 0) The R(1) vector address is unchanged. This address will select both PICs simultaneously (R(1). 1 = 111XXX00 = E0H). Internal CDP1877 logic controls which PIC will respond when an interrupt request is serviced. Additional PIC Application Comments The interval select options provide significant flexibility for interrupt routine memory allocations: • The 2-byte interval allows one to dedicate a full page to interrupt servicing, with variable space between routines, by specifying indirect vectoring with 2-byte short branch instructions on the current page. • The 4-byte interval allows for a 3-byte long branch to any location in memory where the interrupt service routine is located. The branch can be preceded by a Save Instruction to save previous contents of X and P on the stack. • The 8-byte and 16-byte intervals allow enough space to perform a service routine without indirect vectoring. The amount of interval memory can be increased even further if all 8 INTERRUPTS are not required. Thus a 4-level interrupt system could use alternate IR Inputs, and expand the interval to 16 and 32 bytes, respectively. • The 4 Chip Selects allow one to conserve total allotted memory space to the PIC. For one chip, a total of 4 address lines could be used to select the device, mapping it into as little as 4-K of memory space. Note that this selection technique is the only one that allows the PIC to work properly in the system: I/O mapping cannot be used because the PIC must work within the CDP1800 interrupt structure to define the vector address. Decoded signals also will not work because the chip selects must be valid on the trailing edge of TPA. 4-89 CDP1877, CDP1877C Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 50pF LIMITS CDP1877 PARAMETER Address to TPA Setup Time tAS VDD (V) 5 10 Address to TPA Hold Time tAH 5 10 Data Valid after TPB tDTPB 5 10 Data Hold Time from Write tHW 5 10 Address to Valid Data Access Time Data Setup Time to Write tDR 5 10 tDSU 5 10 Address Hold from TPB tHTPB 5 10 Minimum MWR Pulse Width tMWR 5 10 Minimum IR Pulse Width tIRX 5 10 NOTE: 1. Typical values are for TA = 25oC and VDD ±5%. MIN 60 40 60 40 370 210 30 40 0 0 80 40 130 60 130 60 (NOTE 1) TYP 310 340 125 MAX 490 230 MIN 60 60 370 30 0 80 130 130 CDP1877C (NOTE 1) TYP 340 MAX 490 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TPA tAS MEMORY ADDRESS HIGH BYTE tAH LOW BYTE tHTPB TPB MRD tDR DATA FROM PIC TO BUS VALID DATA tMWR MWR tDSU DATA FROM BUS TO PIC tIRX IRX VALID DATA tDH tDTPB FIGURE 4. TIMING WAVEFORMS FOR CDP1877 4-90 CDP1877, CDP1877C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-91