FSTYC9055R1

FSTYC9055D, FSTYC9055R TM Data Sheet June 2000 File Number 4755.1 Radiation Hardened, SEGR Resistant P-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Immunity to Single Event Effects (SEE) is combined with 100K RADs of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil for any desired deviations from the data sheet. Formerly available as type TA17750T. Features • 64A, -60V, rDS(ON) = 0.023Ω • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Typical SEE Immunity - LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 0V - LET of 26MeV/mg/cm2 with VDS up to 100% of Rated Breakdown and VGS of 5V Off-Bias • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 6nA Per-RAD (Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Symbol D G S Ordering Information RAD LEVEL 10K 10K 100K 100K 100K SCREENING LEVEL PART NUMBER/BRAND Commercial TXV Commercial TXV Space FSTYC9055D1 FSTYC9055D3 FSTYC9055R1 FSTYC9055R3 FSTYC9055R4 Packaging SMD2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 FSTYC9055D, FSTYC9055R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSTYC9055D, FSTYC9055R Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) -60 -60 64 41 192 ±20 162 65 1.30 192 64 192 -55 to 150 300 UNITS V V A A A V W W W/ oC A A A oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC MIN -60 -2.0 -1.0 TYP VGS = 0V to -20V VGS = 0V to -12V VGS = 0V to -2V VDD = -30V, ID = 64A ID = 64A, VDS = -15V VDS = -25V, VGS = 0V, f = 1MHz 0.016 160 51 31 -7 7100 2130 370 MAX -7.0 -6.0 25 250 100 200 -1.60 0.023 0.037 60 45 90 35 330 190 18 71 46 0.77 UNITS V V V V µA µA nA nA V Ω Ω ns ns ns ns nC nC nC nC nC V pF pF pF oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current IDSS IGSS VDS(ON) rDS(ON)12 td(ON) tr td(OFF) tf Qg(TOT) Qg(12) Qg(TH) Qgs Qgd V(PLATEAU) CISS COSS CRSS RθJC VDS = -48V, VGS = 0V VGS = ±20V VGS = -12V, ID = 64A ID = 41A, VGS = -12V Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate Charge at 12V Threshold Gate Charge Gate Charge Source Gate Charge Drain Plateau Voltage Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case VDD = -30V, ID = 64A, RL = 0.47Ω, VGS = -12V, RGS = 2.35Ω 2 FSTYC9055D, FSTYC9055R Source to Drain Diode Specifications PARAMETER Forward Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 64A ISD = 64A, dISD/dt = 100A/µs TC = 25oC, Unless Otherwise Specified SYMBOL (Note 3) (Note 3) (Notes 2, 3) (Note 3) (Notes 1, 3) (Notes 1, 3) BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON)12 TEST CONDITIONS VGS = 0, ID = 1mA VGS = VDS, ID = 1mA VGS = ±20V, VDS = 0V VGS = 0, VDS = -48V VGS = -12V, ID = 64A VGS = -12V, ID = 41A MIN -60 -2.0 MAX -6.0 100 25 -1.60 0.023 UNITS V V nA µA V Ω MIN -0.6 TYP MAX -1.8 120 UNITS V ns Electrical Specifications up to 100K RAD PARAMETER Drain to Source Breakdown Volts Gate to Source Threshold Volts Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts Drain to Source On Resistance NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TEST Single Event Effects Safe Operating Area SYMBOL SEESOA ION SPECIES Ni Br Br Br NOTES: 4. Testing conducted at Brookhaven National Labs; witnessed by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). TYPICAL LET (MeV/mg/cm) 26 37 37 37 TYPICAL RANGE (µ) 43 36 36 36 APPLIED VGS BIAS (V) 20 10 15 20 (NOTE 6) MAXIMUM VDS BIAS (V) -60 -60 -36 -24 Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43µ LET = 37MeV/mg/cm2, RANGE = 36µ -70 -60 -50 VDS (V) -40 -30 -20 -10 0 0 5 10 VGS (V) 15 20 25 TEMP = 25oC LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) 1E-3 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 1E-7 -10 -30 -100 DRAIN SUPPLY (V) -300 -1000 FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS 3 FSTYC9055D, FSTYC9055R Performance Curves 70 60 ID , DRAIN CURRENT (A) 50 ID , DRAIN (A) 40 30 20 10 0 -50 1 -1 100 100µs Unless Otherwise Specified (Continued) 500 TC = 25oC 1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -10 -100 VDS , DRAIN-TO-SOURCE VOLTAGE (V) -200 0 50 100 150 TC , CASE TEMPERATURE (oC) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = -12V, ID = 41A 2.0 -12V QG NORMALIZED rDS(ON) 1.5 QGS VG QGD 1.0 0.5 CHARGE 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 5. BASIC GATE CHARGE WAVEFORM 10 FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE THERMAL RESPONSE (ZθJC) 1 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-3 10-2 10-1 PDM NORMALIZED 0.1 t1 t2 100 101 0.001 10-5 10-4 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 4 FSTYC9055D, FSTYC9055R Performance Curves Unless Otherwise Specified 500 IAS , AVALANCHE CURRENT (A) (Continued) 100 STARTING TJ = 25oC STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 10 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS VARY tP TO OBTAIN REQUIRED PEAK IAS 0V tP 50W VGS ≤ 20V tAV IAS 50Ω + VDD 50V-150V BVDSS tP VDS VDD DUT FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD td(ON) tr RL VDS 0V DUT 10% VDS 90% tOFF td(OFF) tf 90% 10% 90% VGS = -12V RGS VGS 10% 50% PULSE WIDTH 50% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS 5 FSTYC9055D, FSTYC9055R Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER Gate to Source Leakage Current Zero Gate Voltage Drain Current Drain to Source On Resistance Gate Threshold Voltage NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS VGS = ±20V VDS = 80% Rated Value TC = 125oC at Rated ID ID = 1.0mA MAX ±20 (Note 7) ±25 (Note 7) ±20% (Note 8) ±20% (Note 8) UNITS nA µA Ω V Screening Information TEST Gate Stress Pind Pre Burn-In Tests (Note 9) Steady State Gate Bias (Gate Stress) Interim Electrical Tests (Note 9) Steady State Reverse Bias (Drain Stress) PDA Final Electrical Tests (Note 9) NOTE: 9. Test limits are identical pre and post burn-in. JANTXV EQUIVALENT VGS = -30V, t = 250µs Optional MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours 10% MIL-S-19500, Group A, Subgroup 2 JANS EQUIVALENT VGS = -30V, t = 250µs Required MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours 5% MIL-S-19500, Group A, Subgroups 2 and 3 Additional Screening Tests PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL SOA IAS ∆VSD ∆VSD TEST CONDITIONS VDS = -48V, t = 10ms VGS(PEAK) = -15V, L = 0.1mH tH = 10ms; VH = -25V; IH = 4A tH = 500ms; VH = -20V; IH = 4A MAX 9.0 192 65 135 UNITS A A mV mV 6 FSTYC9055D, FSTYC9055R Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A E. Group B F. Group C G. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet Class S - Equivalents 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Pre and Post Burn-In Read and Record Data D. Group A E. Group B - Attributes Data Sheet - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) - Attributes Data Sheet - Pre and Post RAD Read and Record Data 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Subgroups A2, A3, A4, A5 and A7 Data - Attributes Data Sheet - Subgroups B1, B3, B4, B5 and B6 Data - Attributes Data Sheet - Subgroups C1, C2, C3 and C6 Data - Attributes Data Sheet - Pre and Post Radiation Data F. Group C G. Group D 7 FSTYC9055D, FSTYC9055R SMD2 3 PAD CERAMIC LEADLESS CHIP CARRIER E INCHES SYMBOL A b D MIN 0.130 0.135 0.520 0.435 0.115 0.685 0.470 0.152 MAX 0.142 0.145 0.530 0.445 0.125 0.695 0.480 0.162 MILLIMETERS MIN 3.30 3.43 13.20 11.05 2.92 17.40 11.94 3.86 MAX 3.60 3.68 13.46 11.30 3.17 17.65 12.19 4.11 NOTES 3 - D D1 D2 E E1 E2 NOTES: A E1 E2 1. 2. 3. 4. No current JEDEC outline for this package. Controlling dimension: INCH. Measurement prior to pre-solder coating the mounting pads. Revision 3 dated 5-00. 2 3 D2 D1 1 b 1 - GATE 2 - SOURCE 3 - DRAIN All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 8