HA1-2540-5

® HA-2540 Data Sheet July 2003 FN2897.5 400MHz, Fast Settling Operational Amplifier The Intersil HA-2540 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is 10 or greater. Additionally, the HA-2540 has a drive capability of ±10V into a 1kΩ load. Other desirable characteristics include low input voltage noise, low offset voltage, and fast settling time. A 400V/µs slew rate ensures high performance in video and pulse amplification circuits, while the 400MHz gainbandwidth product is ideally suited for wideband signal amplification. A settling time of 140ns also makes the HA-2540 an excellent selection for high speed Data Acquisition Systems. Refer to Application Note AN541 and Application Note AN556 for more information on High Speed Op Amp applications. For a lower power version of this product, please see the HA-2850 datasheet. Features • Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 400V/µs • Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 140ns • Wide Gain Bandwidth (AV ≥ 10). . . . . . . . . . . . . . 400MHz • Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MHz • Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mV • Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz • Output Voltage Swing . . . . . . . . . . . . . . . . . . . . . . . ±10V • Monolithic Bipolar Construction Applications • Pulse and Video Amplifiers • Wideband Amplifiers • High Speed Sample-Hold Circuits • Fast, Precise D/A Converters Ordering Information PART NUMBER HA1-2540-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 14 Ld CERDIP PKG. DWG. # F14.3 Pinout HA-2540 (CERDIP) TOP VIEW NC 1 NC 2 NC 3 -IN 4 +IN 5 V- 6 NC 7 + 14 NC 13 NC 12 NC 11 V+ - 10 OUTPUT 9 NC 8 NC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-2540 Absolute Maximum Ratings Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Output Current . . . . . . . . . . . . . . 33mARMS Continuous, 50mAPEAK Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 Maximum Internal Power Dissipation (Note 1) Maximum Junction Temperature (Ceramic Package) . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range HA-2540-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175oC for the ceramic package, and below 150oC for the plastic package. By using Application Note AN556 on Safe Operating Area Equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75oC. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications INPUT CHARACTERISTICS Offset Voltage VSUPPLY = ±15V, RL = 1kΩ , CL < 10pF, Unless Otherwise Specified PARAMETER TEMP (oC) MIN TYP MAX UNITS 25 Full ±10 - 8 13 20 5 1 10 1 6 6 15 20 20 25 6 8 - mV mV µV/oC µA µA µA µA kΩ pF V pA/√Hz nV/√Hz Average Offset Voltage Drift Bias Current Full 25 Full Offset Current 25 Full Input Resistance Input Capacitance Common Mode Range Input Noise Current (f = 1kHz, RSOURCE = 0Ω) Input Noise Voltage (f = 1kHz, RSOURCE = 0Ω) TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) 25 25 Full 25 25 25 Full 10 5 60 10 - 15 72 400 - kV/V kV/V dB V/V MHz Common-Mode Rejection Ratio (Note 4) Minimum Stable Gain Gain Bandwidth Product (Notes 5, 6) OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, 10) Output Current (Note 3) Output Resistance Full Power Bandwidth (Notes 3, 7) TRANSIENT RESPONSE (Note 8) Rise Time Overshoot Slew Rate Settling Time: 10V Step to 0.1% Full 25 25 Full 25 25 25 ±10 ±10 5.5 ±20 30 6 - V mA Ω MHz 25 25 25 25 320 - 14 5 400 140 - ns % V/µs ns 2 HA-2540 Electrical Specifications POWER REQUIREMENTS Supply Current Power Supply Rejection Ratio (Note 9) Full Full 60 20 70 25 mA dB VSUPPLY = ±15V, RL = 1kΩ , CL < 10pF, Unless Otherwise Specified (Continued) PARAMETER TEMP (oC) MIN TYP MAX UNITS NOTES: 3. RL = 1kΩ, VO = ±10V. 4. VCM = ±10V. 5. VO = 90mV. 6. AV = 10. Slew Rate 7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = --------------------------- . 2 π V PEAK 8. Refer to Test Circuits section of the data sheet. 9. VSUPPLY = +5V, -15V and +15V, -5V. 10. Guaranteed range for output voltage is ±10V. Functional operation outside of this range is not guaranteed. Test Circuits and Waveforms VIN + - VOUT 900 NOTES: 100 11. AV = +10. 12. CL ≤ 10pF. FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT A B Vertical Scale: A = 0.5V/Div., B = 5.0V/Div. Horizontal Scale: 50ns/Div. LARGE SIGNAL RESPONSE Vertical Scale: Input = 10mV/Div.; Output = 50mV/Div. Horizontal Scale: 20ns/Div. SMALL SIGNAL RESPONSE V+ 0.001µF NOTES: 13. AV = -10. 14. Load Capacitance should be less than 10pF. Turn on time delay typically 4ns. 15. It is recommended that resistors be carbon composition and the feedback and summing network ratios be matched to 0.1%. PROBE MONITOR INPUT 200Ω + 1 µF - OUTPUT 0.001µF 500Ω 1 µF 2kΩ 5kΩ VSETTLE POINT 16. SETTLE POINT (Summing Node) capacitance should be less than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. FIGURE 2. SETTLING TIME TEST CIRCUIT 3 HA-2540 Schematic Diagram R23 QP22 QP19 R24 VQP25 R22 VQN2 QN1 R6 + INPUT R7 QP8 R18 OUTPUT QP23 QN21 R8 QP3 - INPUT R21 Z1 R25 V+ R10 QN20 DZ1 DZ2 QN14 R11 R12 QN29 R14 QN15 R16 QN13 QN16 R15 R17 V+ QN25 QP4 R9 QN10 R19 QP11 C1 C2 RC2 QN7 QN9 QP17 R13 QP5 R5 R1 QP18 R2 QP28 R3 R4 QP6 V+ QN12 V- Typical Applications 2K 200 + C1 (NOTE 18) 10K R2 4K SIGNAL OUT R1 4K V+ - 1K HA-2540 V+ OFFSET ADJUST VR5 (NOTE 19) 2K CF (NOTE 17) HA-2540 0.1µF R3 4K R4 4K 1K + - NOTES: NOTE: With one HA-2540 and two low capacitance switching diodes, signals exceeding 10MHz can be separated. This circuit is most useful for full wave rectification, AM detectors or sync generation. FIGURE 3. WIDEBAND SIGNAL SPLITTER V- 17. Used for experimental purposes. CF ≅ 3pF. 18. C1 is optional (0.001µF → 0.01µF ceramic). 19. R5 is optional and can be utilized to reduce input signal amplitude and/or balance input conditions. R5 = 500Ω to 1kΩ. FIGURE 4. BOOTSTRAPPING FOR MORE OUTPUT CURRENT AND VOLTAGE SWING Refer to Application Note AN541 For Further Application Information. 4 HA-2540 Typical Performance Curves 100 OUTPUT VOLTAGE SWING (VP-P) 90 CLOSED LOOP GAIN (dB) 80 70 60 50 40 30 20 10 0 -10 100 1K 10K 100K 1M 10M 100M 28 24 20 16 12 8 4 0 1K VS = ±5V VS = ±10V VS = ±15V 10K 100K 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. CLOSED LOOP FREQUENCY RESPONSE FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY NORMALIZED PARAMETERS REFERRED TO VALUES AT 25oC 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -80 SLEW RATE BANDWIDTH OUTPUT VOLTAGE SWING (VP-P) 28 24 20 16 12 8 4 0 0 200 400 600 800 1K 1.2K RESISTANCE (Ω) -40 0 40 80 120 160 TEMPERATURE (oC) FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 8. NORMALIZED AC PARAMETERS vs TEMPERATURE 28 10 OUTPUT VOLTAGE STEP (V) 8 6 4 2 0 -2 -4 -6 -8 -10 0 40 80 120 160 200 240 0 -80 -40 0 40 80 120 160 10mV 1mV SUPPLY CURRENT (mA) 1mV 10mV 24 20 16 12 8 4 VS = ±15V VS = ±5V SETTLING TIME (ns) TEMPERATURE (oC) FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE 5 HA-2540 Typical Performance Curves 14 12 INPUT BIAS CURRENT (µA) 10 8 6 4 BIAS CURRENT 2 0 -80 OFFSET VOLTAGE (Continued) 7 RSOURCE = 0Ω , VS = ±15 |VIO| OFFSET VOLTAGE (mV) 6 5 4 3 2 1 0 160 25 NOISE VOLTAGE (nV/√Hz) 50 NOISE CURRENT (pA/√Hz) 10M PHASE (DEGREES) 20 40 15 CURRENT NOISE 30 10 VOLTAGE NOISE 5 20 10 -40 0 40 80 120 0 10 100 TEMPERATURE (oC) 1K FREQUENCY (Hz) 10K 0 100K FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUENCY +40µV +30µV +20µV CMRR (dB) +10µV 0µV -10µV -20µV -30µV -40µV 120 100 80 60 40 20 VS = ±15, RL = 1K Vertical Scale: 10mV/Div. Horizontal Scale: 50ms/Div. FIGURE 13. BROADBAND NOISE (0.1Hz TO 1MHz) 0 1K 10K 100K FREQUENCY (Hz) 1M FIGURE 14. COMMON MODE REJECTION RATIO vs FREQUENCY 100 100 0 80 OPEN LOOP GAIN (dB) 80 GAIN 60 PHASE 90 40 135 20 180 0 45 PSRR (dB) 60 POSITIVE SUPPLY 40 NEGATIVE SUPPLY 20 0 1K 10K 100K FREQUENCY (Hz) 1M 10M -10 100 225 1K 10K 100K 1M 10M FREQUENCY (Hz) 100M FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUENCY FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUENCY 6 HA-2540 Die Characteristics DIE DIMENSIONS: 62 mils x 76 mils x 19 mils 1575 µmx 1930µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 30 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-2540 V+ OUTPUT V- -IN +IN - IN + IN 7 HA-2540 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8