HA3-5142-5

HA-5142 DU C T NT E PRO T E CE M E a t L A O L P E OBS R Center ND E D OMME ical Support .com/tsc C E R NO hn Data November 16, 2004 ersil ecSheet ww.int t o ur T contac TERSIL or w IN 1-888® FN2909.5 Dual, 400kHz, Ultra-Low Power Operational Amplifier Features The HA-5142 ultra-low power operational amplifier provides AC and DC performance characteristics similar to or better than most general purpose amplifiers while only drawing 1/30 of the supply current of most general purpose amplifiers. In applications which require low power dissipation and good AC electrical characteristics, this device offers the industry’s best speed/power ratio. • Wide Supply Voltage Range Single . . . . . . . . . 3V to 30V - or Dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5V to ±15V • Low Supply Current . . . . . . . . . . . . . . . . . . . . . 45µA/Amp The HA-5142 provides accurate signal processing by virtue of its low input offset voltage (2mV), low input bias current (45nA), high open loop gain (100kV/V) and low noise (20nV/√Hz), for low power operational amplifiers. These characteristics coupled with a 1.5V/µs slew rate and a 400kHz bandwidth make the HA-5142 ideal for use in low power instrumentation, audio amplifier and active filter designs. The wide range of supply voltages (3V to 30V) also allow this amplifier to be very useful in low voltage battery powered equipment. This device is also tested and guaranteed at both ±15V and single ended +5V supplies. This amplifier is available with industry standard pinouts which allow the HA-5142 to be interchangeable with most other dual operational amplifiers. For military grade product refer to the HA-5142/883 data sheet. • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V/µs • High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100kV/V • Unity Gain Stable Applications • Portable Instruments • Meter Amplifiers • Telephone Headsets • Microphone Amplifiers • Instrumentation - For Further Design Ideas See Application Note 544 Part Number Information PART NUMBER TEMP. RANGE (oC) HA3-5142-5 0 to 75 HA7-5142-2 -55 to 125 PACKAGE PKG. DWG. # 8 Ld PDIP E8.3 8 Ld CERDIP F8.3A Pinout HA-5142 (PDIP, CERDIP) TOP VIEW OUT1 1 -IN1 2 1 - +IN1 V- 3 + 2 - + 4 1 8 V+ 7 OUT2 6 -IN2 5 +IN2 FN2912 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1-888-INTERSIL or 321-724-7143 HA-5142 Schematic Diagram V+ OUTPUT -IN +IN V+ V- 2 HA-5142 Absolute Maximum Ratings Thermal Information Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) 8 Lead PDIP Package . . . . . . . . . . . . . 120 N/A 8 Lead CERDIP Package. . . . . . . . . . . 135 50 Maximum Junction Temperature (Hermetic Packages) . . . . . . .175oC Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range HA-5142-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HA-5142-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. RS = 100Ω, CL ≤ 10pF, Unless Otherwise Specified Electrical Specifications -2, -5 V+ = +5V, V- = 0V -2, -5 V+ = +15V, V- = -15V TEST CONDITIONS TEMP. (oC) MIN TYP MAX MIN TYP MAX UNITS Note 11 25 - 2 6 - 2 6 mV Full - - 8 - - 8 mV Full - 3 - - 3 - µV/oC 25 - 45 100 - 45 100 nA Full - - 125 - - 125 nA 25 - 0.3 10 - 0.3 10 nA Full - - 20 - - 20 nA Common Mode Range Full 0 to 3 - - ±10 - - V Differential Input Resistance 25 - 0.6 - - 0.6 - MΩ PARAMETER INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Note 11 Offset Current Note 11 Input Noise Voltage f = 1kHz 25 - 20 - - 20 - nV/√Hz Input Noise Current f = 1kHz 25 - 0.25 - - 0.25 - pA/√Hz Notes 2, 4 25 20 100 - 20 100 - kV/V Full 15 - - 15 - - kV/V Note 7 Full 77 105 - 77 105 - dB Notes 2, 3 25 - 0.4 - - 0.4 - MHz Notes 2, 10 25 1.0 to 3.8 0.7 to 4.2 - ±10 ±13 - V Full 1.2 to 3.5 0.9 to 4.0 - ±10 ±13 - V 25 - 240 - - 24 - kHz TRANSFER CHARACTERISTICS Large Signal Voltage Gain Common Mode Rejection Ratio Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing Full Power Bandwidth Notes 2, 4, 8 3 HA-5142 RS = 100Ω, CL ≤ 10pF, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS PARAMETER -2, -5 V+ = +5V, V- = 0V -2, -5 V+ = +15V, V- = -15V TEMP. (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 600 - - 600 - ns TRANSIENT RESPONSE (Notes 2, 3) Rise Time Slew Rate Note 6 25 0.8 1.5 - 0.8 1.5 - V/µs Settling Time Note 5 25 - 10 - - 10 - µs 25 - 45 80 - 100 150 µA/Amp Full - - 100 - - 200 µA/Amp Full 77 105 - 77 105 - dB POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio Note 9 NOTES: 2. RL = 50kΩ. 3. CL = 50pF. 4. VO = 1.4 to 2.5V for VSUPPLY = +5, 0V; VO = ±10V for VSUPPLY = ±15V. 5. Settling Time is specified to 0.1% of final value for a 3V output step and AV = -1 for VSUPPLY = +5V, 0V. Output step = 10V for VSUPPLY = ±15V. 6. Maximum input slew rate = 10V/µs. 7. VCM = 0 to 3V for VSUPPLY = +5, 0V; VCM = ±10V for VSUPPLY = ±15V. Slew Rate 8. Full Power Bandwidth is guaranteed by equation: FPBW = --------------------------- . 2πV PEAK 9. ∆VS = +10V for VSUPPLY = +5, 0V; ∆VS = ±5V for VSUPPLY = ±15V. 10. For VSUPPLY = +5, 0V terminate RL at +2.5V. Typical output current is ±3mA. 11. VO = 1.4V for VSUPPLY = +5V, 0V. 4 HA-5142 Test Circuits and Waveforms IN + OUT 50kΩ 50pF FIGURE 1. SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT INPUT INPUT OUTPUT OUTPUT +VSUPPLY = +15V, -VSUPPLY = -15V +VSUPPLY = +15V, -VSUPPLY = -15V Vertical Scale: Input = 5V/Div.; Output = 2V/Div. Horizontal Scale: 2µs/Div. Vertical Scale: Input = 100mV/Div.; Output = 50mV/Div. Horizontal Scale: 2µs/Div. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE INPUT INPUT OUTPUT OUTPUT +VSUPPLY = +5V, -VSUPPLY = 0V +VSUPPLY = +5V, -VSUPPLY = 0V Vertical Scale: Input = 2V/Div.; Output = 1V/Div. Horizontal Scale: 5µs/Div. Vertical Scale: Input = 100mV/Div.; Output = 50mV/Div. Horizontal Scale: 5µs/Div. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE 5 HA-5142 Typical Performance Curves VS = ±2.5V, TA = 25oC, Unless Otherwise Specified 70 90 CL = 50pF GAIN 20 0 70 20 60 40 50 50 16 60 PHASE 40 80 30 100 20 120 10 140 0 160 IB (nA) 80 24 40 12 30 10 100 1K 10K 100K 4 10 -40 -60 1M -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FREQUENCY (Hz) FIGURE 2. OPEN LOOP FREQUENCY RESPONSE FIGURE 3. INPUT OFFSET CURRENT AND BIAS CURRENT vs TEMPERATURE 100o 80o 0.4 60o 0.3 PHASE MARGIN 40o 0.2 20o 0.1 UNITY BANDWIDTH (MHz) RL = 50kΩ NORMALIZED AC PARAMETERS REFERRED TO VALUE AT ±2.5V 1.6 BANDWIDTH PHASE MARGIN 8 INPUT OFFSET CURRENT 20 180 -10 1 INPUT BIAS CURRENT 60 |IOS| (nA) 100 RL = 50kΩ PHASE (DEGREES) OPEN LOOP VOLTAGE GAIN (dB) 110 RL = 50kΩ CL = 50pF 1.4 SLEW RATE 1.2 1.0 BANDWIDTH 0.8 0.6 0.4 0o 10 100 ±1 0 1000 ±2 FIGURE 4. BANDWIDTH AND PHASE MARGIN vs LOAD CAPACITANCE VSUPPLY = +10V 10 8 6 VSUPPLY = +5V 4 VSUPPLY = +3V 2 VSUPPLY = +2.5V 10K 100K 1M FREQUENCY (Hz) FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY AND SINGLE SUPPLY VOLTAGE 6 ±6 ±7 ±8 ±9 ±10 RL = 50kΩ SLEW RATE 1.1 1.0 0.9 BANDWIDTH 0.8 0.7 0.6 0 1K ±5 CL = 50pF NORMALIZED PARAMETERS REFERRED TO VALUE AT 25oC OUTPUT VOLTAGE SWING (VP-P) 1.2 VSUPPLY = +15V 12 ±4 FIGURE 5. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE 14 RL = 50kΩ ±3 SUPPLY VOLTAGE (V) LOAD CAPACITANCE (pF) -60 -40 -20 -10 0 20 40 60 80 TEMPERATURE (oC) FIGURE 7. NORMALIZED AC PARAMETERS vs TEMPERATURE 100 120 HA-5142 Typical Performance Curves VS = ±2.5V, TA = 25oC, Unless Otherwise Specified NOISE CURRENT NOISE VOLTAGE 10 1 1 10 100 1K 10K 100 16 OUTPUT VOLTAGE SWING (VP-P) INPUT NOISE VOLTAGE (nV/√Hz) 1000 100 INPUT NOISE CURRENT (10-15A/√Hz) 10,000 1000 VSUPPLY = +20V 14 12 VSUPPLY = +10V 10 8 6 VSUPPLY = +5V 4 2 10 100K VSUPPLY = +3V FREQUENCY (Hz) 100 FIGURE 8. INPUT NOISE vs FREQUENCY 1K 10K 100K FIGURE 9. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD RESISTANCE AND SINGLE SUPPLY VOLTAGE 140 SUPPLY CURRENT PER AMPLIFIER (µA) 80 120 100 80 -PSRR 60 40 +PSRR, CMRR 20 0 10 100 1K 10K 100K 70 60 50 VS = +5V 40 30 VS = +2V VS = +3V 20 10 -60 1M VS = +30V -40 -20 0 FIGURE 10. PSRR AND CMRR vs FREQUENCY 40 60 80 100 120 140 FIGURE 11. POWER SUPPLY CURRENT vs TEMPERATURE AND SINGLE SUPPLY VOLTAGE -140 -120 100kΩ -100 1kΩ - -80 + -60 -40 1kΩ 100kΩ 1kΩ - 0 100 VO1  V O2  - CS = 20 LOG  ---------------------- 100 V O1 VO2 + -20 1kΩ 1K 10K FREQUENCY (Hz) FIGURE 12. CHANNEL SEPARATION vs FREQUENCY 7 20 TEMPERATURE (oC) FREQUENCY (Hz) CHANNEL SEPARATION (dB) PSRR, CMRR (dB) (Continued) 100K HA-5142 Die Characteristics DIE DIMENSIONS: TRANSISTOR COUNT: 104 mils x 55 mils x 19 mils 2650µm x 1400µm x 483µm 72 SUBSTRATE POTENTIAL (POWERED UP): METALLIZATION: V- Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PROCESS: Bipolar/JFET Dielectric Isolation PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-5142 V- +IN2 +IN1 -IN2 OUT2 8 -IN1 NC OUT1 V+ HA-5142 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 9 5 D1 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 8 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 HA-5142 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) LEAD FINISH c1 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 eA e ccc M C A-B S eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 8 8 5. This dimension allows for off-center lid, meniscus, and glass overrun. 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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