HFA1205IP

TM CT RODU NT LETE P EPLACEME at OBSO DED R nt er EN rt Ce /tsc COMM Suppo NO RE rSheetnical .intersil.com Data Tech ww t ou contac TERSIL or w IN 1- 888- HFA1205 July 2004 FN3605.6 Dual, 425MHz, Low Power, Video Operational Amplifier The HFA1205 is a dual, high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. These amplifiers deliver 425MHz bandwidth and 1350V/µs slew rate, on only 60mW of quiescent power. They are specifically designed to meet the performance, power, and cost requirements of high volume video applications. The excellent gain flatness and differential gain/phase performance make these amplifiers well suited for component or composite video applications. Video performance is maintained even when driving a back terminated cable (RL = 150Ω), and degrades only slightly when driving two back terminated cables (RL = 75Ω). RGB applications will benefit from the high slew rates, and high full power bandwidth. The HFA1205 is a pin compatible, low power, high performance upgrade for the popular Intersil HA5023. For a dual amplifier with output disable capability, please see the HFA1245 data sheet. Features • Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 2MΩ • Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 425MHz • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 1350V/µs • Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . . . . ±0.04dB • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% • Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • Pin Compatible Upgrade to HA5023 Applications • Flash A/D Drivers • High Resolution Monitors • Video Switching and Routing • Professional Video Processing • Video Digitizing Boards/Systems • Multimedia Systems • RGB Preamps Part # Information PART NUMBER (BRAND) HFA1205IP HFA1205IB (H1205I) HA5023EVAL TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld SOIC PKG. NO. E8.3 M8.15 • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications • High Speed Oscilloscopes and Analyzers High Speed Op Amp DIP Evaluation Board Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Pinout HFA1205 (PDIP, SOIC) TOP VIEW OUT1 -IN1 +IN1 V1 2 3 4 + + 8 7 6 5 V+ OUT2 -IN2 +IN2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. Copyright © Intersil Corporation 2000, 2004 HFA1205 Absolute Maximum Ratings Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 2) . . . . . . . . . . . . . . . . . Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. VSUPPLY = ±5V, AV = +1, RF = 560Ω , RL = 100Ω , Unless Otherwise Specified (NOTE 3) TEST LEVEL TEMP. (oC) Electrical Specifications PARAMETER INPUT CHARACTERISTICS Input Offset Voltage TEST CONDITIONS MIN TYP MAX UNITS A A 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 45 43 43 48 46 46 0.8 0.5 0.5 - 2 3 1 48 46 46 52 50 50 6 10 5 0.5 0.8 0.8 2 1.3 1.3 2 5 60 3 4 4 5 8 10 15 25 60 1 3 3 8.5 15 200 6 8 8 mV mV µV/ oC dB dB dB dB dB dB µA µA nA/ oC µA/V µA/V µA/V MΩ MΩ MΩ µA µA nA/ oC µA/V µA/ V µA/V Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Input Offset Voltage Power Supply Rejection Ratio ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Non-Inverting Input Bias Current B A A A A A A A A Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Non-Inverting Input Resistance ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Inverting Input Bias Current B A A A A A A A A Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V B A A A 2 HFA1205 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 560Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL A A A C C A A f = 100kHz B B B TEMP. (oC) 25 85 -40 25 25 25, 85 -40 25 25 25 PARAMETER Inverting Input Bias Current Power Supply Sensitivity TEST CONDITIONS ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V MIN ±1.8 ±1.2 - TYP 2 4 4 55 1.5 ±2.4 ±1.7 3.5 2.5 25 MAX 5 8 8 - UNITS µA/V µA/V µA/V Ω pF V V nV/√Hz pA/√Hz pA/√Hz kΩ Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) Input Noise Voltage Density (Note 6) Non-Inverting Input Noise Current Density (Note 6) f = 100kHz Inverting Input Noise Current Density (Note 6) TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain (Note 6) AC CHARACTERISTICS AV = +2, RF = 464Ω , Unless Otherwise Specified AV = +1, +RS = 432Ω A V = +2 AV = -1, RF = 332Ω Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 6) Gain Flatness (AV = +2,VOUT = 0.2VP-P, Note 6) AV = +1, RS = 432Ω A V = +2 AV = -1, RF = 332Ω To 25MHz To 50MHz To 100MHz Minimum Stable Gain Crosstalk (AV = +2, Note 6) OUTPUT CHARACTERISTICS Output Voltage Swing (Note 6) AV = -1, RL = 100Ω RF = 560Ω AV = -1, RL = 50Ω RF = 560Ω RF = 560Ω DC, AV = +2, RF = 464Ω 10MHz 20MHz 10MHz 20MHz 5MHz 10MHz f = 100kHz C 25 - 400 - -3dB Bandwidth (VOUT = 0.2VP-P, Note 6) B B B B B B B B B A B B 25 25 25 25 25 25 25 25 25 Full 25 25 ±3 ±2.8 50 28 - 300 425 350 135 130 200 ±0.04 ±0.04 ±0.07 1 -60 -54 ±3.5 ±3 60 42 90 0.07 -53 -45 -55 -50 - MHz MHz MHz MHz MHz MHz dB dB dB V/V dB dB A A A A B B B B B B 25 Full 25, 85 -40 25 25 25 25 25 25 - V V mA mA mA Ω dBc dBc dBc dBc Output Current (Note 6) Output Short Circuit Current Closed Loop Output Impedance (Note 6) Second Harmonic Distortion (AV = +2, RF = 464Ω, VOUT = 2VP-P) Third Harmonic Distortion (AV = +2, RF = 464Ω, VOUT = 2VP-P) TRANSIENT CHARACTERISTICS AV = +2, RF = 464Ω, Unless Otherwise Specified Rise Time Fall Time B B B B B B 25 25 25 25 25 25 1.0 1.4 5 4 5 10 ns ns % % % % Rise and Fall Times (VOUT = 0.5VP-P) Overshoot (VOUT = 0 to 0.5V, VIN tRISE = 1ns, Note 4) Overshoot (VOUT = 0.5VP-P, VIN tRISE = 1ns, Note 4) +OS -OS +OS -OS 3 HFA1205 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 560Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL B B B B B B B B B B TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 PARAMETER Slew Rate (VOUT = 4VP-P, AV = +1, +RS = 432Ω) Slew Rate (VOUT = 5VP-P, AV = +2) Slew Rate (VOUT = 5VP-P, AV = -1, RF = 332Ω) Settling Time (VOUT = +2V to 0V step, Note 6) TEST CONDITIONS +SR -SR (Note 5) +SR -SR (Note 5) +SR -SR (Note 5) To 0.1% To 0.05% To 0.025% VIN = ±2V MIN - TYP 1150 800 1425 900 2400 1350 23 33 85 10 MAX - UNITS V/µs V/µs V/µs V/µs V/µs V/µs ns ns ns ns Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz) AV = +2, RF = 464Ω, Unless Otherwise Specified RL = 150Ω RL = 75Ω RL = 150Ω RL = 75Ω B B B B 25 25 25 25 ±4.5 5.6 5.4 0.03 0.03 0.03 0.05 ±5.5 6.1 6.3 % % Degrees Degrees Differential Phase (f = 3.58MHz) POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 6) C A A NOTES: 3. Test Level: A. Production Tested.; B. Typical or Guaranteed Limit Based on Characterization.; C. Design Typical for Information Only. 4. Undershoot dominates for output signal swings below GND (e.g., 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 0.5V condition. See the “Application Information “section for details. 5. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” text, and the pulse response graphs for details. 6. See Typical Performance Curves for more information. 25 25 Full 5.8 5.9 V mA/ Op Amp mA/ Op Amp Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF . The HFA1205 design is optimized for a 464Ω RF at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. Table 1 lists recommended RF values for various gains, and the expected bandwidth. For good channel-to-channel gain matching, it is recommended that all resistors (termination as well as gain setting) be ±1% tolerance or better. Note that a series input resistor, on +IN, is required for a gain of +1, to reduce gain peaking and increase stability. TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (ACL ) -1 +1 +2 +5 +10 RF (Ω) 332 464 (+RS = 432Ω) 464 215 180 BANDWIDTH (MHz) 350 300 425 270 115 4 HFA1205 Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 425MHz (for AV = +2). By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. For example, at AV = +2, RS = 50Ω , CL = 22pF, the overall bandwidth is limited to 230MHz, and bandwidth drops to 80MHz at AV = +2, RS = 7Ω , CL = 390pF. 50 A V = +2 SERIES OUTPUT RESISTANCE (Ω) 40 Pulse Undershoot and Asymmetrical Slew Rates The HFA1205 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figures 7, 11, 15 and 19). This undershoot isn’t present for small bipolar signals, or large positive signals (see Figures 5, 6, 9, 10, 13, 14, 17 and 18). Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (see Figures 7, 11, 15, and 19), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (see Figures 5, 9, 13 and 17). 30 20 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. Reduce this capacitance by removing the ground plane under traces connected to IN, and keep connections to -IN as short as possible. 10 0 0 50 100 150 200 250 300 350 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1205 may be evaluated using the HA5023 Evaluation Board. The performance of the HFA1205IB (SOIC) may be evaluated using the HA5023 Evaluation Board and a SOIC to DIP adaptor like the Aries Electronics Part Number 08-350000-10. The schematic for amplifier 1 and the board layout are shown in Figure 2 and Figure 3. Resistors RF, RG and RS may require a change to the appropriate value (see “Optimum Feedback Resistor” section) for the gain being evaluated. To order evaluation boards (Part Number HA5023EVAL), please contact your local sales office. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. 5 HFA1205 50Ω OUT RG IN 3 50Ω RS 4 5 GND RF 2 + 7 6 GND 1 8 0.1µF +5V 10µF −5V 10µF 0.1µF FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC FIGURE 3A. TOP LAYOUT FIGURE 3B. BOTTOM LAYOUT FIGURE 3. EVALUATION BOARD LAYOUT 6 HFA1205 Typical Performance Curves 300 AV = +2 250 OUTPUT VOLTAGE (mV) VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified 3.0 AV = +2 2.5 OUTPUT VOLTAGE (V) 200 150 100 50 0 -50 -100 TIME (5ns/DIV.) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) FIGURE 4. SMALL SIGNAL POSITIVE PULSE RESPONSE 200 AV = + 2 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 A V = +2 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 6. SMALL SIGNAL BIPOLAR PULSE RESPONSE 300 AV = + 1 250 200 OUTPUT VOLTAGE (mV) 150 100 50 0 -50 -100 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) FIGURE 7. LARGE SIGNAL BIPOLAR PULSE RESPONSE 3.0 A V = +1 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) FIGURE 8. SMALL SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL POSITIVE PULSE RESPONSE 7 HFA1205 Typical Performance Curves VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 200 AV = + 1 150 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) 2.0 A V = +1 1.5 1.0 OUTPUT VOLTAGE (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 OUTPUT VOLTAGE (mV) TIME (5ns/DIV.) FIGURE 10. SMALL SIGNAL BIPOLAR PULSE RESPONSE 300 AV = - 1 250 200 OUTPUT VOLTAGE (mV) 150 100 50 0 -50 -100 TIME (5ns/DIV.) FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE 3.0 AV = -1 2.5 2.0 OUTPUT VOLTAGE (V) 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) FIGURE 12. SMALL SIGNAL POSITIVE PULSE RESPONSE FIGURE 13. LARGE SIGNAL POSITIVE PULSE RESPONSE 8 HFA1205 Typical Performance Curves 200 AV = - 1 150 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 AV = -1 OUTPUT VOLTAGE (mV) FIGURE 14. SMALL SIGNAL BIPOLAR PULSE RESPONSE 300 250 A V = +5 OUTPUT VOLTAGE (mV) 200 AV = +10 150 100 50 A V = +5 0 -50 -100 TIME (5ns/DIV.) FIGURE 15. LARGE SIGNAL BIPOLAR PULSE RESPONSE 3.0 2.5 A V = +5 2.0 OUTPUT VOLTAGE (V) 1.5 1.0 0.5 A V = +5 0 -0.5 -1.0 TIME (5ns/DIV.) AV = +10 FIGURE 16. SMALL SIGNAL POSITIVE PULSE RESPONSE 200 150 A V = +5 100 OUTPUT VOLTAGE (mV) AV = +10 50 0 -50 A V = +5 -100 -150 -200 TIME (5ns/DIV.) FIGURE 17. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 1.5 AV = + 5 1.0 OUTPUT VOLTAGE (V) AV = +10 0.5 0 -0.5 -1.0 A V = +5 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 18. SMALL SIGNAL BIPOLAR PULSE RESPONSE FIGURE 19. LARGE SIGNAL BIPOLAR PULSE RESPONSE 9 HFA1205 Typical Performance Curves VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 630 0.1 SETTLING ERROR (%) A V = +2 VOUT = 2V CH2 200 63 20 GAIN (kΩ) 6.3 PHASE 2.0 0.63 0.2 -0.1 0.063 135 90 45 0 PHASE (DEGREES) PHASE (DEGREES) 180 GAIN 0.05 0.025 0 -0.025 -0.05 10 20 30 40 50 60 TIME (ns) 70 80 90 100 0.001 0.01 0.1 1 3 6 10 FREQUENCY (MHz) 100 500 FIGURE 20. SETTLING TIME RESPONSE FIGURE 21. OPEN LOOP TRANSIMPEDANCE GAIN (dB) 3 0 -3 -6 VOUT = 200mVP-P GAIN NORMALIZED GAIN (dB) AV = +1, CH2 3 0 -3 -6 VOUT = 200mVP-P GAIN AV = +2, CH1 A V = +5 PHASE AV = +10 AV = +2, CH2 AV = +1, CH1 PHASE AV = - 1 0 90 180 AV = + 1 AV = - 1 270 360 1000 NORMALIZED PHASE (DEGREES) 0 90 AV = +10 AV = + 5 AV = + 2 180 270 360 BOTH CHANNELS SHOWN 1 BOTH CHANNELS SHOWN 1 10 100 FREQUENCY (MHz) 1000 10 100 FREQUENCY (MHz) FIGURE 22. FREQUENCY RESPONSE FIGURE 23. FREQUENCY RESPONSE 10 HFA1205 Typical Performance Curves NORMALIZED GAIN (dB) AV = + 2 3 GAIN 0 -3 -6 PHASE VOUT = 1VP-P , CH1 VOUT = 2.5VP-P VOUT = 4VP-P 90 180 270 360 BOTH CHANNELS SHOWN 1 10 100 FREQUENCY (MHz) 1000 1 PHASE (DEGREES) 0 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P -6 PHASE VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) GAIN (dB) VOUT = 1VP-P , CH2 A V = +1 3 0 -3 GAIN VOUT = 1VP-P , CH2 VOUT = 4VP-P VOUT = 1VP-P , CH1 VOUT = 2.5VP-P 0 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 90 180 270 360 BOTH CHANNELS SHOWN 10 100 FREQUENCY (MHz) 1000 PHASE (DEGREES) FIGURE 24. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FIGURE 25. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES AV = -1 GAIN (dB) 3 GAIN 0 -3 -6 PHASE VOUT = 4VP-P VOUT = 1VP-P NORMALIZED GAIN (dB) BOTH CHANNELS SHOWN NORMALIZED PHASE (DEGREES) 3 0 -3 -6 -9 AV = -1, VOUT = 5VP-P AV = +2, VOUT = 5VP-P AV = +1, VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 0 90 180 270 360 BOTH CHANNELS SHOWN 1 10 100 FREQUENCY (MHz) 1000 1 10 100 FREQUENCY (MHz) 1000 FIGURE 26. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES -40 VOUT = 200mVP-P 0.4 NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 BOTH CHANNELS SHOWN 1 10 FREQUENCY (MHz) 100 0.3 AV = +2, CH1 AV = +2, CH2 AV = +1, CH2 AV = -1 CROSSTALK (dB) -45 -50 -55 -60 -65 -70 -75 -80 -85 FIGURE 27. FULL POWER BANDWIDTH RL = 100Ω RL = 1kΩ AV = +1, CH1 1 10 FREQUENCY (MHz) 100 FIGURE 28. GAIN FLATNESS FIGURE 29. CROSSTALK 11 HFA1205 Typical Performance Curves 10 20 30 ISOLATION (dB) 40 50 60 70 80 90 100 1 10 100 FREQUENCY (MHz) 1000 0.3 1 10 100 1000 A V = +1 A V = +2 VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) A V = +2 OUTPUT RESISTANCE (Ω) 1K 100 10 1 0.1 0.01 FREQUENCY (MHz) FIGURE 30. REVERSE ISOLATION (S12) 30 AV = + 2 25 NOISE VOLTAGE (nV/√Hz) 100 FIGURE 31. OUTPUT RESISTANCE 100 20 INI+ 10 10 15 ENI 10 5 0 50 100 150 1 0.1 1 10 FREQUENCY (kHz) 1 100 FREQUENCY (MHz) FIGURE 32. 3rd ORDER INTERCEPT vs FREQUENCY FIGURE 33. INPUT NOISE CHARACTERISTICS 16 25oC TOTAL SUPPLY CURRENT (mA) 14 -55oC 12 125oC 10 25oC 8 3.6 3.5 3.4 OUTPUT VOLTAGE (V) 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 AV = -1 |-VOUT| (RL = 100Ω) +VOUT (RL = 100Ω) |-VOUT| (RL = 50Ω) +VOUT (RL = 50Ω) 6 -25 0 25 50 75 TEMPERATURE (oC) 100 125 4 3 4 5 6 SUPPLY VOLTAGE (±V) 7 FIGURE 34. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 35. SUPPLY CURRENT vs SUPPLY VOLTAGE 12 NOISE CURRENT (pA/√Hz) 8 INI- TOI (dBm) HFA1205 Die Characteristics DIE DIMENSIONS: 69 mils x 92 mils 1750µm x 2330µm METALLIZATION: Type: Metal 1: AICu (2%)/TiW Thickness: Metal 1: 8kÅ ± 0.4kÅ Type: Metal 2: AICu (2%) Thickness: Metal 2: 16kÅ ± 0.8kÅ SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) PASSIVATION: Type: Nitride Thickness: 4kÅ ± 0.5kÅ TRANSISTOR COUNT: 180 Metallization Mask Layout HFA1205 -IN1 OUT1 NC V+ NC OUT2 +IN1 NC NC -IN2 V- NC NC +IN2 13 HFA1205 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 14 HFA1205 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 15