HFA1405_05

UCT PROD CT OLETE UTE PRODU OBS IT BS Sheet Data T L5455 LE SU POSSIB EL2480, E ® HFA1405 March 1, 2005 FN3604.9 Quad, 560MHz, Low Power, Video Operational Amplifier The HFA1405 is a quad, high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. These amplifiers deliver up to 560MHz bandwidth and 2500V/µs slew rate, on only 58mW of quiescent power. They are specifically designed to meet the performance, power, and cost requirements of high volume video applications. The excellent gain flatness and differential gain/phase performance make these amplifiers well suited for component or composite video applications. Video performance is maintained even when driving a back terminated cable (RL = 150Ω), and degrades only slightly when driving two back terminated cables (RL = 75Ω). RGB applications will benefit from the high slew rates, and high full power bandwidth. The HFA1405 is a pin compatible, low power, high performance upgrade for the popular Intersil HA5025, and for the CLC414 and CLC415. Features • Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ • Wide -3dB Bandwidth (AV = +2). . . . . . . . . . . . . . 560MHz • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2500V/µs • Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . . . . ±0.03dB • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • All Hostile Crosstalk (5MHz) . . . . . . . . . . . . . . . . . . -60dB • Pin Compatible Upgrade to HA5025, CLC414, and CLC415 Applications • Flash A/D Drivers • Professional Video Processing • Video Digitizing Boards/Systems • Multimedia Systems Part # Information PART NUMBER HFA1405IB HFA1405IP HA5025EVAL TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 14 Ld SOIC 14 Ld PDIP PKG. DWG. # M14.15 E14.3 • RGB Preamps • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications • High Speed Oscilloscopes and Analyzers High Speed Op Amp DIP Evaluation Board Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Pinout HFA1405 (PDIP, SOIC) TOP VIEW OUT 1 1 -IN 1 2 +IN 1 3 V+ 4 +IN 2 5 -IN 2 6 OUT 2 7 + + 14 OUT 4 13 -IN 4 12 +IN 4 11 V10 +IN 3 9 -IN 3 8 OUT 3 + + - 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2000-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1405 Absolute Maximum Ratings TA = 25oC Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Output Current (Note 2) . . . . . . . . . . . . . . . . .Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (NOTE 4) TEST LEVEL HFA1405IB (SOIC) TEMP( oC) MIN TYP MAX HFA1405IP (PDIP) MIN TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Input Offset Voltage TEST CONDITIONS A A 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 45 43 43 48 46 46 0.8 0.5 0.5 - 2 3 1 48 46 46 52 48 48 6 10 5 0.5 0.8 0.8 1.2 0.8 0.8 2 5 60 3 4 4 5 8 10 15 25 60 1 3 3 7.5 15 200 6 8 8 45 43 43 48 46 46 0.8 0.5 0.5 - 2 3 1 48 46 46 52 48 48 6 10 5 0.5 0.8 0.8 1.2 0.8 0.8 2 5 60 3 4 4 5 8 10 15 25 60 1 3 3 7.5 15 200 6 8 8 mV mV µV/oC dB dB dB dB dB dB µA µA nA/oC µA/V µA/V µA/V MΩ MΩ MΩ µA µA nA/oC µA/V µA/V µA/V Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Input Offset Voltage Power Supply Rejection Ratio Non-Inverting Input Bias Current ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V B A A A A A A A A Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity Non-Inverting Input Resistance ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Inverting Input Bias Current B A A A A A A A A Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V B A A A 2 HFA1405 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 4) TEST LEVEL A A A C B A A f = 100kHz B B B HFA1405IB (SOIC) TEMP( oC) 25 85 -40 25 25 25, 85 -40 25 25 25 MIN ±1.8 ±1.2 TYP 2 4 4 60 1.4 ±2.4 ±1.7 3.5 2.5 20 MAX 5 8 8 HFA1405IP (PDIP) MIN ±1.8 ±1.2 TYP 2 4 4 60 2.2 ±2.4 ±1.7 3.5 2.5 20 MAX 5 8 8 UNITS µA/V µA/V µA/V Ω pF V V nV/√Hz pA/√Hz pA/√Hz PARAMETER Inverting Input Bias Current Power Supply Sensitivity TEST CONDITIONS ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IB-IAS CMS Tests) Input Noise Voltage Density Non-Inverting Input Noise Current f = 100kHz Density Inverting Input Noise Current Density TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain AC CHARACTERISTICS (Note 3) -3dB Bandwidth (VOUT = 0.2VP-P, Notes 3, 5) Full Power Bandwidth (VOUT = 5VP-P, Notes 3, 5) Gain Flatness (VOUT = 0.2VP-P, Notes 3, 5) AV = -1 AV = +2 AV = +6 AV = -1 AV = +2 AV = +6 AV = -1, 25MHz AV = -1, 50MHz AV = -1, 100MHz AV = +2, 25MHz AV = +2, 50MHz AV = +2, 100MHz AV = +6, 15MHz AV = +6, 30MHz Minimum Stable Gain Crosstalk (AV = +1, All Channels Hostile, Note 5) 5MHz 10MHz AV = -1 f = 100kHz C 25 - 500 - - 500 - kΩ B B B B B B B B B B B B B B A B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 Full 25 25 - 420 560 140 260 165 140 ±0.03 ±0.04 ±0.09 ±0.03 ±0.03 ±0.07 ±0.08 ±0.19 1 -60 -56 - - 360 400 100 260 165 100 ±0.04 ±0.04 ±0.06 ±0.04 ±0.04 ±0.06 ±0.08 ±0.27 1 -55 -52 - MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB dB dB V/V dB dB OUTPUT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified Output Voltage Swing (Note 5) Output Current (Note 5) Output Short Circuit Current Closed Loop Output Impedance Second Harmonic Distortion (VOUT = 2VP-P, Note 5) Third Harmonic Distortion (VOUT = 2VP-P, Note 5) 10MHz 20MHz 10MHz 20MHz AV = -1, RL = 100Ω AV = -1, RL = 50Ω A A A A B B B B B B 25 Full 25, 85 -40 25 25 25 25 25 25 ±3 ±2.8 50 28 ±3.4 ±3 60 42 90 0.2 -51 -46 -63 -56 ±3 ±2.8 50 28 ±3.4 ±3 60 42 90 0.2 -51 -46 -63 -56 V V mA mA mA Ω dBc dBc dBc dBc 3 HFA1405 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 4) TEST LEVEL HFA1405IB (SOIC) TEMP( oC) MIN TYP MAX HFA1405IP (PDIP) MIN TYP MAX UNITS PARAMETER TEST CONDITIONS TRANSIENT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P, Note 3) Overshoot (VOUT = 0.5VP-P, VIN tRISE = 1ns, Notes 3, 6) AV = +2 AV = +6 AV = -1, +OS AV = -1, -OS AV = +2, +OS AV = +2, -OS AV = +6, +OS AV = +6, -OS Slew Rate (VOUT = 5VP-P, Notes 3, 5) AV = -1, +SR AV = -1, -SR AV = +2, +SR AV = +2, -SR AV = +6, +SR AV = +6, -SR Settling Time To 0.1% (VOUT = +2V to 0V Step, Note 5) To 0.05% To 0.025% Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz) Differential Phase (f = 3.58MHz) VIN = ±2V RL = 150Ω RL = 75Ω RL = 150Ω RL = 75Ω B B B B B B B B B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 0.8 2.9 7 8 5 10 2 2 2500 1900 1700 1700 1500 1100 23 30 37 8.5 0.9 4 3 13 7 11 2 2 2500 1900 1600 1400 1000 1000 23 30 40 8.5 ns ns % % % % % % V/µs V/µs V/µs V/µs V/µs V/µs ns ns ns ns AV = +2 (Note 3), Unless Otherwise Specified B B B B 25 25 25 25 ±4.5 0.02 0.03 0.03 0.06 ±5.5 6.1 6.3 ±4.5 0.03 0.06 0.03 0.06 ±5.5 6.1 6.3 % % Degrees Degrees POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 5) C A A NOTES: 3. The optimum feedback resistor depends on closed loop gain and package type. See the “Optimum Feedback Resistor” table in the Application Information section for details. 4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 5. See Typical Performance Curves for more information. 6. Undershoot dominates for output signal swings below GND (e.g., 2VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 2V condition. See the “Application Information” section for details. 25 25 Full 5.8 5.9 5.8 5.9 V mA/Op Amp mA/Op Amp Application Information Performance Differences Between Packages The amplifiers comprising the HFA1405 are high frequency current feedback amplifiers. As such, they are sensitive to feedback capacitance which destabilizes the op amp and causes overshoot and peaking. Unfortunately, the standard quad op amp pinout places the amplifier’s output next to its inverting input, thus making the package capacitance an unavoidable parasitic feedback capacitor. The larger parasitic capacitance of the PDIP requires an inherently more stable amplifier, which yields a PDIP device with lower performance than the SOIC device - see Electrical Specification tables for details. Because of these performance differences, designers should evaluate and breadboard with the same package style to be used in production. Note that the “Typical Performance Curves” section has separate pulse and frequency response graphs for each 4 HFA1405 package type. Graphs not labeled with a specific package type are applicable to all packages. resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figure 6 and Figure 9). This undershoot isn’t present for small bipolar signals, or large positive signals (see Figure 4 and Figure 5). Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1405 design is optimized for RF = 402Ω/510Ω (PDIP/SOIC) at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback causes the same problems due to the feedback impedance decrease at higher frequencies). However, at higher gains the amplifier is more stable so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For good channel-tochannel gain matching, it is recommended that all resistors (termination as well as gain setting) be ±1% tolerance or better. TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (ACL) -1 +1 +2 +5 +6 +10 RF (Ω) PDIP/SOIC 310/360 510 (+RS = 510)/ 464 (+RS = 649) 402/510 NA/200 500/500 (Note) NA/180 BANDWIDTH (MHz) PDIP/SOIC 360/420 300/375 400/560 NA/330 100/140 NA/140 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and eventual instability. To reduce this capacitance the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 560MHz. By decreasing RS as CL increases (as illustrated in the curve), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. NOTE: RF = 500Ω is not the optimum value. It was chosen to match the RF of the CLC414 and CLC415, for performance comparison purposes. Performance at AV = +6 may be increased by reducing RF below 500Ω. Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥ 50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. Pulse Undershoot The HFA1405 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, 5 HFA1405 50 SERIES OUTPUT RESISTANCE (Ω) TOP LAYOUT 40 30 20 AV = +2 10 0 0 50 100 150 200 250 300 350 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE BOTTOM LAYOUT Evaluation Board The performance of the HFA1405 PDIP or SOIC can be evaluated using the HA5025 Evaluation Board. The HFA1405IB (SOIC) requires a SOIC to DIP adaptor like the Aries Electronics Part Number 14-350000-10. The schematic for the PDIP/SOIC amplifier 1 and the HA5025EVAL board layout are shown in Figure 2 and Figure 3. Resistors RF, RG , and +RS may require a change to values applicable to the HFA1405. To order evaluation board (part number HA5025EVAL), please contact your local sales office. 50Ω OUT RG IN 50Ω RF +RS 3 4 5 +5V 10µF 0.1µF 6 7 9 8 GND GND 1 2 + 14 13 12 11 10 0.1µF 10µF -5V FIGURE 3. EVALUATION BOARD LAYOUT FOR PDIP/SOIC FIGURE 2. EVALUATION BOARD SCHEMATIC FOR PDIP/SOIC 6 HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified 160 AV = +2 120 SOIC OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) A V = +2 SOIC FIGURE 4. SMALL SIGNAL PULSE RESPONSE 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = + 2 SOIC OUTPUT VOLTAGE (mV) FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE 160 120 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) AV = - 1 SOIC FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = -1 SOIC OUTPUT VOLTAGE (V) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 FIGURE 7. SMALL SIGNAL PULSE RESPONSE AV = -1 SOIC TIME (5ns/DIV.) FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE 7 HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 1.6 A V = +6 SOIC OUTPUT VOLTAGE (V) 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) TIME (5ns/DIV.) AV = +6 SOIC 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 FIGURE 10. SMALL SIGNAL PULSE RESPONSE 2 1 0 -1 -2 -3 FIGURE 11. LARGE SIGNAL PULSE RESPONSE NORMALIZED GAIN (dB) VOUT = 200mVP-P 6 3 GAIN 0 -3 PHASE AV = -1 AV = +6 0 AV = +6 AV = -1 AV = +2 90 180 270 360 0.3 1 10 FREQUENCY (MHz) 100 800 SOIC AV = +2 NORMALIZED PHASE (DEGREES) NORMALIZED GAIN (dB) AV = +2 VOUT = 200mVP-P SOIC GAIN RF = 1 k Ω RF = 1.5kΩ RF = 500Ω RF = 683Ω RF = 750Ω PHASE RF = 1.5kΩ 0 90 180 RF = 500Ω 1 10 100 FREQUENCY (MHz) 270 360 800 FIGURE 12. FREQUENCY RESPONSE 0.3 0.2 NORMALIZED GAIN (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 1 10 FREQUENCY (MHz) 100 AV = +6 AV = -1 AV = +2 VOUT = 200mVP-P SOIC FIGURE 13. FREQUENCY RESPONSE vs FEEDBACK RESISTOR 0.2 0.1 NORMALIZED GAIN (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1 10 FREQUENCY (MHz) 100 RF = 1.5kΩ RF = 750Ω RF = 1kΩ RF = 683Ω AV = +2, SOIC VOUT = 200mVP-P RF = 500Ω FIGURE 14. GAIN FLATNESS FIGURE 15. GAIN FLATNESS vs FEEDBACK RESISTOR 8 PHASE (DEGREES) HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) -10 SOIC -20 -30 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 -100 -110 0.3 1 10 FREQUENCY (MHz) 100 200 RL = SETTLING ERROR (%) RL = 100Ω 0.2 0.15 0.1 0.05 0.025 0 -0.025 -0.05 -0.1 -0.15 -0.2 0 5 10 15 20 25 30 TIME (ns) 35 AV = +2 VOUT = 2V SOIC ∞ 40 45 50 FIGURE 16. ALL HOSTILE CROSSTALK 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 FIGURE 17. SETTLING RESPONSE AV = +2 PDIP AV = +2 PDIP TIME (5ns/DIV.) FIGURE 18. SMALL SIGNAL PULSE RESPONSE 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) 1.6 AV = -1 PDIP OUTPUT VOLTAGE (V) 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 FIGURE 19. LARGE SIGNAL PULSE RESPONSE AV = -1 PDIP TIME (5ns/DIV.) FIGURE 20. SMALL SIGNAL PULSE RESPONSE FIGURE 21. LARGE SIGNAL PULSE RESPONSE 9 HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 AV = +1 PDIP 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = +1 PDIP TIME (5ns/DIV.) FIGURE 22. SMALL SIGNAL PULSE RESPONSE 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) 1.6 AAV = +6 V = +2 PDIP PDIP RF = 150Ω OUTPUT VOLTAGE (V) 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 FIGURE 23. LARGE SIGNAL PULSE RESPONSE A V = +6 PDIP RF = 150Ω TIME (5ns/DIV.) FIGURE 24. SMALL SIGNAL PULSE RESPONSE 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 AV = + 6 PDIP RF = 500Ω 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) FIGURE 25. LARGE SIGNAL PULSE RESPONSE A V = +6 PDIP RF = 500Ω -120 -160 TIME (5ns/DIV.) FIGURE 26. SMALL SIGNAL PULSE RESPONSE FIGURE 27. LARGE SIGNAL PULSE RESPONSE 10 HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) VOUT = 200mVP-P PDIP 3 GAIN 0 -3 PHASE -6 AV = +2 AV = -1 AV = +1 AV = -1 AV = +1 (RF = +RS = 510Ω) 0 90 180 270 360 0.3 1 10 FREQUENCY (MHz) 100 800 NORMALIZED PHASE (DEGREES) AV = +2 AV = +6 VOUT = 200mVP-P 3 0 GAIN -3 -6 PHASE 90 RF = 500Ω RF = 150Ω 180 270 360 0.3 1 10 FREQUENCY (MHz) 100 800 RF = 150Ω RF = 500Ω PHASE (DEGREES) 0 PDIP FIGURE 28. FREQUENCY RESPONSE 3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 AV = +6 (RF = 500Ω) AV = +6 (RF = 150Ω) 0.3 1 10 FREQUENCY (MHz) 100 800 1 AV = +2 VOUT = 5VP-P PDIP AV = -1 2 1 0 -1 -2 -3 FIGURE 29. FREQUENCY RESPONSE AV = +2 VOUT = 200mVP-P PDIP RF = 365Ω RF = 390Ω RF = 422Ω RF = 510Ω 10 FREQUENCY (MHz) 100 800 FIGURE 30. FULL POWER BANDWIDTH FIGURE 31. FREQUENCY RESPONSE vs FEEDBACK RESISTOR NORMALIZED GAIN (dB) 0.2 0.1 0 VOUT = 200mVP-P PDIP AV = +1 (RF = +RS = 510Ω) PDIP AV = +2 -10 -20 -30 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 RL = ∞ RL = 100Ω -0.1 -0.2 -0.3 AV = +6 (RF = 150Ω) AV = -1 1 10 FREQUENCY (MHz) 100 -100 0.3 1 10 FREQUENCY (MHz) 100 FIGURE 32. GAIN FLATNESS FIGURE 33. ALL HOSTILE CROSSTALK 11 HFA1405 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 3.6 0.2 0.15 SETTLING ERROR (%) 0.1 0.05 0.025 0 -0.025 -0.05 -0.1 -0.15 -0.2 0 5 10 15 20 25 30 TIME (ns) 35 40 45 50 AV = +2 VOUT = 2V PDIP OUTPUT VOLTAGE (V) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 +VOUT (RL= 50Ω) AV = -1 +VOUT (RL= 100Ω) |-VOUT| (RL= 50Ω) |-VOUT| (RL= 100Ω) TEMPERATURE (oC) FIGURE 34. SETTLING RESPONSE 6.6 SUPPLY CURRENT (mA/AMPLIFIER) 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 4.5 5 5.5 6 FIGURE 35. OUTPUT VOLTAGE vs TEMPERATURE 6.5 7 SUPPLY VOLTAGE (±V) FIGURE 36. SUPPLY CURRENT vs SUPPLY VOLTAGE 12 HFA1405 Die Characteristics DIE DIMENSIONS: 79 mils x 118 mils 2000µm x 3000µm METALLIZATION: Type: Metal 1: AICu (2%)/TiW Thickness: Metal 1: 8kÅ ± 0.4kÅ Type: Metal 2: AICu (2%) Thickness: Metal 2: 16kÅ ± 0.8kÅ SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) PASSIVATION: Type: Nitride Thickness: 4kÅ ± 0.5kÅ TRANSISTOR COUNT: 320 Metallization Mask Layout HFA1405 -IN1 OUT1 OUT4 -IN4 +IN1 +IN4 V+ V- +IN2 +IN3 -IN2 OUT2 V- OUT3 -IN3 13 HFA1405 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 A1 B C D E α µ A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 14 HFA1405 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15