HI5662EVAL2

HI5662 Data Sheet February 1999 File Number 4317.2 Dual 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference The HI5662 is a monolithic, dual 8-Bit, 60MSPS analog-todigital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The HI5662 reaches a new level of multi-channel integration. The fully pipeline architecture and an innovative input stage enable the HI5662 to accept a variety of input configurations, single-ended or fully differential. Only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. This allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI5662 has excellent dynamic performance while consuming only 650mW power at 60MSPS. The A/D only requires a single +5V power supply and encode clock. Data output latches are provided which present valid data to the output bus with a latency of 6 clock cycles. For those customers needing dual channel 10-bit resolution, please refer to the HI5762. For single channel 10-bit applications, please refer to the HI5767. Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS • 7.8 Bits at fIN = 10MHz • Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz • Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB • On-Chip Sample and Hold Amplifiers • Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V • Fully Differential or Single-Ended Analog Inputs • Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V • TTL/CMOS Compatible Digital Inputs • CMOS Compatible Digital Outputs . . . . . . . . . . . . 3.0/5.0V • Offset Binary Digital Data Output Format • Dual 8-Bit A/D Converters on a Monolithic Chip Applications • Wireless Local Loop • PSK and QAM I and Q Demodulators • Medical Imaging • High Speed Data Acquisition Ordering Information PART NUMBER HI5662/6IN HI5662EVAL2 TEMP. RANGE (oC) -40 to 85 25 PACKAGE 44 Ld MQFP Evaluation Platform PKG. NO. Q44.10x10 Pinout HI5662 (MQFP) TOP VIEW VROUT AVCC1 QVDC AGND IVDC VRIN QIN+ QINIIN+ IINNC AGND AVCC2 ID7 ID6 ID5 ID4 ID3 DVCC3 DGND ID2 ID1 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24 AGND AVCC2 QD7 QD6 QD5 QD4 QD3 DVCC3 DGND QD2 QD1 10 11 23 12 13 14 15 16 17 18 19 20 21 22 DVCC1 CLK DVCC2 DGND DGND 10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 QD0 ID0 NC NC NC NC HI5662 Functional Block Diagram I/QINI/QIN+ S/H BIAS I/QVDC STAGE 1 2-BIT FLASH 2-BIT DAC + ∑ DVCC3 X2 I/QD7 (MSB) I/QD6 STAGE M-1 DIGITAL DELAY AND DIGITAL ERROR CORRECTION I/QD5 I/QD4 I/QD3 2-BIT FLASH 2-BIT DAC I/QD2 I/QD1 + ∑ I/QD0 (LSB) - X2 STAGE M 2-BIT FLASH I or Q CHANNEL VREFOUT VREFIN REFERENCE CLOCK CLK AVCC1,2 AGND DVCC1,2 DGND 11 HI5662 Typical Application Schematic HI5662 IIN + (42) IIN + (44) IVDC IIN (43) IIN (LSB) ID0 (12) ID1 (11) ID2 (10) ID3 (7) ID4 (6) ID5 (5) ID6 (4) (MSB) ID7 (3) ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 QIN + (36) QIN + (34) QVDC (LSB) QD0 (22) QD1 (23) QD2 (24) QD3 (27) QD4 (28) QD5 (29) QD6 (30) (MSB) QD7 (31) QD0 QD1 QD2 QD3 QD4 QD5 QD6 QD7 QIN - (35) QIN - 0.1µF (40) VRIN (38) VROUT CLK (17) CLOCK DVCC3 (8,26) (13,14,20,21,39) NC 0.1µF + 10µF +5V or +3V (37) AVCC1 +5V + 10µF (2,32) AVCC2 0.1µF DVCC2 (18) DVCC1 (16) 0.1µF + 10µF +5V (1,33,41) AGND DGND (9,15,19,25) BNC AGND DGND 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE 12 HI5662 Pin Descriptions PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NAME AGND AVCC2 ID7 ID6 ID5 ID4 ID3 DVCC3 DGND ID2 ID1 ID0 NC NC DGND DVCC1 CLK DVCC2 DGND NC NC QD0 QD1 DESCRIPTION Analog Ground Analog Supply (+5.0V) I-Channel, Data Bit 7 Output (MSB) I-Channel, Data Bit 6 Output I-Channel, Data Bit 5 Output I-Channel Data Bit 4 Output I-Channel, Data Bit 3 Output Digital Output Supply (+3.0V or +5.0V) Digital Ground I-Channel, Data Bit 2 Output I-Channel, Data Bit 1 Output I-Channel, Data Bit 0 Output (LSB) No Connect No Connect Digital Ground Digital Supply (+5.0V) Sample Clock Input Digital Supply (+5.0V) Digital Ground No Connect No Connect Q-Channel, Data Bit 0 Output (LSB) Q-Channel, Data Bit 1 Output 32 33 34 35 36 37 38 39 40 41 42 43 44 AVCC2 AGND QVDC QINQIN+ AVCC1 VROUT NC VRIN AGND IIN+ IINIVDC 27 28 29 30 31 QD3 QD4 QD5 QD6 QD7 PIN NO. 24 25 26 NAME QD2 DGND DVCC3 DESCRIPTION Q-Channel, Data Bit 2 Output Digital Ground Digital Output Supply (+3.0V or +5.0V) Q-Channel, Data Bit 3 Output Q-Channel, Data Bit 4 Output Q-Channel, Data Bit 5 Output Q-Channel, Data Bit 6 Output Q-Channel, Data Bit 7 Output (MSB) Analog Supply (+5.0V) Analog Ground Q-Channel DC Bias Voltage Output Q-Channel Negative Analog Input Q-Channel Positive Analog Input Analog Supply (+5.0V) +2.5V Reference Voltage Output No Connect +2.5V Reference Voltage Input Analog Ground I-Channel Positive Analog Input I-Channel Negative Analog Input I-Channel DC Bias Voltage Output 13 HI5662 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) HI5662/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Operating Conditions Temperature Range HI5662/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS 8 fIN = 10MHz fIN = 10MHz fIN = DC fIN = DC -10 - 0.5 ±0.2 1 ±1.0 +10 - Bits LSB LSB LSB LSB No Missing Codes No Missing Codes fIN = 10MHz fIN = 10MHz, Single Ended Analog Input fIN = 10MHz 60 7.5 7.0 - 1 7.8 7.7 48.7 - MSPS MSPS Bits Bits dB Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD I/Q Channel Crosstalk I/Q Channel Offset Match I/Q Channel Full Scale Error Match Transient Response Over-Voltage Recovery fIN = 10MHz - 48 - dB fIN = 10MHz fIN = 10MHz fIN = 10MHz fIN = 10MHz f1 = 1MHz, f2 = 1.02MHz - -66 -71 -71 71 64 -75 2.5 2.5 1 1 -60 - dBc dBc dBc dBc dBc dBc LSB LSB Cycle Cycle (Note 2) 0.2V Overdrive (Note 2) - 14 HI5662 Electrical Specifications PARAMETER ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN+ or RINAnalog Input Capacitance, CIN+ or CINAnalog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IBDIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 INTERNAL VOLTAGE REFERENCE Reference Output Voltage, VROUT (Loaded) Reference Output Current, IROUT Reference Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VRIN Total Reference Resistance, RRIN Reference Current, IRIN DC BIAS VOLTAGE DC Bias Voltage Output, VDC Maximum Output Current SAMPLING CLOCK INPUT Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Hold, tH 5 5 10.7 ns psRMS ns IOH = 100µA; DVCC3 = 5V IOL = 100µA; DVCC3 = 5V IOH = 100µA; DVCC3 = 3V IOL = 100µA; DVCC3 = 3V 4.0 2.4 7 0.8 0.5 V V V V pF CLK CLK CLK, VIH = 5V CLK, VIL = 0V CLK 2.0 -10.0 -10.0 7 0.8 +10.0 +10.0 V V µA µA pF 3.0 0.4 V mA with VRIN = 2.5V with VRIN = 2.5V 2.5 1.25 2 V kΩ mA 2.35 2.5 2 -400 2.65 4 V mA ppm/oC VIN+, VIN- = VREF,DC VIN+, VIN- = 2.5V,DC VIN+, VIN- = VREF-, VREF+, DC (Notes 2, 3) (Notes 2, 3) (Note 2) Differential Mode (Note 2) -10 -0.5 0.25 ±0.5 1.0 1 10 250 10 +0.5 4.75 V V MΩ pF µA µA MHz V AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS 15 HI5662 Electrical Specifications PARAMETER Data Output Delay, tOD Data Latency, tLAT Power-Up Initialization Sample Clock Pulse Width (Low) Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 and DVCC2 Digital Output Supply Voltage, DVCC3 (Note 2) (Note 2) At 3.0V (Note 2) At 5.0V (Note 2) Supply Current, ICC Power Dissipation Offset Error Sensitivity, ∆VOS Gain Error Sensitivity, ∆FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. AVCC or DVCC = 5V ±5% AVCC or DVCC = 5V ±5% fS = 60MSPS 4.75 4.75 2.7 4.75 5.0 5.0 3.0 5.0 130 650 ±0.125 ±0.15 5.25 5.25 3.3 5.25 670 V V V V mA mW LSB LSB For a Valid Sample (Note 2) Data Invalid Time (Note 2) (Note 2) (Note 2) AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued) TEST CONDITIONS MIN 6 7.5 7.5 TYP 11.7 6 8.3 8.3 ±5 MAX 6 20 UNITS ns Cycles Cycles ns ns % 16 HI5662 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 H N + 1 SN + 2 SN + 5 HN + 5 SN + 6 H N + 6 SN + 7 H N + 7 SN + 8 HN + 8 INPUT S/H 1ST STAGE B1 , N - 1 B1 , N B1 , N + 1 B1 , N + 4 B1 , N + 5 B1 , N + 6 B1 , N + 7 2ND STAGE B2 , N - 2 B2 , N - 1 B2 , N B2 , N + 4 B2 , N + 5 B2 , N + 6 M-th STAGE B9 , N - 5 B9 , N - 4 B9 , N B9 , N + 1 B9 , N + 2 B9 , N + 3 DATA OUTPUT DN - 6 DN - 5 tLAT DN - 1 DN DN + 1 DN + 2 NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5662 INTERNAL CIRCUIT TIMING ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.4V DATA N-1 DATA N 0.5V FIGURE 2. HI5662 INPUT-TO-OUTPUT TIMING 17 HI5662 Typical Performance Curves 8 50 50 ENOB (BITS) SINAD (dB) 7 44 44 SNR (dB) 38 6 38 fS = 60MSPS TA = 25oC 5 1 10 INPUT FREQUENCY (MHz) 32 100 32 1 fS = 60MSPS TA = 25oC 10 INPUT FREQUENCY (MHz) 100 FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND SINAD vs INPUT FREQUENCY 70 FIGURE 4. SNR vs INPUT FREQUENCY 90 85 80 75 dBc 70 65 60 55 50 1 -3HD -THD dB -2HD 60 50 -THD (dBc) 40 30 SNR (dB) OR SINAD (dB) 20 fS = 60MSPS TA = 25oC 10 INPUT FREQUENCY (MHz) 100 10 -40 -30 -20 INPUT LEVEL (dBFS) -10 0 FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 8 1MHz < fIN < 15MHz TA = 25oC ICC AICC ENOB (BITS) 7 6 fS = 60MSPS 1MHz < fIN < 15MHz TA = 25oC 5 40 42 44 46 48 50 52 54 56 58 60 SUPPLY CURRENT (mA) DICC1 DICC2 60 70 DICC3 10 20 30 40 fS (MSPS) 50 DUTY CYCLE (%, tHI /tCLK) FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE CLOCK DUTY CYCLE FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK FREQUENCY 18 HI5662 Typical Performance Curves (Continued) 2.50 INTERNAL REFERENCE VOLTAGE, VROUT (V) 2.49 DC BIAS VOLTAGE, I/Q VDC (V) 2.48 2.47 2.46 2.45 2.44 2.43 2.42 2.41 2.40 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 3.05 3.10 3.00 2.95 IVDC QVDC 2.90 2.85 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 FIGURE 9. INTERNAL REFERENCE VOLTAGE (VROUT) vs TEMPERATURE FIGURE 10. DC BIAS VOLTAGE (I/QVDC) vs TEMPERATURE 13.0 140 ICC 120 12.5 SUPPLY CURRENT (mA) 100 80 AICC 60 40 20 DICC1 DICC2 fS = 60MSPS 1MHz < fIN < 15MHz tOD (ns) tOD 12.0 11.5 DICC3 -20 0 20 40 TEMPERATURE (oC) 60 80 11.0 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 0 -40 FIGURE 11. DATA OUTPUT DELAY (tOD) vs TEMPERATURE FIGURE 12. SUPPLY CURRENT vs TEMPERATURE 0 -10 -20 -30 -40 dB -50 -60 -70 -80 -90 -100 0 100 200 300 400 500 600 700 FREQUENCY (BIN) 800 900 1023 fS = 60MSPS fIN = 10MHz TA = 25oC FIGURE 13. 2048 POINT FFT PLOT 19 HI5662 TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE CODE CENTER DESCRIPTION +Full Scale (+FS) -7/16LSB +FS - 17/16LSB +9/16LSB -7/16LSB -FS + 19/16LSB -Full Scale (-FS) + 9/16LSB NOTE: 8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V. DIFFERENTIAL INPUT VOLTAGE (I/QIN+ - I/QIN-) 0.498291V 0.494385V 2.19727mV -1.70898mV -0.493896V -0.497803V MSB I/QD7 1 1 1 0 0 0 I/QD6 1 1 0 1 0 0 I/QD5 1 1 0 1 0 0 I/QD4 1 1 0 1 0 0 I/QD3 1 1 0 1 0 0 I/QD2 1 1 0 1 0 0 I/QD1 1 1 0 1 0 0 LSB I/QD0 1 0 0 1 1 0 Detailed Description Theory of Operation The HI5662 is a dual 8-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 14 depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are controlled by an internal sampling clock which is a nonoverlapping two phase signal, φ1 and φ2 , derived from the master sampling clock. During the sampling phase, φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, φ2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sampleand-hold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the I/QIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. Φ1 I/QIN+ As illustrated in the functional block diagram and the timing diagram in Figure 1, identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the last stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the identical two-bit subconverter stages with the corresponding output of the last stage flash converter before applying the results to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final eight bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken (see the timing diagram in Figure 1). This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is provided in offset binary format (see Table 1, A/D Code Table). CH Φ1 VOUT+ VOUT- Φ1 Φ2 CS -+ +CS I/QIN- Φ1 Internal Reference Voltage Output, VREFOUT The HI5662 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. Φ1 CH Φ1 FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD 20 HI5662 An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5V reference voltage used by the converter. A band-gap reference circuit is used to generate a precision +1.25V internal reference voltage. This voltage is then amplified by a wide-band uncompensated operational amplifier connected in a gain-of-two configuration. An external, user-supplied, 0.1µF capacitor connected from the VROUT output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier. an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent DC bias source and stays well within the analog input common mode voltage range over temperature. For the AC coupled differential input (Figure 15) and with VRIN connected to VROUT, full scale is achieved when the VIN and -VIN input signals are 0.5VP- P, with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the I/QIN+ input is at VDC + 0.25V and the I/QIN- input is at VDC - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely, the converter will be at negative full scale when the I/QIN+ input is equal to VDC - 0.25V and I/QIN- is at VDC + 0.25V (I/QIN+ - I/QIN- = -0.5V). The analog input can be DC coupled (Figure 16) as long as the inputs are within the analog input common mode voltage range (0.25V ≤ VDC ≤ 4.75V). VIN VDC R C I/QIN+ HI5662 I/QVDC Reference Voltage Input, VREFIN The HI5662 is designed to accept a +2.5V reference voltage source at the VRIN input pin. Typical operation of the converter requires VRIN to be set at +2.5V. The HI5662 is tested with VRIN connected to VROUT yielding a fully differential analog input voltage range of ±0.5V. The user does have the option of supplying an external +2.5V reference voltage. As a result of the high input impedance presented at the VRIN input pin, 1.25kΩ typically, the external reference voltage being used is only required to source 2mA of reference input current. In the situation where an external reference voltage will be used an external 0.1µF capacitor must be connected from the VROUT output pin to analog ground in order to maintain the stability of the internal operational amplifier. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN . -VIN VDC R I/QIN- FIGURE 16. DC COUPLED DIFFERENTIAL INPUT Analog Input, Differential Connection The analog input of the HI5662 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 15 and Figure 16) will deliver the best performance from the converter. The resistors, R, in Figure 16 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. Analog Input, Single-Ended Connection The configuration shown in Figure 17 may be used with a single ended AC coupled input. VIN R I/QIN+ HI5662 I/QVDC R VIN R VDC I/QIN+ HI5662 I/QIN- -VIN I/QIN- FIGURE 15. AC COUPLED DIFFERENTIAL INPUT Since the HI5662 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 4.75V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. A DC voltage source, I/QVDC , equal to 3.0V (typical), is made available to the user to help simplify circuit design when using 21 FIGURE 17. AC COUPLED SINGLE ENDED INPUT Again, with VRIN connected to VROUT, if VIN is a 1VP-P sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ - I/QIN- = +0.5V) and will be at negative full scale when I/QIN+ is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +5V HI5662 or below AGND. In this case, VDC could range between 0.5V and 4.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the DC bias source, I/QVDC, of the HI5662. The single ended analog input can be DC coupled (Figure 18) as long as the input is within the analog input common mode voltage range. VIN VDC R C HI5662 I/QIN+ regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. Refer to the application note “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. Static Performance Definitions Offset Error (VOS) The midscale code transition should occur at a level 1 / 4LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. VDC I/QIN- Full-Scale Error (FSE) FIGURE 18. DC COUPLED SINGLE ENDED INPUT The resistor, R, in Figure 18 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5662. The last code transition should occur for an analog input that is 3 / 4LSB below Positive Full Scale (+FS) with the offset error removed. Full scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Sensitivity Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted. Sampling Clock Requirements The HI5662 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families. In order to ensure rated performance of the HI5662, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL/CMOS levels. Performance of the HI5662 will only be guaranteed at conversion rates above 1MSPS (Typ). This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS must to be performed before valid data is available. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5662. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is typically -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. The Effective Number of Bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5 dB (Typical). VCORR adjusts the SINAD, and hence the ENOB, for the amount the analog input signal is backed off from full scale. Supply and Ground Considerations The HI5662 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The digital data outputs also have a separate supply pin, DVCC3 , which can be powered from a 3.0V or 5.0V supply. This allows the outputs to interface with 3.0V logic if so desired. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5662 should be driven by clean, linear 22 HI5662 Signal To Noise and Distortion Ratio (SINAD) SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS/2, excluding DC. I/Q Channel Crosstalk I/Q Channel Crosstalk is a measure of the amount of channel separation or isolation between the two A/D converter cores contained within the dual converter package. The measurement consists of stimulating one channel of the converter with a fullscale input signal and then measuring the amount that signal is below, in dBc, a fullscale signal on the opposite channel. Signal To Noise Ratio (SNR) SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS /2 excluding the fundamental, the first five harmonics and DC. Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. Aperture Delay (tAP) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS /2. Aperture Jitter (tAJ) Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Data Latency (tLAT) After the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken. This is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. This delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital data lags the analog input sample by 6 sample clock cycles. Transient Response Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Over-Voltage Recovery Over-Voltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Power-Up Initialization This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter. Full Power Input Bandwidth (FPBW) Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 23