HI5766EVAL1

HI5766 Data Sheet February 1999 File Number 4130.5 10-Bit, 60 MSPS A/D Converter The HI5766 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 60 MSPS speed is made possible by a fully differential pipelined architecture with an internal sample and hold. The HI5766 has excellent dynamic performance while consuming only 260mW power at 60 MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. It is pin-for-pin functionally compatible with the HI5702, HI5703 and the HI5746. For internal voltage reference, please refer to the HI5767 data sheet. Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MSPS • 8.3 Bits at fIN = 10MHz • Low Power at 60 MSPS . . . . . . . . . . . . . . . . . . . . 260mW • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz • On Chip Sample and Hold • Fully Differential or Single-Ended Analog Input • Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V • TTL/CMOS Compatible Digital Inputs • CMOS Compatible Digital Outputs . . . . . . . . . . . . 3.0/5.0V • Offset Binary or Two’s Complement Output Format Applications • Professional Video Digitizing • Medical Imaging • Digital Communication Systems • High Speed Data Acquisition Ordering Information PART NUMBER HI5766KCB HI5766KCA HI5766EVAL1 TEMP. RANGE (oC) 0 to 70 0 to 70 25 PACKAGE 28 Ld SOIC (W) 28 Ld SSOP Evaluation Board PKG. NO. M28.3 M28.15 Pinout HI5766 (SOIC, SSOP) TOP VIEW DVCC1 1 DGND 2 DVCC1 3 DGND 4 AVCC 5 AGND 6 VREF + 7 VREF - 8 VIN+ 9 VIN- 10 VDC 11 AGND 12 AVCC 13 OE 14 28 D0 27 D1 26 D2 25 D3 24 D4 23 DVCC2 22 CLK 21 DGND 20 D5 19 D6 18 D7 17 D8 16 D9 15 DFS 31 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI5766 Functional Block Diagram VDC VINVIN+ S/H BIAS CLOCK CLK STAGE 1 DFS 2-BIT FLASH 2-BIT DAC OE + ∑ DVCC2 X2 D9 (MSB) D8 D7 D6 STAGE 8 DIGITAL DELAY AND DIGITAL ERROR CORRECTION D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + ∑ D0 (LSB) - X2 DGND2 STAGE 9 2-BIT FLASH AVCC AGND DVCC1 DGND1 VREF + VREF - (OPTIONAL) 32 HI5766 Typical Application Schematic HI5766 2.5V 2.0V (OPTIONAL) VREF+ (7) VREF - (8) (LSB) (28) D0 (27) D1 AGND (12) AGND (6) DGND1 (2) DGND1 (4) DGND2 (21) (26) D2 (25) D3 (24) D4 (20) D5 (19) D6 (18) D7 (17) D8 (MSB) (16) D9 VIN + VIN + (9) VDC (11) VIN VIN - (10) (1) DVCC1 (3) DVCC1 (23) DVCC2 0.1µF CLOCK CLK (22) DFS (15) OE (14) (13) AVCC (5) AVCC 0.1µF + 10µF +5V D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE + 10µF +5V DGND AGND BNC Pin Descriptions PIN NO. 1 2 3 4 5 6 7 NAME DVCC1 DGND1 DVCC1 DGND1 AVCC AGND VREF+ VREF VIN+ VINVDC AGND AVCC OE DESCRIPTION Digital Supply (+5.0V). Digital Ground. Digital Supply (+5.0V). Digital Ground. Analog Supply (+5.0V). Analog Ground. +2.5V Positive Reference Voltage Input. +2.0V Negative Reference Voltage Input (Optional). Positive Analog Input. 24 Negative Analog Input. 25 DC Bias Voltage Output. 26 Analog Ground. 27 13 14 Analog Supply (+5.0V). 28 Digital Output Enable Control Input. D0 Data Bit 0 Output (LSB). D1 Data Bit 1 Output. D2 Data Bit 2 Output. D3 Data Bit 3 Output. D4 Data Bit 4 Output. PIN NO. 15 16 17 18 19 20 21 22 8 23 NAME DFS D9 D8 D7 D6 D5 DGND2 CLK DVCC2 DESCRIPTION Data Format Select Input. Data Bit 9 Output (MSB). Data Bit 8 Output. Data Bit 7 Output. Data Bit 6 Output. Data Bit 5 Output. Digital Ground. Sample Clock Input. Digital Output Supply (+3.0V or +5.0V). 9 10 11 12 33 HI5766 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . 6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Operating Conditions Temperature Range HI5766KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD Differential Gain Error Differential Phase Error Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IB(Note 3) (Note 3) fIN = DC fIN = DC fIN = DC fIN = DC 10 -40 - ±1.0 ±0.5 12 4 ±2.0 ±1.0 +40 - Bits LSB LSB LSB LSB No Missing Codes No Missing Codes fIN = 10MHz fIN = 10MHz 60 - 0.5 8.3 51.7 1 - MSPS MSPS Bits dB fIN = 10MHz - 53.7 - dB fIN = 10MHz fIN = 10MHz fIN = 10MHz fIN = 10MHz f1 = 1MHz, f2 = 1.02MHz fS = 17.72 MSPS, 6 Step, Mod Ramp fS = 17.72 MSPS, 6 Step, Mod Ramp (Note 2) 0.2V Overdrive (Note 2) - -56.2 -61.6 -58.1 58.1 62 0.8 0.1 1 1 ±0.5 1.0 1 10 - - dBc dBc dBc dBc dBc % Degree Cycle Cycle -10 +10 V V MΩ pF µA 34 HI5766 Electrical Specifications AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS (Note 3) MIN Differential Mode (Note 2) 0.25 TYP ±0.5 250 MAX 4.75 UNITS µA MHz V PARAMETER Differential Analog Input Bias Current IBDIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 REFERENCE INPUT Total Reference Resistance, RL Reference Current Positive Reference Voltage Input, VREF+ Negative Reference Voltage Input, VREF Reference Common Mode Voltage (VREF+ + VREF -) / 2 DC BIAS VOLTAGE DC Bias Voltage Output, VDC Maximum Output Current DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Hold, tH Data Output Delay, tOD Data Output Enable Time, tEN Data Output Enable Time, tDIS Data Latency, tLAT Power-Up Initialization POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 Digital Output Supply Voltage, DVCC2 Supply Current, ICC Power Dissipation At 3.0V At 5.0V (Note 2) (Note 2) (Note 2) - 2.5K 1.0 2.5 2.0 2.25 - Ω mA V V V - 3.2 - 0.4 V mA CLK, DFS, OE CLK, DFS, OE CLK, DFS, OE, VIH = 5V CLK, DFS, OE, VIL = 0V 2.0 -10.0 -10.0 - 7 0.8 +10.0 +10.0 - V V µA µA pF IOH = 100µA; DVCC2 = 5V IOL = 100µA; DVCC2 = 5V VO = 0/5V; DVCC2 = 5V IOH = 100µA; DVCC2 = 3V IOL = 100µA; DVCC2 = 3V VO = 0/5V; DVCC2 = 3V 4.0 2.4 - ±1 ±1 10 0.5 ±10 0.5 ±10 - V V µA V V µA pF For a Valid Sample (Note 2) Data Invalid Time (Note 2) - 5 5 7 8 5 5 - 7 20 ns psRMS ns ns ns ns Cycles Cycles 4.75 4.75 2.7 4.75 - 5.0 5.0 3.0 5.0 52 260 5.25 5.25 3.3 5.25 - V V V V mA mW VIN+ - VIN- = 1.25V and DFS = “0” VI+ - VIN- = 1.25V and DFS = “0” 35 HI5766 Electrical Specifications AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS AVCC or DVCC = 5V ±5% AVCC or DVCC = 5V ±5% MIN TYP ±0.4 ±0.8 MAX UNITS LSB LSB PARAMETER Offset Error Sensitivity, ∆VOS Gain Error Sensitivity, ∆FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 H N + 1 SN + 2 SN + 5 HN+5 SN + 6 H N + 6 SN + 7 HN + 7 SN + 8 HN + 8 INPUT S/H 1ST STAGE B1 , N - 1 B1 , N B1 , N + 1 B1 , N + 4 B1 , N + 5 B1 , N + 6 B1 , N + 7 2ND STAGE B2 , N - 2 B2 , N - 1 B2 , N B2 , N + 4 B2 , N + 5 B2 , N + 6 9TH STAGE B9 , N - 5 B9 , N - 4 B9 , N B9 , N + 1 B9 , N + 2 B9 , N + 3 DATA OUTPUT DN - 7 DN - 6 tLAT DN - 2 DN - 1 DN DN + 1 NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5766 INTERNAL CIRCUIT TIMING 36 HI5766 Timing Waveforms ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.4V DATA N - 1 DATA N 0.5V FIGURE 2. INPUT-TO-OUTPUT TIMING Typical Performance Curves 9 fS = 60 MSPS TA = 25oC ENOB (BITS) 8 SND dB 45 55 SNR fS = 60 MSPS TA = 25oC 7 6 1 10 INPUT FREQUENCY (MHz) 100 35 1 10 INPUT FREQUENCY (MHz) 100 FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY FIGURE 4. SINAD AND SNR vs INPUT FREQUENCY 85 fS = 60 MSPS TA = 25oC 75 -2HD SFDR dBc 65 -3HD 9 8 7 6 5 4 45 1 10 INPUT FREQUENCY (MHz) 100 3 0 5 10 15 20 25 30 35 INPUT LEVEL (-dBFS) fS = 60 MSPS fIN = 10MHz TA = 25oC 55 -THD NOTE: SFDR depicted here does not include any harmonic distortion. FIGURE 5. -2HD, -3HD, -THD AND SFDR vs INPUT FREQUENCY FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs ANALOG INPUT LEVEL 37 ENOB (BITS) HI5766 Typical Performance Curves 10 fS = 60 MSPS fIN = 10MHz TA = 25oC 8.8 8.6 8.4 8.2 8.0 7.8 6 40 45 50 55 DUTY CYCLE (%, tH /tCLK) 60 7.6 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 VREF+ (V) fS = 60 MSPS fIN = 10MHz TA = 25oC VREF + - VREF - = 0.5V (Continued) 9 ENOB (BITS) 8 7 FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE CLOCK DUTY CYCLE 53 ENOB (BITS) FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF + 85 fS = 60 MSPS 80 SNR 75 dBc SND 70 65 -3HD fIN = 10MHz -2HD TA = 25oC VREF + - VREF - = 0.5V 52 51 dB 50 49 48 fS = 60 MSPS fIN = 10MHz TA = 25oC VREF + - VREF - = 0.5V 47 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 VREF+ (V) 60 55 -THD SFDR 50 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 VREF+ (V) NOTE: SFDR depicted here does not include any harmonic distortion. FIGURE 9. SINAD AND SNR vs VREF + FIGURE 10. -2HD, -3HD, -THD AND SFDR vs VREF + 8.4 fS = 60 MSPS fIN = 10MHz TA = 25oC VREF - NOT DRIVEN ENOB (BITS) 8.2 51 50 SNR 49 dB SINAD 48 8.0 47 fS = 60 MSPS fIN = 10MHz TA = 25oC VREF - NOT DRIVEN 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 VREF+ (V) 2.75 7.8 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 VREF+ (V) 46 2.25 FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF + (VREF - NOT DRIVEN) FIGURE 12. SINAD AND SNR vs VREF + (VREF - NOT DRIVEN) 38 HI5766 Typical Performance Curves 80 fS = 60 MSPS fIN = 10MHz -3HD 70 dBc 65 SFDR 60 -2HD 55 -THD 50 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 VREF+ (V) 2.75 8.3 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 TA = 25oC VREF - NOT DRIVEN ENOB (BITS) (Continued) 8.6 fS = 60 MSPS TA = 25oC 8.5 10MHz 75 8.4 1MHz VCM (V) FIGURE 13. -2HD, -3HD, -THD AND SFDR vs VREF + (VREF - NOT DRIVEN) FIGURE 14. EFFECTIVE NUMBER OF BITS (ENOB) vs ANALOG INPUT COMMON MODE VOLTAGE 60 8.9 SUPPLY CURRENT (mA) 8.7 60 MSPS/1MHz ENOB (BITS) 8.5 8.3 60 MSPS/10MHz 8.1 7.9 7.7 7.5 -40 50 40 AICC 30 20 10 DICC2 0 -20 0 20 40 TEMPERATURE (oC) 60 80 10 20 30 40 fS (MSPS) 50 60 DICC1 1MHz ≤ fIN ≤ 15MHz TA = 25oC ICC FIGURE 15. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK FREQUENCY 1200 1000 800 IREF (µA) tOD (ns) 9.5 9.0 8.5 tOD 8.0 7.5 7.0 IREF + 600 400 200 IREF 0 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 6.5 6.0 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 FIGURE 17. REFERENCE CURRENT vs TEMPERATURE FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE 39 HI5766 Typical Performance Curves 0.90 0.85 0.80 0.75 DG (%) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -40 0 -20 0 20 40 TEMPERATURE (oC) 60 80 0.05 DP 0.1 0.15 fS = 17.72 MSPS DG 0.2 DP (DEGREES) (Continued) 0.25 0.70 0.65 0.60 DG (%) DP 0.55 0.50 0.45 DG 0.15 0.1 0.05 DP DG DP (DEGREES) 0.2 0.3 0.25 fS = 17.72 MSPS AVCC /DVCC1 = 5V ±5%, TA = 25oC 0.40 0 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 DVCC2 (V) FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE FIGURE 20. DIFFERENTIAL GAIN/PHASE vs SUPPLY VOLTAGE 3.30 0 -10 -20 fS = 60 MSPS fIN = 1MHz TA = 25oC 3.20 VDC (V) OUTPUT LEVEL (dB) -30 -40 -50 -60 -70 -80 -90 3.10 3.00 -40 -100 -20 0 20 40 TEMPERATURE (oC) 60 80 0 100 200 300 400 500 600 700 FREQUENCY (BIN) 800 900 1023 FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE FIGURE 22. 2048 POINT FFT PLOT 0 -10 -20 OUTPUT LEVEL (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 100 200 300 400 500 600 700 FREQUENCY (BIN) 800 900 1023 fS = 60 MSPS fIN = 10MHz TA = 25oC FIGURE 23. 2048 POINT FFT PLOT 40 HI5766 Detailed Description Theory of Operation The HI5766 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 24 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, φ1 and φ2 , derived from the master sampling clock. During the sampling phase, φ1 , the input signal is applied to the sampling capacitors, CS. At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, φ2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS. The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is synchronized to the external sampling clock by a double buffered latching technique. The output of the digital error correction circuit is available in two’s complement or offset binary format depending on the state of the Data Format Select (DFS) control input (see Table 1, A/D Code Table). Reference Voltage Inputs, VREF - and VREF+ The HI5766 is designed to accept two external reference voltage sources at the VREF input pins. Typical operation of the converter requires VREF+ to be set at +2.5V and VREF - to be set at 2.0V. However, it should be noted that the input structure of the VREF+ and VREF - input pins consists of a resistive voltage divider with one resistor of the divider (nominally 500Ω) connected between VREF+ and VREF - and the other resistor of the divider (nominally 2000Ω) connected between VREF - and analog ground. This allows the user the option of supplying only the +2.5V VREF+ voltage reference with the +2.0V VREF - being generated internally by the voltage division action of the input structure. The HI5766 is tested with VREF - equal to +2.0V and VREF+ equal to +2.5V yielding a fully differential analog input voltage range of ±0.5V. VREF+ and VREF - can differ from the above voltages. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at both of the reference voltage input pins, VREF+ and VREF -. φ1 VIN+ CH φ1 VOUT+ VOUT- φ1 φ2 CS -+ +CS VIN- φ1 φ1 CH φ1 FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD Analog Input, Differential Connection The analog input to the HI5766 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 25 and Figure 26) will give the best performance for the converter. As illustrated in the functional block diagram and the timing diagram in Figure 1, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverter stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final 10-bit digital data output of the converter. 41 VIN R VIN+ HI5766 VDC R -VIN VIN- FIGURE 25. AC COUPLED DIFFERENTIAL INPUT Since the HI5766 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 4.75V. HI5766 The performance of the ADC does not change significantly with the value of the analog input common mode voltage. A DC voltage source, VDC, equal to 3.2V (Typ), is made available to the user to help simplify circuit design when using an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent DC bias source and stays well within the analog input common mode voltage range over temperature. For the AC coupled differential input (Figure 25) assume the difference between VREF+, typically 2.5V, and VREF -, typically 2V, is 0.5V. Full scale is achieved when the VIN and -VIN input signals are 0.5VP-P, with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the VIN+ input is at VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ VIN- = +0.5V). Conversely, the converter will be at negative full scale when the VIN+ input is equal to VDC 0.25V and VIN- is at VDC + 0.25V (VIN+ - VIN- = -0.5V). The analog input can be DC coupled (Figure 26) as long as the inputs are within the analog input common mode voltage range (0.25V ≤ VDC ≤ 4.75V). VIN VDC R C VIN+ HI5766 VDC sinewave, then VIN+ is a 1VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will be at negative full scale when VIN+ is equal to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. In this case, VDC could range between 0.5V and 4.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the DC bias source, VDC , output of the HI5766. The single ended analog input can be DC coupled (Figure 28) as long as the input is within the analog input common mode voltage range. VIN VDC R C HI5766 VIN+ VDC VIN- FIGURE 28. DC COUPLED SINGLE ENDED INPUT -VIN VDC R VIN- FIGURE 26. DC COUPLED DIFFERENTIAL INPUT The resistors, R, in Figure 26 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. The resistor, R, in Figure 28 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5766. Digital Output Control and Clock Requirements The HI5766 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5766, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5766 will only be guaranteed at conversion rates above 1 MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1 MSPS will have to be performed before valid data is available. A Data Format Select (DFS) pin is provided which will determine the format of the digital data outputs. When at logic low, the data will be output in offset binary format. When at logic high, the data will be output in two’s complement format. Refer to Table 1 for further information. Analog Input, Single-Ended Connection The configuration shown in Figure 27 may be used with a single ended AC coupled input. VIN R VDC VIN+ HI5766 VIN- FIGURE 27. AC COUPLED SINGLE ENDED INPUT Again, assume the difference between VREF+, typically 2.5V, and VREF-, typically 2V, is 0.5V. If VIN is a 1VP-P 42 HI5766 TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) TWO’S COMPLEMENT OUTPUT CODE (DFS HIGH) CODE CENTER DESCRIPTION +Full Scale (+FS) -1/4 LSB +FS - 11/4 LSB +3/4 LSB -1/4 LSB -FS + 13/4 LSB -Full Scale (-FS) + 3/4 LSB M LM L S S S DIFFERENTIAL S BB B INPUT VOLTAGE B D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (VIN+ - VIN-) 0.499756V 0.498779V 732.422µV -244.141µV -0.498291V -0.499268V 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 NOTES: 8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage, (VREF + - VREF -) = 0.5V. 9. VREF+ = 2.5V and VREF - = 2V. The output enable pin, OE, when pulled high will three-state the digital outputs to a high impedance state. Set the OE input to logic low for normal operation. OE INPUT 0 1 DIGITAL DATA OUTPUTS Active High Impedance error removed. Full Scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Supply and Ground Considerations The HI5766 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The digital data outputs also have a separate supply pin, DVCC2 , which can be powered from a 3V or 5V supply. This allows the outputs to interface with 3V logic if so desired. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5766 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply should be isolated with a ferrite bead from the digital supply. Refer to the application note “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. Power Supply Sensitivity Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5766. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from Full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Static Performance Definitions Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02 where: VCORR = 0.5 dB. Full-Scale Error (FSE) The last code transition should occur for an analog input that is 3/4 LSBs below positive Full Scale (+FS) with the offset 43 VCORR adjusts the SINAD, and hence the ENOB, for the amount the analog input signal is below full scale. HI5766 Signal To Noise and Distortion Ratio (SINAD) SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS/2, excluding DC. Video Definitions Differential Gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance signal as it is offset through the input voltage range of an ADC. Signal To Noise Ratio (SNR) SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS/2 excluding the fundamental, the first five harmonics and DC. Differential Gain (DG) Differential Gain is the peak difference in chrominance amplitude (in percent) relative to the reference burst. Differential Phase (DP) Differential Phase is the peak difference in chrominance phase (in degrees) relative to the reference burst. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Aperture Delay (tAP) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS/2. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale. Aperture Jitter (tAJ) Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Transient Response Transient response is measured by providing a full scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Data Latency (tLAT) After the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. This delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital data lags the analog input sample by 7 sample clock cycles. Over-Voltage Recovery Over-Voltage Recovery is measured by providing a full scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Full Power Input Bandwidth (FPBW) Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency. Power-Up Initialization This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 44