ISL12025

® ISL12025 Data Sheet August 13, 2008 FN6371.3 Real-Time Clock/Calendar with I2C Bus™ and EEPROM The ISL12025 device is a low power real-time clock with timing and crystal compensation, clock/calender, 64-bit unique ID, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512x8-bit EEPROM, in a 16 Bytes per page format. The oscillator uses an external, low-cost 32.768kHz crystal. The real-time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Features • Real-Time Clock/Calendar - Tracks Time in Hours, Minutes and Seconds - Day of the Week, Day, Month and Year • 64-Bit Unique ID • Two Non-Volatile Alarms - Settable on the Second, Minute, Hour, Day of the Week, Day or Month - Repeat Mode (Periodic Interrupts) • Automatic Backup to Battery or Super Cap • On-Chip Oscillator Compensation - Internal Feedback Resistor and Compensation Capacitors - 64 Position Digitally Controlled Trim Capacitor - 6 Digital Frequency Adjustment Settings to ±30ppm • 512x8-Bits of EEPROM - 16-Bytes Page Write Mode (32 total pages) - 8 Modes of Block Lock™ Protection - Single Byte Write Capability • High Reliability - Data Retention: 50 years - Endurance: 2,000,000 Cycles Per Byte • I2C Interface - 400kHz Data Transfer Rate • 800nA Battery Supply Current • Package Options - 8 Ld SOIC and 8 Ld TSSOP Packages • Pb-Free (RoHS Compliant) Ordering Information PART NUMBER (Note) TEMP. PART VRESET RANGE (°C) MARKING VOLTAGE 2.63V 2.63V PACKAGE PKG. (Pb-Free) DWG. # M8.15 ISL12025IBZ* 12025 IBZ ISL12025IVZ* 2025 IVZ -40 to +85 8 Ld SOIC -40 to +85 8 Ld TSSOP M8.173 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL12025 (8 LD SOIC) TOP VIEW X1 X2 RESET GND 1 2 3 4 8 7 6 5 VDD VBAT SCL SDA Applications • Utility Meters • Audio/Video Components • Modems • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Fixed Broadband Wireless Equipment • Pagers/PDA • POS Equipment • Test Meters/Fixtures SCL SDA GND RESET ISL12025 (8 LD TSSOP) TOP VIEW VBAT VDD X1 X2 1 2 3 4 8 7 6 5 • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2006, 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL12025 Block Diagram OSC COMPENSATION 32.768KHZ X1 OSCILLATOR X2 TIMER FREQUENCY 1Hz CALENDAR DIVIDER LOGIC TIME KEEPING REGISTERS (SRAM) BATTERY SWITCH CIRCUITRY VDD VBAT SCL SDA MASK SERIAL INTERFACE DECODER CONTROL DECODE LOGIC CONTROL/ REGISTERS (EEPROM) STATUS REGISTERS (SRAM) ALARM COMPARE ALARM REGS (EEPROM) 4k EEPROM ARRAY 8 RESET WATCHDOG TIMER LOW VOLTAGE RESET Pin Descriptions PIN NUMBER SOIC 1 2 3 TSSOP 3 4 5 SYMBOL X1 X2 RESET BRIEF DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground. Ground. Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Power Supply. 4 5 6 7 8 6 7 8 1 2 GND SDA SCL VBAT VDD 2 FN6371.3 August 13, 2008 ISL12025 Absolute Maximum Ratings Voltage on VDD, VBAT, SCL, SDA, and RESET pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on X1 and X2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 120 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. DC Electrical Specifications Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C and VDD = 3.3V. CONDITIONS MIN (Note 12) 2.7 1.8 TYP MAX (Note 12) 5.5 5.5 UNIT V V SYMBOL VDD VBAT PARAMETER Main Power Supply Backup Power Supply Electrical Specifications SYMBOL IDD1 PARAMETER Supply Current with I2C Active CONDITIONS VDD = 2.7V VDD = 5.5V IDD2 Supply Current for Non-Volatile Programming Supply Current for Main Timekeeping (Low Power Mode) Battery Supply Current VDD = 2.7V VDD = 5.5V VDD = VSDA = VSCL = 2.7V VDD = VSDA = VSCL = 5.5V VBAT = 1.8V, VDD = VSDA = VSCL= 0V VBAT = 3.0V, VDD = VSDA = VSCL= 0V IBATLKG VTRIP Battery Input Leakage VBAT Mode Threshold VDD = 5.5V, VBAT = 1.8V -100 1.8 2.2 30 50 10 800 850 MIN (Note 12) TYP MAX (Note 12) 500 800 2.5 3.5 10 20 1000 1200 100 2.6 UNIT µA µA mA mA µA µA nA nA nA V mV mV V/ms 7 7, 10 7, 10 8 3, 6, 7 3, 6, 7 5 3, 4, 5 NOTES 3, 4, 5 IDD3 IBAT VTRIPHYS VTRIP Hysteresis VBATHYS VBAT Hysteresis VDD SRVDD Negative Slew rate RESET OUTPUT VOL Output Low Voltage VDD = 5.5V IOL = 3mA VDD = 2.7V IOL = 1mA ILO Output Leakage Current VDD = 5.5V VOUT = 5.5V 100 0.4 0.4 400 V V nA 3 FN6371.3 August 13, 2008 ISL12025 Watchdog Timer/Low Voltage Reset Parameters SYMBOL tRPD tPURST VRVALID VRESET PARAMETER VDD Detect to RESET LOW Power-up Reset Time-Out Delay Minimum VDD for Valid RESET Output ISL12025-4.5A Reset Voltage Level ISL12025 Reset Voltage Level ISL12025-3 Reset Voltage Level ISL12025-2.7A Reset Voltage Level ISL12025-2.7 Reset Voltage Level tWDO Watchdog Timer Period 32.768kHz crystal between X1 and X2 100 1.0 4.59 4.33 3.04 2.87 2.58 1.70 725 225 tRST tRSP Watchdog Timer Reset Time-Out Delay I2C Interface Minimum Restart Time 32.768kHz crystal between X1 and X2 225 1.2 4.64 4.38 3.09 2.92 2.63 1.75 750 250 250 4.69 4.43 3.14 2.97 2.68 1.801 775 275 275 CONDITIONS MIN (Note 12) TYP (Note 5) 500 250 400 MAX (Note 12) UNITS ns ms V V V V V V s ms ms ms µs NOTES 9 EEPROM SPECIFICATIONS EEPROM Endurance EEPROM Retention Temperature ≤+75°C 2,000,000 50 Cycles Years Serial Interface (I2C) Specifications SYMBOL VIL VIH PARAMETER SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage CONDITIONS SBIB = 1 (Under VDD mode) SBIB = 1 (Under VDD mode) SBIB = 1 (Under VDD mode) IOL = 4mA VIN = 5.5V VIN = 5.5V MIN (Note 12) -0.3 0.7xVDD 0.05xVDD 0 0.1 0.1 0.4 10 10 TYP MAX (Note 12) 0.3xVDD VDD + 0.3 UNITS V V V V µA µA NOTES Hysteresis SDA and SCL Input Buffer Hysteresis VOL ILI ILO SDA Output Buffer LOW Voltage Input Leakage Current on SCL I/O Leakage Current on SDA TIMING CHARACTERISTICS fSCL tIN tAA SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 1300 400 50 900 kHz ns ns tBUF Time the Bus Must Be Free before SDA crossing 70% of VDD during a the Start of a New Transmission STOP condition, to SDA crossing 70% of VDD during the following START condition. ns 4 FN6371.3 August 13, 2008 ISL12025 Serial Interface (I2C) Specifications (Continued) SYMBOL tLOW tHIGH tSU:STA tHD:STA PARAMETER Clock LOW Time Clock HIGH Time START Condition Set-up Time START Condition Hold Time CONDITIONS Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. From SCL falling edge crossing 70% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. MIN (Note 12) 1300 600 600 600 TYP MAX (Note 12) UNITS ns ns ns ns NOTES tSU:DAT Input Data Set-up Time 100 ns tHD:DAT Input Data Hold Time 0 ns tSU:STO STOP Condition Set-up Time 600 ns tHD:STO STOP Condition Hold Time for Read or Volatile Only Write Output Data Hold Time 600 ns tDH 0 ns Cpin tWC tR tF Cb RPU SDA and SCL Pin Capacitance Non-Volatile Write Cycle Time SDA and SCL Rise Time SDA and SCL Fall Time Capacitive loading of SDA or SCL From 30% to 70% of VDD From 70% to 30% of VDD Total on-chip and off-chip 20 + 0.1xCb 20 + 0.1xCb 10 1 12 10 20 250 250 400 pF ms ns ns pF kΩ 10 11 11 11 11 SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and Off-chip tF. For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ NOTES: 3. RESET Inactive (no reset). 4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz. 5. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V. 6. Bit BSW = 0 (Standard Mode), ATR=00h, VBAT ≥1.8V. 7. Specified at +25°C. 8. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 9. Parameter is not 100% tested. 10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle. 11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5 FN6371.3 August 13, 2008 ISL12025 Timing Diagrams tF tHIGH tLOW tR tHD:STO SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tAA SDA (OUTPUT TIMING) tDH tBUF FIGURE 1. BUS TIMING SCL SDA 8TH BIT OF LAST BYTE ACK tWC STOP CONDITION START CONDITION FIGURE 2. WRITE CYCLE TIMING tRSP tRSPtWDO tRST tRSP>tWDO tRST SCL SDA RESET START STOP START NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (tRST). FIGURE 3. WATCHDOG TIMING VRESET VDD tPURST tRPD tR RESET tF VRVALID tPURST FIGURE 4. RESET TIMING 6 FN6371.3 August 13, 2008 ISL12025 Typical Performance Curves 4.0 3.5 3.0 2.5 IBAT (µA) 2.0 1.5 1.0 0.5 0.0 1.8 2.3 2.8 3.3 SCL, SDA PULL-UPS = VBAT BSW = 0 OR 1 3.8 VBAT (V) 4.3 4.8 5.3 BSW = 0 OR 1 SCL, SDA PULL-UPS = 0V IBAT (µA) Temperature is +25°C unless otherwise specified 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.8 2.3 2.8 3.3 3.8 VBAT(V) 4.3 4.8 5.3 SCL, SDA PULL-UPS = 0V BSW = 0 OR 1 FIGURE 5. IBAT vs VBAT, SBIB = 0 FIGURE 6. IBAT vs VBAT, SBIB = 1 5.0 4.5 4.0 3.5 IDD (µA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 TEMPERATURE (°C) 55 65 75 85 VDD = 3.3V IBAT (µA) VDD = 5.5V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 TEMPERATURE (°C) 55 65 75 85 VBAT = 3.0V FIGURE 7. IDD3 vs TEMPERATURE FIGURE 8. IBAT vs TEMPERATURE 4.5 PPM CHANGE FROM ATR = 0 4.0 3.5 3.0 IDD (µA) 2.5 2.0 1.5 1.0 0.5 0.0 1.8 2.3 2.8 3.3 3.8 VDD (V) 4.3 4.8 5.3 80 60 40 20 0 -20 -40 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28 ATR SETTING FIGURE 9. IDD3 vs VDD FIGURE 10. ΔFOUT vs ATR SETTING 7 FN6371.3 August 13, 2008 ISL12025 Description The ISL12025 device is a Real-Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Bytes per page format, oscillator compensation, CPU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. The Real-Time Clock keeps track of time with separate registers for Hours, Minutes and Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. The 64-bit unique ID is a random numbers programmed, verified and locked at the factory and it is only accessible for reading and cannot be altered by the customer. The Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register. There is a repeat mode for the alarms allowing a periodic interrupt. The ISL12025 device integrates CPU Supervisory functions (POR, WDT) and Battery Switch. There is Power-On-Reset (RESET) output with 250ms delay from power-on. It will also assert RESET when VDD goes below the specified threshold. The Vtrip threshold is selectable via VTS2/VTS1/VTS0 registers to five (5) preselected levels. There is WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. The WatchDog Timer activates the RESET pin when it expires. The device offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or Super Cap. The entire ISL12025 device is fully operational from 2.7V to 5.5V and the clock/calendar portion of the ISL12025 device remains fully operational down to 1.8V (Standby Power Mode). The ISL12025 device provides 4k bits of EEPROM with eight modes of BlockLock™ control. The BlockLock™ allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as VDD. The output circuitry controls the fall time of the output signal with the use of a slope-controlled pull-down. The circuit is designed for 400kHz I2C interface speed. VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event the VDD supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used. RESET The RESET signal output can be used to notify a host processor that the Watchdog timer has expired or the VDD voltage supply has dipped below the VRESET threshold. It is an open drain, active LOW output. Recommended value for the pull-up resistor is 10kΩ. If unused, it can be tied to ground. X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12025 to supply a timebase for the real-time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over-temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit (see Figure 11). NOTE: NO EXTERNAL COMPENSATION RESISTORS OR CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO BE CONNECTED TO THE X1 AND X2 PINS. X1 X2 FIGURE 11. RECOMMENDED CRYSTAL CONNECTION Pin Descriptions Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). The pull-up resistor on this pin must use the same voltage source as VDD. Real-Time Clock Operation The Real-Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 8 FN6371.3 August 13, 2008 ISL12025 24 hour or AM/PM format. When the ISL12025 powers up after the loss of both VDD and VBAT, the clock will not operate until at least one byte is written to the clock register. addresses from 0000h to 003Fh. The defined addresses are described in the Table 2. Writing to and reading from the undefined addresses are not recommended. Reading the Real-Time Clock The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real-Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. CCR Access The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (see “Writing to the Clock/Control Registers” on page 13.) The CCR is divided into 6 sections. These are: 1. Alarm 0 (8 bytes; non-volatile) 2. Alarm 1 (8 bytes; non-volatile) 3. Control (5 bytes; non-volatile) 4. Unique ID (8 bytes, non-volatile) 5. Real-Time Clock (8 bytes; volatile) 6. Status (1 byte; volatile) Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. A read or write can begin at any address in the CCR. It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register. Writing to the Real-Time Clock The time and date may be set by writing to the RTC registers. RTC Register should be written ONLY with Page Write. To avoid changing the current time by an incomplete write operation, write to the all 8 bytes in one write operation. When writing the RTC registers, the new time value is loaded into a separate buffer at the falling edge of the clock during the Acknowledge. This new RTC value is loaded into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation, the RTC will reflect the newly loaded data beginning with the next “one second” clock cycle after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any non-volatile write sequences. Accuracy of the Real-Time Clock The accuracy of the Real-Time Clock depends on the accuracy of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “Application Section” on page 21. Real-Time Clock Registers (Volatile) SC, MN, HR, DT, MO, YR: Clock/Calendar Registers These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99. Clock/Control Registers (CCR) The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory 9 FN6371.3 August 13, 2008 ISL12025 DW: Day of the Week Register This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’. OSCF: Oscillator Fail Indicator This bit is set to “1” if the oscillator is not operating, or is operating but has clock jitter which does not affect the accuracy of RTC counting. The bit is set to “0” if the oscillator is functioning and does not have clock jitter. This bit is read only, and is set/reset by hardware. RWEL: Register Write Enable Latch This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. Y2K: Year 2000 Register Can have value 19 or 20. As of the date of the introduction of this device, there would be no real use for the value 19 in a true real-time clock, however. 24 Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21 bit functions as an AM/PM indicator with a ‘1’, representing PM. The clock defaults to standard time with H21 = 0. WEL: Write Enable Latch The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Status Register (SR) (Volatile) The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR). TABLE 1. STATUS REGISTER (SR) ADDR 003Fh Default 7 BAT 0 6 AL1 0 5 4 3 0 0 2 RWEL 0 1 WEL 0 0 RTCF 1 RTCF: Real-Time Clock Fail Bit This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set internally when the device powers up after having lost all power to the device (both VDD and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not result in setting the RTCF bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’. AL0 OSCF 0 0 BAT: Battery Supply This bit set to “1” indicates that the device is operating from VBAT, not VDD. It is a read-only bit and is set/reset by hardware (ISL12025 internally). Once the device begins operating from VDD, the device sets this bit to “0”. Unused Bits: Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location. AL1, AL0: Alarm Bits These bits announce if either alarm 0 or alarm 1 match the real-time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. 10 FN6371.3 August 13, 2008 ISL12025 TABLE 2. CLOCK/CONTROL MEMORY MAP BIT ADDR. 003F 0037 0036 0035 0034 0033 0032 0031 0030 0027 0026 0025 0024 0023 0022 0021 0020 0014 0013 0012 0011 0010 000F 000E 000D 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 Alarm0 (EEPROM) Alarm1 (EEPROM) Control (EEPROM) Device ID TYPE Status RTC (SRAM) REG NAME SR Y2K DW YR MO DT HR MN SC ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 PWR DTR ATR INT BL Y2K1 DWA1 YRA1 MOA1 DTA1 HRA1 MNA1 SCA1 Y2K0 DWA0 YRA0 MOA0 DTA0 HRA0 MNA0 SCA0 EMO0 EDT0 EHR0 EMN0 ESC0 EMO1 EDT1 EHR1 EMN1 ESC1 0 EDW0 7 BAT 0 0 Y23 0 0 MIL 0 0 ID77 ID67 ID57 ID47 ID37 ID27 ID17 ID07 SBIB 0 0 IM BP2 0 EDW1 6 AL1 0 0 Y22 0 0 0 M22 S22 ID76 ID66 ID56 ID46 ID36 ID26 ID16 ID06 BSW 0 0 AL1E BP1 0 0 5 AL0 Y2K21 0 Y21 0 D21 H21 M21 S21 ID75 ID65 ID55 ID45 ID35 ID25 ID15 ID05 0 0 ATR5 AL0E BP0 A1Y2K21 0 4 OSCF Y2K20 0 Y20 G20 D20 H20 M20 S20 ID74 ID64 ID54 ID44 ID34 ID24 ID14 ID04 0 0 ATR4 0 WD1 A1Y2K20 0 3 0 Y2K13 0 Y13 G13 D13 H13 M13 S13 ID73 ID63 ID53 ID43 ID33 ID23 ID13 ID03 0 0 ATR3 0 WD0 A1Y2K13 0 2 RWEL 0 DY2 Y12 G12 D12 H12 M12 S12 ID72 ID62 ID52 ID42 ID32 ID22 ID12 ID02 VTS2 DTR2 ATR2 0 0 0 DY2 1 WEL 0 DY1 Y11 G11 D11 H11 M11 S11 ID71 ID61 ID51 ID41 ID31 ID21 ID11 ID01 VTS1 DTR1 ATR1 0 0 0 DY1 0 RTCF Y2K10 DY0 Y10 G10 D10 H10 M10 S10 ID70 ID60 ID50 ID40 ID30 ID20 ID10 ID00 VTS0 DTR0 ATR0 0 0 A1Y2K10 DY0 19/20 0-6 19/20 0-6 0-99 1-12 1-31 0-23 0-59 0-59 RANGE DEFAULT 01h 20h 00h 00h 00h 01h 00h 00h 00h * * * * * * * * 4Xh 00h 00h 00h 18h 20h 00h 00h 00h 00h 00h 00h 20h 00h 00h 00h 00h 00h 00h Unused - Default = RTC Year value (No EEPROM) - Future expansion 0 0 0 A1M22 A1S22 0 0 0 A1D21 A1H21 A1M21 A1S21 A0Y2K21 0 A1G20 A1D20 A1H20 A1M20 A1S20 A0Y2K20 0 A1G13 A1D13 A1H13 A1M13 A1S13 A0Y2K13 0 A1G12 A1D12 A1H12 A1M12 A1S12 0 DY2 A1G11 A1D11 A1H11 A1M11 A1S11 0 DY1 A1G10 A1D10 A1H10 A1M10 A1S10 A0Y2K10 DY0 1-12 1-31 0-23 0-59 0-59 19/20 0-6 Unused - Default = RTC Year value (No EEPROM) - Future expansion 0 0 0 A0M22 A0S22 0 A0D21 A0H21 A0M21 A0S21 A0G20 A0D20 A0H20 A0M20 A0S20 A0G13 A0D13 A0H13 A0M13 A0S13 A0G12 A0D12 A0H12 A0M12 A0S12 A0G11 A0D11 A0H11 A0M11 A0S11 A0G10 A0D10 A0H10 A0M10 A0S10 1-12 1-31 0-23 0-59 0-59 NOTE: (Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation (see device ordering information). *indicates set at the factory, read-only) 11 FN6371.3 August 13, 2008 ISL12025 Alarm Registers (Non-Volatile) Alarm0 and Alarm1 The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. See “Device Operation” on page 13 and “Application Section” on page 21 for more information. frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation. X1 CX1 CRYSTAL OSCILLATOR X2 CX2 Control Registers (Non-Volatile) The Control Bits and Registers described in the following are non-volatile. FIGURE 12. DIAGRAM OF ATR BL Register BP2, BP1, BP0 - Block Protect Bits The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3. TABLE 3. PROTECTED ADDRESSES ISL12025 None (Default) 180h – 1FFh 100h – 1FFh 000h – 1FFh 000h – 03Fh 000h – 07Fh 000h – 0FFh 000h – 1FFh BP2 BP1 BP0 ARRAY LOCK None Upper 1/4 Upper 1/2 Full Array First 4 Pages First 8 Pages First 16 Pages Full Array The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 12). The value of CX1 and CX2 is given by Equation 1: C X = ( 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 ) pF (EQ. 1) The effective series load capacitance is the combination of CX1 and CX2: C LOAD = ---------------------------------X1 X2 1 1 1 ⎛ ---------- + ---------- ⎞ ⎝C C⎠ (EQ. 2) ⎠ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 C LOAD = ⎛ ---------------------------------------------------------------------------------------------------------------------------- ⎞ pF ⎝ 2 For example: CLOAD(ATR = 00000) = 12.5pF, CLOAD(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. Oscillator Compensation Registers There are two trimming options. - ATR. Analog Trimming Register - DTR. Digital Trimming Register These registers are non-volatile. The combination of analog and digital trimming can give up to -64ppm to +110ppm of total adjustment. DTR Register - DTR2, DTR1, DTR0: Digital Trimming Register The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DTR2 is a sign bit, where: DTR2 = 0 means frequency compensation is >0. DTR2 = 1 means frequency compensation is