ISL21007

® ISL21007 Data Sheet April 12, 2007 FN6326.1 Precision, Low Noise FGA™ Voltage References The ISL21007 FGA™ voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil’s proprietary Floating Gate Analog technology. The ISL21007 features very low noise (4µVP-P for 0.1Hz to 10Hz) and very low operating current (150µA, Max). In addition, the ISL21007 family features guaranteed initial accuracy as low as ±0.5mV. This combination of high initial accuracy, low drift, and low output noise performance of the ISL21007 enables versatile high performance control and data acquisition applications with low power consumption. Features • Reference Output Voltage . . . . . . . . . . . . . . .1.25V, 2.50V • Initial Accuracy . . . . . . . . . . . . . . . . . . . . ±0.5mV (B grade) • Input Voltage Range: . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V • Low Output Voltage Noise . . . . . . 4µVP-P (0.1Hz to 10Hz) • Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150µA (Max) • Temperature Coefficient . . . . . . . . . . . . 3ppm/°C (B grade) • Operating Temperature Range. . . . . . . . . -40°C to +125°C • Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC • Pb-Free Plus Anneal Available (RoHS Compliant) Available Options VOUT OPTION (V) 1.250 1.250 1.250 2.500 2.500 2.500 INITIAL ACCURACY (mV) ±0.5 ±1.0 ±2.0 ±0.5 ±1.0 ±2.0 TEMPCO. (ppm/°C) 3 5 10 3 5 10 Applications • High Resolution A/Ds and D/As • Digital Meters • Bar Code Scanners • Basestations • Battery Management/Monitoring • Industrial/Instrumentation Equipment PART NUMBER ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z Pinout ISL21007 (8 LD SOIC) TOP VIEW GND or NC 1 VIN 2 DNC 3 GND 4 8 DNC 7 DNC 6 VOUT 5 TRIM 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL21007 Ordering Information PART NUMBER (Note) ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z PART MARKING 21007BF Z12 21007CF Z12 21007DF Z12 21007BF Z25 21007CF Z25 21007DF Z25 VOUT OPTION (V) 1.250 1.250 1.250 2.500 2.500 2.500 GRADE ±0.5mV, 3ppm/°C ±1.0mV, 5ppm/°C ±2.0mV, 10ppm/°C ±0.5mV, 3ppm/°C ±1.0mV, 5ppm/°C ±2.0mV, 10ppm/°C TEMP. RANGE (°C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add “-TK” suffix for tape and reel 2 FN6326.1 April 12, 2007 ISL21007 Pin Descriptions PIN NUMBER 1 2 4 5 6 3, 7, 8 PIN NAME GND or NC VIN GND TRIM VOUT DNC Ground Connection Power Supply Input Connection Voltage Reference Output Connection Allows user trim ±2.5% Do Not Connect; Internal Connection – Must Be Left Floating Do Not Connect; Internal Connection - Must Be Left Floating DESCRIPTION Typical Application Circuit 1 +3V C1 10µF 2 3 4 GND VIN NC GND NC NC VOUT NC 8 7 6 5 ISL21007-12, 25 SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK A0 A1 A2 SI SO /RDY UP DOWN OE /CS CLR VCC VH VL VREF VSS VOUT VBUF VFB 20 19 18 17 16 15 14 13 12 11 LOW NOISE DAC OUTPUT C1 0.001µF FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC 3 FN6326.1 April 12, 2007 ISL21007 Absolute Voltage Ratings Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Max Voltage VIN to Gnd . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Max Voltage VOUT to Gnd (10s). . . . . . . . . . . . . . . -0.5V to VOUT + 1 Voltage on “DNC” pins . . . . No connections permitted to these pins. Lead Temperature, soldering (10s) . . . . . . . . . . . . . . . . . . . . +260°C ESD Rating Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV Thermal Information Continuous Power Dissipation (TA = +70°C) (Note 1) 8 Lead SOIC derate 5.88mW/°C above +70°C . . . . . . 471mW Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Common Electrical Specifications (ISL21007-12, -25)TA = -40°C to +125°C, unless otherwise specified. PARAMETER VIN VOA DESCRIPTION Input Voltage Range VOUT Accuracy @ TA = +25°C ISL21007B ISL21007C ISL21007D TC VOUT Output Voltage Temperature Coefficient (Note 2) ISL21007B ISL21007C ISL21007D IIN ΔVOUT/Δt Supply Current Long Term Stability (Note 4) Trim Range tR Turn on Settling Time Ripple Rejection eN VN Output Voltage Noise Broadband Voltage Noise Noise Density VOUT = ±0.1% f = 10kHz 0.1Hz ≤ f ≤ 10Hz 10Hz ≤ f ≤ 1kHz f = 1kHz TA = +25°C ±2.0 75 TBD ±2.5 120 60 4 2.2 60 CONDITIONS MIN 2.7 -0.5 -1.0 -2.0 TYP MAX 5.5 +0.5 +1.0 +2.0 3 5 10 150 UNIT V mV mV mV ppm/°C ppm/°C ppm/°C µA ppm/√1kHrs % µs dB µVP-P µVRMS nV/√Hz Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified. PARAMETER VOUT ΔVOUT /ΔVIN ΔVOUT/ΔIOUT DESCRIPTION Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA ≤ IOUT ≤ 7mA Sinking: -7mA ≤ IOUT ≤ 0mA ISC ΔVOUT/ΔTA Short Circuit Current Thermal Hysteresis (Note 3) TA = +25°C, VOUT tied to GND ΔTA = +165°C CONDITIONS MIN TYP 1.250 100 10 20 40 50 700 100 150 MAX UNIT V µV/V µV/mA µV/mA mA ppm 4 FN6326.1 April 12, 2007 ISL21007 Electrical Specifications (ISL21007-25, VOUT = 2.50V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified PARAMETER VOUT ΔVOUT /ΔVIN ΔVOUT/ΔIOUT ISC ΔVOUT/ΔTA NOTES: 2. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40°C to +125°C = +165°C. 3. Thermal Hysteresis is the change of VOUT measured @ TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled from +25°C to +125°C to -40°C to +25°C. 4. FGA voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are significantly smaller with time, asymptotically approaching zero beyond 1,000 hours. Because of this decreasing characteristics, long term drift is specified in ppm/√1kHrs. DESCRIPTION Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA ≤ IOUT ≤ 5mA Sinking: -5mA ≤ IOUT ≤ 0mA Short Circuit Current Thermal Hysteresis (Note 3) TA = +25°C, VOUT tied to GND ΔTA = +165°C CONDITIONS MIN TYP 2.500 50 10 20 50 50 200 100 150 MAX UNIT V µV/V µV/mA µV/mA mA ppm Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) 120 UNIT 3 100 80 IIN (µA) 60 40 20 0 2.5 UNIT 1 IIN (µA) UNIT 2 90 85 80 75 70 65 60 2.5 -40°C +25°C +125°C 95 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 VIN (V) FIGURE 2. IIN vs VIN (3 UNITS) FIGURE 3. IIN vs VIN OVER TEMPERATURE VOUT (V) (NORMALIZED TO 1.25V AT VIN = 3.0V) 1.25015 ΔVO (µV) (NORMALIZED TO VIN = 3.0V) 1.25010 UNIT 3 1.25005 1.25000 UNIT 2 1.24995 1.24990 UNIT 1 1.24985 1.24980 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 150 100 50 0 -50 -100 -150 -200 -250 -300 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 +25°C -40°C +125°C FIGURE 4. LINE REGULATION (3 UNITS) FIGURE 5. LINE REGULATION OVER TEMPERATURE 5 FN6326.1 April 12, 2007 ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) 0.15 +25°C 0.10 0.05 VOUT (V) ΔVOUT (mV) 0.00 -0.05 -0.10 -0.15 -7 -40°C +125°C 1.25005 1.25000 1.24995 1.24990 1.24985 1.24980 -6 -5 -4 SINKING -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4567 SOURCING 1.24975 -40 UNIT 3 UNIT 2 (Continued) 1.25010 UNIT 1 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 FIGURE 6. LOAD REGULATION OVER TEMPERATURE FIGURE 7. VOUT vs TEMPERATURE (3 UNITS) X: 5µs/DIV Y: 500mV/DIV X: 5µs/DIV Y: 500mV/DIV FIGURE 8. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD FIGURE 9. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE X: 20µs/DIV Y: 1V/DIV 120 1nF LOAD 100 80 ZOUT (Ω) VIN 60 40 10nF LOAD NO LOAD VOUT = 1.25V (FOR TYP IIN) 20 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 10. TURN ON TIME FIGURE 11. ZOUT vs FREQUENCY 6 FN6326.1 April 12, 2007 ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) GAIN IS x1000, NOISE IS 4µVp-p (Continued) NO OUTPUT CAPACITANCE X: 50µs/DIV Y: 1V/DIV +7mA 2mV/DIV -7mA FIGURE 12. VOUT NOISE, 0.1Hz to 10Hz FIGURE 13. LOAD TRANSIENT RESPONSE 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10nF LOAD 1nF LOAD VIN (DC) = 3V VIN (AC) = 50mVP-P NO LOAD FREQUENCY (Hz) FIGURE 14. PSRR vs CAPACITIVE LOADS 7 FN6326.1 April 12, 2007 ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) 120 UNIT 3 100 80 IIN (µA) 60 40 20 0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 UNIT 1 UNIT 2 IIN (µA) 100 95 90 85 80 75 70 65 60 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 +25°C -40°C +125°C FIGURE 15. IIN vs VIN (3 UNITS) FIGURE 16. IIN vs VIN OVER TEMPERATURE VOUT (V) (NORMALIZED TO 2.5V AT VIN = 3V) 2.50020 ΔVO (µV) (NORMALIZED TO VIN = 3.0V) 2.50010 2.50000 UNIT 2 2.49990 2.49980 2.49970 2.49960 2.5 UNIT 3 UNIT 1 100 50 0 -50 -100 -150 -200 -250 -300 -350 -400 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 -40°C +25°C +125°C 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 FIGURE 17. LINE REGULATION (3 UNITS) 0.60 0.40 0.20 ΔVOUT (mV) VOUT (V) 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 +25°C -40°C +125°C FIGURE 18. LINE REGULATION OVER TEMPERATURE 2.5003 2.5002 2.5001 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 -40 -20 0 UNIT 3 20 40 60 80 TEMPERATURE (°C) 100 120 140 UNIT 1 UNIT 2 NORMALIZED TO +25°C SINKING OUTPUT CURRENT (mA) SOURCING FIGURE 19. LOAD REGULATION OVER TEMPERATURE FIGURE 20. VOUT vs TEMPERATURE (3 UNITS) 8 FN6326.1 April 12, 2007 ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued) X: 5µs/DIV Y: 500mV/DIV X: 5µs/DIV Y: 500mV/DIV FIGURE 21. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD FIGURE 22. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE X: 20µs/DIV Y: 1V/DIV 160 140 120 VIN ZOUT (Ω) 100 80 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1nF LOAD NO LOAD 10nF LOAD VOUT = 2.5V (FOR TYP IIN) FIGURE 23. TURN ON TIME FIGURE 24. ZOUT vs FREQUENCY GAIN IS x1000, NOISE IS 4µVP-P NO OUTPUT CAPACITANCE X: 50µs/DIV Y: 500mV/DIV +5mA 2mV/DIV -5mA FIGURE 25. VOUT NOISE, 0.1Hz to 10Hz FIGURE 26. LOAD TRANSIENT RESPONSE 9 FN6326.1 April 12, 2007 ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued) 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10nF LOAD 1nF LOAD VIN (DC) = 3V VIN (AC) = 50mVP-P NO LOAD FREQUENCY (Hz) FIGURE 27. PSRR vs CAPACITIVE LOADS Applications Information FGA Technology The ISL21007 voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). The process used for these reference devices is a floating gate CMOS process, and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections. Board Mounting Considerations For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package which will subject the die to mild stresses when the PC board is heated and cooled and slightly changes shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. Noise Performance and Reduction The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4µVP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40µVP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1 pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10 times the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21007 is not designed to drive heavily capactive loads, so for load capacitances above 0.001µF the noise reduction network shown in Figure 28 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to 1MHz using this network with a 0.01µF capacitor and a 2kΩ resistor in series with a 10µF capacitor. Also, transient response is improved with higher value output capacitor. The Micropower Operation The ISL21007 consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 75µA and noise is 4µVP-P benefitting precision, low noise portable applications such as handheld meters and instruments. Data Converters in particular can utilized the ISL21007 as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise. 10 FN6326.1 April 12, 2007 ISL21007 0.01µF value can be increased for better load transient response with little sacrifice in output stability. VIN = 3.0V 10µF 0.1µF VIN VO ISL21007 GND 0.01µF 10µF 2kΩ FIGURE 28. HANDLING HIGH LOAD CAPACITANCE Turn-On Time The ISL21007 devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 120µs. This is shown in Figure 10. Circuit design must take this into account when looking at power up delays or sequencing. Temperature Coefficient The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH – VLOW), and divide by the temperature extremes of measurement (THIGH – TLOW). The result is divided by the nominal reference voltage (at T = +25°C) and multiplied by 106 to yield ppm/°C. This is the “Box” method for specifying temperature coefficient. Output Voltage Adjustment The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from Vout to ground, and connecting the wiper to the TRIM pin. The TRIM input is high impedance, so no series resistance is needed. The resistor in the potentiometer should be a low tempco (