®
ISL23511
Single Push Button Controlled Potentiometer (XDCP™)
Data Sheet December 3, 2007 FN6588.0
Low Noise, Low Power, 32 Taps, Push Button Controlled Potentiometer
The Intersil ISL23511 is a three-terminal digitally-controlled potentiometer (XDCP) implemented by a resistor array composed of 31 resistive elements and a wiper switching network. The ISL23511 features a push button control, a shutdown mode, as well as an industry-leading µTQFN package. The push button control has individual PU and PD inputs for adjusting the wiper. To eliminate redundancy the wiper position will automatically increment or decrement if one of these inputs is held longer than one second. Forcing both PU and PD low for more than two seconds activates shutdown mode. Shutdown mode disconnects the top of the resistor chain and moves the wiper to the lowest position, minimizing power consumption. The three terminals accessing the resistor chain naturally configure the ISL23511 as a voltage divider. A rheostat is easily formed by floating an end terminal or connecting it to the wiper.
VCC (SUPPLY VOLTAGE)
O
Features
• Solid-state volatile potentiometer • Push button controlled • Single or Auto increment/decrement - Fast Mode after 1s button press • Shutdown Mode • 32 wiper tap points - Zero scale wiper position on power-up • Low power CMOS - VCC = 2.7V to 5.5V - Terminal voltage, 0 to VCC - Standby current, 3µA max • RTOTAL value = 10kΩ, 50kΩ • Packages - 8 Ld SOIC and 10 Ld µTQFN (2.1x1.6mm) • Pb-free (RoHS compliant)
Applications
• Volume Control • LED/LCD Brightness Control • Contrast Control • Programming Bias Voltages • Ladder Networks
NC
10
PU PD
1 2 3 4 RW
O
9
NC VCC NC RL
uTFQFN
(Top View)
8 7 6
PU PD CONTROL BLOCK
RH
RH VSS
RW
PU 1 2 3 4
5
8
VCC NC RL RW
RL
PD RH VSS
SOIC
(Top View)
7 6 5
VSS (GROUND)
Ordering Information
PART NUMBER ISL23511WFB8Z* (Note 1) ISL23511UFB8Z* (Note 1) ISL23511WFRU10Z* (Note 2) ISL23511UFRU10Z* (Note 2) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING 23511 WFBZ 23511 UFBZ GA FZ RTOTAL (kΩ) 10 50 10 50 TEMP. RANGE(°C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 10 Ld µTQFN 10 Ld µTQFN M8.15 M8.15 L10.2.1x1.6A L10.2.1x1.6A PKG. DWG. #
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL23511 Pinouts
ISL23511 (8 LD SOIC) TOP VIEW
O
ISL23511 (10 LD µTDFN) TOP VIEW
NC 8 7 6 5 VCC NC RL RW PD RH VSS 10
O
PU PD RH VSS
1 2 3 4
PU
1 2 3 4 RW 5
9 8 7 6
NC VCC NC RL
Pin Descriptions
SOIC PIN 1 2 3 µTQFN PIN 1 2 3 SYMBOL PU PD RH BRIEF DESCRIPTION The PU is a negative-edge triggered input with internal pull-up. Toggling PU will move the wiper close to RH terminal. The PD is a negative-edge triggered input with internal pull-up. Toggling PD will move the wiper close to RL terminal. The RH and RL pins of the ISL23511 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the PU/PD input. Ground The RW pin is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. The RH and RL pins of the ISL23511 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the PU/PD input. No connection Supply Voltage
4 5 6
4 5 6
VSS RW RL
7 8
7, 9, 10 8
NC VCC
Block Diagrams
VCC (SUPPLY VOLTAGE) PU PD 5-BIT UP/DOWN COUNTER 31 30 29 ONE 28 OF THIRTY TWO DECODER 2 RL 1 0 VSS (GROUND) RL RH
PU PD CONTROL BLOCK
RH
RW
TRANSFER GATES
RESISTOR ARRAY
RW
GENERAL
DETAILED
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FN6588.0 December 3, 2007
ISL23511
Absolute Maximum Ratings
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at PU and PD Pin with Respect to GND . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with respect to GND . . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V
Thermal Information
Thermal Resistance (Typical, Note 3, 4) θJA (°C/W) θJC (°C/W) 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . 120 10 Lead µTQFN . . . . . . . . . . . . . . . . . 150 48.3 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. θJC is for the location in the center of the exposed metal pad on the package underside.
Potentiometer Specifications Over recommended operating conditions, unless otherwise specified.
SYMBOL RTOTAL PARAMETER RH to RL Resistance W option U option RH to RL Resistance Tolerance End-to-End Temperature Coefficient W option U option RW VRH, VRL CH/CL/CW (Note 17) ILkgDCP INL (Note 10) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) TCV (Note 11) fCUTOFF Wiper Resistance VRH and VRL Terminal Voltages Noise on wiper terminal Potentiometer Capacitance Leakage on DCP Pins Voltage at pin from GND to VCC -1 Monotonic over all tap positions W option U option Full-scale Error W option U option Ratiometric Temperature Coefficient wiper from 5 hex to 1F hex for W and U option 3dB cut off frequency wiper at the middle scale, W option wiper at the middle scale, U option -0.5 0 0 -3 -1 0.3 0.3 -0.3 -0.3 ±25 500 75 VCC = 3.3V, wiper current IRW = VCC/RTOTAL VRH and VRL to GND from 0Hz to 10MHz 0 -80 10/10/25 0.05 0.4 -20 ±80 ±125 130 400 VCC TEST CONDITIONS MIN (Note 18) TYP (Note 5) 10 50 +20 MAX (Note 18) UNIT kΩ kΩ % ppm/°C (Note 16) ppm/°C (Note 16) Ω V dBV pF µA
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW unloaded) Integral Non-linearity Differential Non-linearity Zero-scale Error 1 0.5 3 1 0 0 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) ppm/°C kHz kHz
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 15) Integral Non-linearity DCP register set between 1 hex and 1F hex; monotonic over all tap positions; W option DCP register set between 1 hex and 1F hex; monotonic over all tap positions; U option -1.5 -1 1.5 1 MI (Note 12) MI (Note 12)
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FN6588.0 December 3, 2007
ISL23511
Potentiometer Specifications Over recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL RDNL (Note 14) Roffset (Note 13) PARAMETER Differential Non-linearity Offset TEST CONDITIONS W and U option W option U option MIN (Note 18) -0.5 0 0 1 0.5 TYP (Note 5) MAX (Note 18) 0.5 3 1 UNIT MI (Note 12) MI (Note 12) MI (Note 12)
DC Electrical Specifications
SYMBOL ICC ISB ILkg VIH VIL CIN (Note 17) Rpull_up (Note 17)
Over recommended operating conditions unless otherwise specified. TEST CONDITIONS VCC = 5.5V, perform wiper move operation 0.6 VIN = VSS to VCC -2 VCC x 0.7 VCC x 0.1 VCC = 3.3V, TA = +25°C, f = 1MHz 10 1 MIN (Note 18) TYP (Note 5) MAX (Note 18) 150 3 +2 UNIT µA µA µA V V pF MΩ
PARAMETER VCC Active Current Standby Current PU, PD Input Leakage Current PU, PD Input HIGH Voltage PU, PD input LOW Voltage PU, PD Input Capacitance Pull-up Resistor for PU and PD
AC Electrical Specifications
SYMBOL tGAP (Note 17) tDB tS SLOW tS FAST tstdn (Note 17) tR VCC NOTES:
Over recommended operating conditions unless otherwise specified. MIN (Note 18) TYP (Note 5) 1 15 100 25 250 50 2 0.2 50 30 375 75 MAX (Note 18) UNIT ms ms ms ms s V/ms
PARAMETER Time Between Two Separate Push Button Events Debounce Time Wiper Change on a Slow Mode Wiper Change on a Fast Mode Time to Enter Shutdown Mode (keep PU and PD LOW) VCC Power-up Rate
5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)31 – V(RW)0]/31. V(RW)31 and V(RW)0 are voltage on RW pin for the DCP register set to 1F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)31 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB -1, for i = 1 to 31; i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 31 Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 11. T C = --------------------------------------------------------------------------------------------- × --------------------for i = 5 to 31 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW31 – RW0|/31. MI is a minimum increment. RW31 and RW0 are the measured resistances for the DCP register set to 1F hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW31/MI, when measuring between RW and RH. 14. RDNL = (RWi – RWi-1)/MI, for i = 1 to 31. 15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 31. 16.
6 for i = 5 to 31, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is the [ Max ( Ri ) – Min ( Ri ) ] 10 T C R = --------------------------------------------------------------- × -------------------- minimum value of the resistance over the temperature range. [ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 +165°C 17. Limits should be considered typical and are not production tested.
18. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
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FN6588.0 December 3, 2007
ISL23511 Slow Mode Timing
tDB PU tGAP
MI* VW
* MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage.
Fast Mode Timing
tDB PU
tS FAST
tS SLOW
VW 1s
MI*
* MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage.
Shutdown Mode Timing
tDB PU 2s SHUTDOWN MODE
PD
VW
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FN6588.0 December 3, 2007
ISL23511 Typical Performance Curves
160 140 WIPER RESISTANCE (Ω) 120 ICC (µA) 100 80 60 40 20 0 0 5 10 15 20 25 30 -40ºC 0.5 0 -40 +25ºC 2.0 1.5 1.0 VCC = 5.5V VCC = 2.7V VCC = 5.5V +125ºC 3.0 2.5
-15
10
35
60
85
110
TAP POSITION (DECIMAL)
TEMPERATURE (°C)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W)
FIGURE 2. STANDBY ICC vs TEMPERATURE
0.010 VCC = 2.7V
0.03 0.02 VCC = 2.7V
0.005 0.01 DNL (LSB) INL (LSB) 0.000 0.00 -0.01 -0.02 VCC = 5.5V -0.010 0 5 10 15 20 25 30 -0.03 0 5 10 15 20 25 30 VCC = 5.5V
-0.005
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W)
0.006 FULL SCALE ERROR (LSB) ZERO SCALE ERROR (LSB) 0.005 0.004 VCC = 5.5V 0.003 0.002 0.001 0 -40 VCC = 2.7V
0 -0.1 -0.2 -0.3 -0.4 VCC = 2.7V -0.5 -40 -15 10 35 60 85 110 VCC = 5.5V
-15
10
35
60
85
110
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. ZS ERROR vs TEMPERATURE
FIGURE 6. FS ERROR vs TEMPERATURE
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FN6588.0 December 3, 2007
ISL23511 Typical Performance Curves
0.2 VCC = 2.7V 0.1 RDNL (LSB) RINL (LSB) 0.6
(Continued)
0.8 VCC = 2.7V
0.0
0.4 VCC = 5.5V 0.2
-0.1
VCC = 5.5V
-0.2
0
5
10
15
20
25
30
0.0 0 5 10 15 20 25 30 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W)
1.20 VCC = 5.5V RTOTAL CHANGE (%) 0.60 TCv (ppm/°C) 10k
40 35 30 25 20 15 10 50k 5 0 -15 10 35 60 85 110 TEMPERATURE (°C) 5 10 15 20 VCC = 2.7V
10k
VCC = 5.5V
0.00
50k
-0.60
VCC = 2.7V
-1.20 -40
25
30
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
300 250 50k TCr (ppm/°C) 200 150 100 50 0 VCC = 2.7V VCC = 5.5V 10k
5
10
15
20
25
30
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (500kHz)
ISL23511 Power-Up and Power-Down Requirements
There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VRH and VRL, i.e., VCC ≥ VRH,VRL. The VCC ramp rate specification is always in effect. input, the wiper will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wiper position if PU or PD remain LOW for less than 15ms, typical. Each of the buttons can be pushed either once for a single increment/decrement or continuously for a multiple increments/decrements. The number of increments/decrements of the wiper position depend on how long the button is being pushed. When making a continuous push, after the first second, the increment/decrement speed increases. For the first second, the device will be in the slow scan mode. Then, if the button is held for longer than 1s, the device will go into the fast scan mode. As soon as the button is released, the ISL23511 will return to a stand-by condition. If both PU and PD buttons are pulled low more than 15ms from each other, all commands are ignored upon release of ALL buttons. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme.
Pin Descriptions
RH and RL
The RH and RL pins of the ISL23511 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction.
RW
The RW pin is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. The default wiper position at power-up is at 0 tap.
PU
The debounced PU input is used to increment the wiper position. An on-chip pull-up holds the PU input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent higher tap position.
Shutdown Mode
The ISL23511 enters into Shutdown Mode if both PU and PD inputs are kept LOW for 2 seconds. In this mode, the resistors array is totally disconnected from its RH pin and the wiper is moved to the position closest to the RL pin, as shown in Figure 13.
RH
PD
The debounced PD input is used to decrement the wiper position. An on-chip pull-up holds the PD input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent lower tap position.
RW
Device Operation
There are three sections of the ISL23511: the input control, the counter and decode section and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch, connecting a point on the resistor array to the wiper output. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The ISL23511 is designed to interface directly to two push button switches for effectively moving the wiper up or down. The PU and PD inputs increment or decrement a 5-bit counter respectively. The output of this counter is decoded to select one of the thirty-two wiper positions along the resistive array. The wiper increment input, PU and the wiper decrement input, PD are both connected to an internal pull-up so that they normally remain HIGH. When pulled LOW by an external push button switch or a logic LOW level
RL
FIGURE 13. DCP CONNECTION IN SHUTDOWN MODE
Note that PU and PD inputs must be brought LOW within tDB time window of 15ms (see “Shutdown Mode Timing” on page 5.) otherwise all commands will be ignored until both inputs are released. Holding either PU or PD input LOW for more than 15ms will exit shutdown mode and return wiper to prior shutdown position. If PU or PD will be held LOW for more than 250ms, the ISL23511 will start auto-increment or auto-decrement of wiper position.
RTOTAL with VCC Removed
The end to end resistance of the array will fluctuate once VCC is removed.
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FN6588.0 December 3, 2007
ISL23511
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FN6588.0 December 3, 2007
ISL23511 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 2.05 1.55 0.20 2.10 1.60 0.50 BSC 0.20 0.35 0.40 10 4 1 0 12 0.45 0.25 2.15 1.65 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
2.50 1.75
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW (DATUM A) PIN #1 ID 1 2 NX L N (DATUM B) N-1 e 3 (ND-1) X e BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e (A1) NX b 5 A
C
D E e k L N
4xk
Nd Ne θ
0.10 M C A B 0.05 M C
L
TERMINAL TIP
FOR ODD TERMINAL/SIDE
b
0.05 MIN
L 2.00 0.80
0.275
0.10 MIN DETAIL “A” PIN 1 ID 0.50
0.25
LAND PATTERN 10
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FN6588.0 December 3, 2007
ISL23511 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
α
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0° 8° 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0° 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
α
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6588.0 December 3, 2007