ISL24201IRTZ-EVALZ

Programmable VCOM Calibrator with EEPROM ISL24201 The ISL24201 provides an 8-bit programmable current sink that is used in conjunction with an external voltage divider and buffer amplifier to generate a voltage source that is positioned between the analog supply voltage and ground. The current sink’s resolution is controlled by an external resistor, RSET, and the span of the VCOM voltage is controlled by the voltage divider resistor ratio and the source impedance of R1 and R2. This device has an 8-bit data register and 8-bit EEPROM for storing a volatile and a permanent value for its output. The ISL24201 has an I2C bus interface that is used to read and write to its registers and EEPROM. At power-up the EEPROM value is transferred to the data register and output. The ISL24201 is available in an 8 Ld 3mm x 3mm TDFN package. This package has a maximum height of 0.8mm for very low profile designs. The ambient operating temperature range is -40°C to +85°C. Features • 8-bit, 256-Step, Adjustable Sink Current Output • 4.5V to 18V Analog Supply Voltage Operating Range • 2.25V to 3.6V Logic Supply Voltage Operating Range • 400kHz, I2C Interface • On-Chip 8-Bit EEPROM • Output Guaranteed Monotonic Over-Temperature • Pb-free (RoHS-compliant) Applications • LCD Panel VCOM Generator • Electrophoretic Display VCOM Generator • Resistive Sensor Driver • Low Power Current Loop Related Literature • See AN1621 for ISL24201 Evaluation Board Application Note “ISL24201IRTZ-EVALZ Evaluation Board User Guide” Typical Application 3.3V VDD AVDD LCD PANEL 5 2 R1 6 MICROCONTROLLER I2C PORT 7 SCL 3 WP RSET 4 EL5411T SDA ISL24201 SET OUT 1 VCOM 8 R2 I/O PIN FIGURE 1. APPLICATION SHOWING ISL24201 WITH A BUFFER AMPLIFIER December 9, 2010 FN7586.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL24201 Block Diagram VDD 5 AVDD 2 SDA SCL 6 7 I2C INTERFACE DAC REGISTERS ANALOG DCP AND CURRENT SINK Q1 1 OUT WP 3 8-BIT EEPROM CURRENT SINK ISL24201 4 GND A1 8 SET FIGURE 2. BLOCK DIAGRAM OF THE ISL24201 Pin Configuration ISL24201 (8 LD TDFN) TOP VIEW OUT 1 AVDD 2 WP 3 GND 4 PAD 6 SDA 5 VDD 8 SET 7 SCL Pin Descriptions PIN NAME OUT PIN NUMBER 1 FUNCTION Adjustable Sink Current Output Pin. The current sunk into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 256. See the “SET” pin function description below (pin 8) for the maximum adjustable sink current setting. High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor. EEPROM Write Protect. Active Low. 0 = Programming disabled; 1 = Programming allowed. This pin has an internal pull-down current sink Ground connection. System power supply input. Bypass to GND with 0.1µF capacitor. I2C Serial Data Input and Output I2C Clock Input Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Thermal pad should be connected to system ground plane to optimize thermal performance. AVDD WP 2 3 (THERMAL PAD CONNECTS TO GND) GND VDD SDA SCL SET 4 5 6 7 8 PAD - 2 FN7586.1 December 9, 2010 ISL24201 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL24201IRTZ ISL24201IRTZ-EVALZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page ISL24201. For more information on MSL please see techbrief TB363. PART MARKING 201Z Evaluation Board INTERFACE I2C TEMP RANGE (°C) -40 to +85 8 Ld 3x3 TDFN PACKAGE (Pb-Free) PKG. DWG. # L8.3x3A 3 FN7586.1 December 9, 2010 ISL24201 Absolute Maximum Ratings Supply Voltage AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Input Voltage with respect to Ground SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V Output Voltage with respect to Ground OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD Continuous Output Current OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . .1.5kV Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 53 11 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Range AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS DC CHARACTERISTICS VDD AVDD AVDD IDD IAVDD SETZSE SETFSE VOUT SET VD IOUT INL VDD Supply Range - Operating AVDD Supply Range Supporting EEPROM Programming AVDD Supply Range for Wide-Supply Operation (not supporting EEPROM Programming) VDD Supply Current AVDD Supply Current SET Zero-Scale Error SET Full-Scale Error OUT Voltage Range SET Voltage Drift Maximum OUT Sink Current Integral Non-Linearity IOUT < 0.5mA VSET + 0.4 7 4 ±2 ±1 WP = SCL = SDA = VDD WP = SCL = SDA = VDD 2.25 10.8 4.5 37 24 3.6 19 19 65 38 ±3 ±8 AVDD V V V µA µA OUT CHARACTERISTICS LSB LSB V μV/°C mA LSB LSB DNL Differential Non-Linearity 2C INPUTS AND OUTPUT I I2CVIH I2CVIL I2CH IL VOLS VIH VIL VWPH ILWPN SDA, SCL Logic 1 Input Voltage SDA, SCL Logic 0 Input Voltage SDA, SCL Hysteresis Input Leakage Current of SDA, SCL SDA Output Logic Low WP Input Logic High WP Input Logic Low WP Input Hysteresis WP Input Leakage Current -0.20 260 -0.5 I = -3mA 0.7VDD 260 1.44 V 0.55 ±1 0.4 V mV µA V V 0.3VDD -1 V mV µA 4 FN7586.1 December 9, 2010 ISL24201 Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL 2C TIMING I fCLK tSCH tSCL tDSP tSDS tSDH tBUF tSTS tSTH tSPS CSDA CS tW I2C Clock Frequency I2C Clock High Time I2C Clock Low Time I2C Spike Rejection Filter Pulse Width I2C Data Set Up Time I2C Data Hold Time I2C Time Between Stop and Start I2C Repeated Start Condition Set-up I2C Repeated Start Condition Hold I2C Stop Condition Set-up SDA Pin Capacitance SCL Pin Capacitance EEPROM Write Cycle Time 0.6 1.3 0 250 250 200 0.6 0.6 0.6 10 10 100 50 PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 400 kHz µs µs ns ns ns µs µs µs µs pF pF ms NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Application Information The ISL24201 provides the ability to adjust the VCOM voltage during production test and alignment, under digital control, to minimize the flicker of an LCD panel. A digitally controlled potentiometer (DCP), with 256 steps of resolution, adjusts the sink current of the OUT pin. Figure 3 shows the VCOM adjustment using a mechanical potentiometer circuit and the equivalent circuit replacement with the ISL24201. The output is connected to an external voltage divider, as shown in Figure 3, so that the ISL24201 will have the ability to reduce the voltage on the output by increasing the OUT pin sink current. The amount of current sunk is controlled by the I2C serial interface. AVDD RA R1 = RA R2 = RB+RC RSET = RARB + RARC 20RB RC RB VCOM VDD ISL24201 or ISL24202 SET RSET AVDD AVDD R1 OUT IOUT VCOM R2 FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT 5 FN7586.1 December 9, 2010 ISL24201 DCP (Digitally Controlled Potentiometer) Figure 4 shows the relationship between the register value and the resistor string of the DCP. Note that the register value of zero actually selects the first step of the resistor string. The output voltage of the DCP is given by Equation 1: RegisterValue + 1 A VDD V DCP = ⎛ -------------------------------------------------- ⎞ ⎛ ------------- ⎞ ⎝ ⎠ ⎝ 20 ⎠ 256 (EQ. 1) The maximum value of IOUT can be calculated by substituting the maximum register value of 255 into Equation 2, resulting in Equation 3: A VDD I OUT ( MAX ) = ------------------20R SET (EQ. 3) Equation 2 can also be used to calculate the unit sink current step size by removing the Register Value term from it as shown in Equation 4. A VDD I STEP = --------------------------------------------( 256 ) ( 20 ) ( R SET ) (EQ. 4) AVDD 19R 255 254 253 252 R 251 2 1 0 REGISTER VALUE AVDD 20 The voltage difference between the OUT pin and SET pin, which are also the drain and source of the output transistor, should be greater than the minimum saturation voltage for the IOUT(MAX) being used. This will keep the output transistor in its saturation region to maintain linear operation over the full range of register values. VDCP Figure 6 shows IDS vs VDS for transistor Q1. The line labeled "Minimum Saturation Voltage" is the minimum voltage that should be maintained across the drain and source of Q1. To find the minimum saturation voltage for a specific condition, locate the voltage at the intersection of the IOUT(MAX) value from Equation 3 and the line labeled "Minimum Saturation Voltage". 4.5 4.0 3.5 MINIMUM SATURATION VOLTAGE SATURATION REGION IDS (mA) FIGURE 4. SIMPLIFIED SCHEMATIC OF DIGITAL CONTROL POTENTIOMETER (DCP) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 5 6 VDS (V) 7 8 9 10 Output Current Sink Figure 5 shows the schematic of the OUT pin current sink. The circuit made up of amplifier A1, transistor Q1, and resistor RSET forms a voltage controlled current source. AVDD AVDD R1 OUT VDCP Q1 A1 VSAT SET VSET = (IOUT)*(RSET) = VDCP R2 VOUT FIGURE 6. IDS vs VDS FOR THE ISL24201 OUTPUT TRANSISTOR IOUT RSET FIGURE 5. CURRENT SINK CIRCUIT The external RSET resistor sets the full-scale sink current that determines the lowest output voltage of the external voltage divider R1 and R2. IOUT is calculated as shown by Equation 2: V DCP RegisterValue + 1 A VDD 1 I OUT = ------------- = ⎛ -------------------------------------------------- ⎞ ⎛ ------------- ⎞ ⎛ ------------ ⎞ ⎝ ⎠ ⎝ 20 ⎠ ⎝ R ⎠ 256 R SET SET (EQ. 2) 6 FN7586.1 December 9, 2010 ISL24201 The maximum voltage on the SET pin is AVDD/20 and is added to the minimum voltage difference between the VOUT and SET pins to calculate the minimum VOUT voltage, as shown in Equation 5. OUT PIN MAXIMUM CURRENT (mA) A VDD V OUT ( MIN ) ≥ ------------- + MinimumSaturationVoltage 20 (EQ. 5) 0.6 10 kΩ R TH Output Voltage The output voltage, VOUT, of the OUT pin can be calculated from Equation 6: ⎛ R2 ⎞ ⎛ RegisterValue + 1 ⎛ R 1 ⎞ ⎞ V OUT = A VDD ⎜ ------------------- ⎟ ⎜ 1 – -------------------------------------------------- ⎜ ------------------- ⎟ ⎟ R1+ R2 ⎠ ⎝ 256 ⎝ 20R SET⎠ ⎠ ⎝ (EQ. 6) 0.4 0.3 kΩ 25 While Equation 6 can be used to calculate the output voltage, it does not help select the values of R1, R2 and RSET to obtain a specific range of VCOM voltages. 0.2 R TH Output Voltage Span Calculation The span of the output voltage is typically centered around the nominal VCOM voltage value, which is typically near half of the AVDD voltage. The high VCOM voltage occurs with the register value of zero, while the low VCOM voltage occurs with the register value of 255. Figure 7 shows the definition of several terms used later in the text. A VDD 0.1 R TH 00k Ω R TH = 1 0 0 1 2 3 4 = 0.5 = kΩ = 50 5 6 VCOM SPAN (V) FIGURE 8. GRAPH of VCOM SPAN vs MAXIMUM OUTCURRENT AND RTH To make a final selection of the resistor values for R1 and R2, The supply voltage AVDD and the value of RSET are specified. The calculations for R1 and R2 are shown in Equations 9 and 10: H IG H V CO M V O LTAG E 40R SET ( SPAN ) R 1 = ----------------------------------------A VDD + SPAN SPAN (EQ. 9) N O M IN AL V CO M V O LTAG E LO W V CO M V O LTA G E 40R SET ( SPAN ) R 2 = ----------------------------------------A VDD – SPAN (EQ. 10) The R1 and R2 calculations are based on the span of the VCOM voltage being centered at half the AVDD voltage. GND FIGURE 7. VOLTAGE LEVELS FOR VCOM There are three variables that control the VCOM calibrator’s operating point; the span of the VCOM voltage, the maximum current sink and the source impedance of the resistive divider. Figure 8 shows a range of operating points for these three variables and a quick way to estimate a specific operating point. The X-axis is the span of the VCOM voltage (High VCOM Voltage - Low VCOM Voltage), and the Y-axis is the maximum sink current set by RSET. The individual plots of each RTH show the VCOM span plotted against the maximum OUT sink current given that value of source impedance of the voltage divider. RTH is the Thevenin equivalent resistance of the voltage divider R1 and R2, which is the resistance of the parallel combination of R1 and R2, as shown in Equation 7. R1 R2 R TH = ------------------R1 + R2 (EQ. 7) As an example, AVDD = 15V, the maximum value for ISET is selected to be 100µA and the required span is 2V. Using Figure 8 as a guide, the VCOM maximum is equal to 8.5V and the VCOM minimum is equal to 6.5V. Rearranging equation and calculation the value of RSET: A VDD 15 R SET = ------------------------------------ = ------------------------------------- = 7500 Ω 20I OUT ( MAX ) 20 ( 0.000100 ) (EQ. 11) Calculating the value of R1 is shown in Equation 12. 40 ( 7500 ) ( 2 ) R 1 = ---------------------------------- = 39.29k Ω 15 + 2 (EQ. 12) Calculating the value of R2 is shown in Equation 13. 40 ( 7500 ) ( 2 ) R 2 = ---------------------------------- = 46.15k Ω 15 – 2 (EQ. 13) The span of the VCOM voltage is shown by Equation 8. V COM SPAN = I SET ( R TH ) (EQ. 8) 7 FN7586.1 December 9, 2010 ISL24201 Table 1 shows the calculated results of the VCOM voltage with these values. TABLE 1. EXAMPLE VOUT vs REGISTER VALUE REGISTER VALUE 0 20 40 60 80 100 120 127 140 160 180 200 220 240 255 VOUT (V) 8.49 8.34 8.18 8.02 7.87 7.71 7.55 7.50 7.40 7.24 7.09 6.93 6.77 6.62 6.50 0.050 0.250 0.300 OUT and SET Pin Current vs. OUT Pin Voltage Register = 255 OUT Pin Current 0.200 Current (mA) SET Pin Current 0.150 0.100 0.000 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 OUT Pin Voltage (V) FIGURE 9. OUT PIN LEAKAGE CURRENT Power Supply Sequence The recommended power supply sequencing is shown in Figure 10. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for tVS is 0µs. When removing power, the sequence of VDD and AVDD is not important. VDD AVDD tVS Figure 6 is used to find the minimum saturation voltage for an IOUT maximum of 100µA, which is about 0.3V. The minimum VOUT is 6.5V, which also meets the minimum VOUT - VSET requirements specified in Equation 14: 15V V OUT MIN = 6.5V > --------- + 0.3V = 1.05V 20 (EQ. 14) OUT Pin Leakage Current When the voltage on the OUT pin is greater than 10V, there is a leakage current flowing into the pin in addition to the ISET current. Figure 9 shows the ISET current and the OUT pin current for OUT pin voltage up to 19V. In applications where the voltage on the OUT pin will be greater than 10V, the actual output voltage will be lower than the voltage calculated by Equation 6. The graph in Figure 9 was measured with RSET = 4.99kΩ. FIGURE 10. POWER SUPPLY SEQUENCE Do not remove VDD or AVDD within 100ms of the start of the EEPROM programming cycle. Removing power before the EEPROM programming cycle is completed may result in corrupted data in the EEPROM. Operating and Programming Supply Voltage and Current To program the EEPROM, AVDD must be ≥10.8V. If programming is not required, the ISL24201 will operate over an AVDD range of 4.5V to 19V. During EEPROM programming, IDD and IAVDD will temporarily be higher than their quiescent currents. Figure 11 shows a typical IDD and IAVDD current profile during EEPROM programming. The current pulses are Erase and Write cycles. The EEPROM programming algorithm is shown in Figure 12. The algorithm allows up to 4 erase cycles and 4 programming cycles, however typical parts only require 1 cycle of each, sometimes 2 when AVDD is near the minimum 10.8V limit. 8 FN7586.1 December 9, 2010 ISL24201 VDD Programming Current 2.7mA ISL24201 Programming The ISL24201 accepts I2C bus address and data when the WP pin is at or above VIH (>0.7VDD). The ISL24201 ignores the I2C bus when the WP pin is at or below VIL (10.8V. After the EEPROM programming cycle is started, the WP pin can be returned to logic low while the while it completes, which takes a maximum of 100ms. The ISL24201 uses a 6 bit I2C address, which is “100111xx”. The complete read and write protocol is shown in Figures 13 and 14. A re E E P R O M C e lls P ro g ra m m e d ? I2C Bus Signals No Yes EEPROM P ro g ra m m in g C o m p le te The ISL24201 uses fixed voltages for its I2C thresholds, rather than the percentage of VDD described in the I2C specification (see Table 3). This should not cause a problem in most systems, but the I2C logic levels in a specific design should be checked to ensure they are compatible with the ISL24201. TABLE 3. ISL24201 I2C BUS LOGIC LEVELS SYMBOL I2CVIL I2CV IH FIGURE 12. EEPROM PROGRAMMING FLOWCHART ISL24201 0.55V 1.44V I2C STANDARD 0.3*VDD 0.7*VDD 9 FN7586.1 December 9, 2010 ISL24201 I2C Read and Write Format IS L 2 4 2 0 1 I 2 C W rite B y te 1 S tart MSB 1 0 0 1 1 1 D0 6 b it A d d re ss D a ta LSB R/W LSB 0 A ACK M SB D7 D6 D5 D4 D3 D2 D1 B y te 2 D a ta P ro g ram LSB P A ACK S to p R / W = 0 = W rite R/W = 1 = Read W hen R/W = 0 P = 0 = E E P R O M P ro g ra m m in g P = 1 = R e g iste r W rite FIGURE 13. I2C WRITE FORMAT ISL24201 I2C Read Byte 1 Start MSB 1 0 0 1 1 1 X 6 bit Address X R/W LSB 1 A ACK Start MSB D7 D6 D5 D4 D3 D2 D1 Byte 2 Data LSB D0 A ACK Stop R/W = 0 = Write R/W = 1 = Read FIGURE 14. I2C READ FORMAT 10 FN7586.1 December 9, 2010 ISL24201 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE 12/9/10 12/1/10 REVISION FN7586.1 FN7586.0 CHANGE On page 5, corrected MIN spec for “tBUF” from 125µs to 200µs. Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL24201 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/sear For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7586.1 December 9, 2010 ISL24201 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 A B ( 1.95) ( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 ) SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 ±0.10 1 SIDE VIEW 0.75 ±0.05 0.10 C C 0.08 C 8 8X 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 8X 0.30 ±0.05 0.10 M C A B 4 C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. 12 FN7586.1 December 9, 2010