ISL28110FBBZ

Precision Low Noise JFET Operational Amplifiers ISL28110, ISL28210 The ISL28110, ISL28210, are single and dual JFET amplifiers featuring low noise, high slew rate, low input bias current and offset voltage, making them the ideal choice for high impedance applications where precision and low noise are important. The combination of precision, low noise, and high speed combined with a small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision medical and analytical instrumentation, sensor conditioning, precision power supply controls, industrial controls and photodiode amplifiers. The ISL28110 single amplifier is available in the 8 Ld SOIC, TDFN, and MSOP packages. The ISL28210 dual amplifier is available in the 8 Ld SOIC and TDFN packages. All devices are offered in standard pin configurations and operate over the extended temperature range from -40°C to +125°C. ISL28110, ISL28210 Features • Wide Supply Range. . . . . . . . . . . . . . . . . 9V to 40V • Low Voltage Noise . . . . . . . . . . . . . . . . . . 6nV/√Hz • Input Bias Current . . . . . . . . . . . . . . . . . . . . . 2pA • High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 23V/µs • High Bandwidth . . . . . . . . . . . . . . . . . . . .12.5MHz • Low Input Offset . . . . . . . . . . . . . . . . .300µV, Max • Offset Drift . . . . . . . . . . . . . . . . Grade C 10µV/°C • Low Current Consumption . . . . . . . . . . . . . 2.55mA • Operating Temperature Range . . . -40°C to +125°C • Small Package Offerings in Single, and Dual • Pb-Free (RoHS compliant) Applications*(see page 16) • Precision Instruments • Photodiode Amplifiers • High Impedance Buffers • Medical Instrumentation • Active Filter Blocks • Industrial Controls Typical Application RF CF Input Bias Current vs Common Mode Input Voltage NORMALIZED INPUT BIAS CURRENT (pA) 10 8 6 4 2 0 -2 -4 -6 -8 -10 -15 -10 -5 0 VCM (V) 5 10 15 VS = ±15V V+ PHOTO DIODE RSH CT + OUTPUT V- BASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER September 13, 2010 FN6639.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28110, ISL28110, ISL28210 Pin Configurations ISL28110 (8 LD TDFN) TOP VIEW NC 1 -IN A 2 +IN A 3 V- 4 PAD -+ 8 NC 7 V+ 6 VOUT A 5 NC ISL28110 (8 LD, SOIC, MSOP) TOP VIEW NC -IN A +IN A V1 2 3 4 -+ 8 NC 7 V+ 6 VOUT A 5 NC ISL28210 (8 LD TDFN) TOP VIEW VOUT A -IN A +IN A V1 2 3 4 PAD -+ +8 V+ 7 VOUT B 6 -IN B 5 +IN B VOUT A -IN A +IN A V1 2 3 4 ISL28210 (8 LD SOIC) TOP VIEW 8 V+ -+ +7 VOUT B 6 -IN B 5 +IN B Pin Descriptions ISL28110 (8 Ld TDFN) 3 2 6 4 ISL28110 (8 Ld SOIC, ISL28210 8 Ld MSOP) (8 Ld TDFN) 3 2 6 4 3 2 1 4 5 6 7 7 1, 5, 8 PAD 7 1, 5, 8 PAD PAD 8 ISL28210 (8 Ld SOIC) 3 2 1 4 5 6 7 8 PIN NAME +IN A -IN A VOUT A V+IN B -IN B VOUT B V+ EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 2 Circuit 3 Circuit 1 Circuit 1 Circuit 2 Circuit 3 DESCRIPTION Amplifier A non-inverting input Amplifier A inverting input Amplifier A output Negative power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output Positive power supply No connect Thermal Pad is electrically isolated from active circuitry. Pad can float, connect to Ground or to a potential source that is free from signals or noise sources. V+ CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 3 V+ ININ+ V+ OUT VCIRCUIT 2 V- CIRCUIT 1 2 FN6639.0 September 13, 2010 ISL28110, ISL28110, ISL28210 Ordering Information PART NUMBER (Notes 1, 2, 3) Coming Soon ISL28110FBZ ISL28210FBZ Coming Soon ISL28110FRTZ Coming Soon ISL28210FRTZ Coming Soon ISL28110FRTBZ Coming Soon ISL28210FRTBZ Coming Soon ISL28110FBBZ Coming Soon ISL28210FBBZ Coming Soon ISL28110FUBZ Coming Soon ISL28110FUZ NOTES: 1. Add “-T7”, “-T13” or “-T7A” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on MSL please see techbrief TB363. PART MARKING 28110 FBZ -C 28210 FBZ -C -C 8110 -C 8210 8110 8210 28110 FBZ -C 28210 FBZ 8110Z 8110Z TCVOS (µV/°C) 10 (C Grade) 10 (C Grade) 10 (C Grade) 10 (C Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 4 (B Grade) 10 (C Grade) PACKAGE (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld TDFN 8 Ld SOIC 8 Ld SOIC 8 Ld MSOP 8 Ld MSOP PKG. DWG. # M8.15E M8.15E L8.3x3A L8.3x3A L8.3x3A L8.3x3A M8.15E M8.15E M8.118 M8.118 3 FN6639.0 September 13, 2010 ISL28110, ISL28110, ISL28210 Absolute Voltage Ratings Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Turn On Voltage Slew Rate . . . . . . . . 1V/µs Maximum Differential Input Voltage . . . . . . . . . . . . . . . 33V Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input current for input voltage >V+ or 33V reverse breakdown voltage which enables the device to function reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. No special input signal restrictions are needed for power supply operation up to ±15V, and input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. For power supply operation greater than ±16V (>32V), the internal ESD clamp diodes alone cannot clamp the maximum input differential signal to the power supply rails without the risk of exceeding the 33V breakdown of the JFET gate. Under these conditions, differential input voltage limiting is necessary to prevent damage to the JFET input stage. In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 39 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. V+ RINRIN + VS = ±15V INPUT OFFSET VOLTAGE (VOS) T = +25°C 500 400 200 100 0 -100 -200 NORMALIZED VOS (uV) 300 INPUT BIAS (IB) -300 -400 -500 15 -10 -5 0 VCM (V) 5 10 FIGURE 40. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs COMMON MODE INPUT VOLTAGE Output Drive Capability The complementary bipolar emitter follower output stage features low output impedance (Figure 40) and is capable of substantial current drive over the full temperature range (Figures 25, 26) while driving the output voltage close to the supply rails. The output current is internally limited to approximately ±50mA at +25°C. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. VINVIN+ RL Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28110 and ISL28210 are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit. Beyond these limits, the device is still immune to reversal to 1V beyond the FN6639.0 September 13, 2010 V- FIGURE 39. INPUT ESD DIODE CURRENT LIMITING 14 ISL28110, ISL28210 rails but damage to the internal ESD protection diodes can result unless these input currents are limited. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) Maximizing Dynamic Signal Range The amplifiers maximum undistorted output swing is a figure of merit for precision, low distortion applications. Audio amplifiers are a good example of amplifiers that require low noise and low signal distortion over a wide output dynamic range. When these applications operate from batteries, raising the amplifier supply voltage to overcome poor output voltage swing has the penalty of increased power consumption and shorter battery life. Amplifiers whose input and output stages can swing closest to the power supply rails while providing low noise and undistorted performance, will provide maximum useful dynamic signal range and longer battery life. Rail-to-rail input and output (RRIO) amplifiers have the highest dynamic signal range but their added complexity degrades input noise and amplifier distortion. Many contain two input pairs, one pair operating to each supply rail. The trade-offs for these are increased input noise and distortion caused by non-linear input bias current and capacitance when amplifying high impedance sources. Their rail-to-rail output stages swing to within a few millivolts of the rail, but output impedances are high so that their output swing decreases and distortion increases rapidly with increasing load current. At heavy load currents the maximum output voltage swing of RRO op amps can be lower than a good emitter follower output stage. The ISL28110 and ISL28210 low noise input stage and high performance output stage are optimized for low THD+N into moderate loads over the full -40°C to +125°C temperature range. Figures 17 and 18 show the 1kHz THD+N unity gain performance vs output voltage swing at load resistances of 2kΩ and 600Ω. Figure 41 shows the unity-gain THD+N performance driving 600Ω from ±5V supplies. 1 VS = ±5V RL = 600Ω 0.1 THD+N (%) AV = 1 +125°C 0.01 +85°C +25°C where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × --------------------------RL (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance 0.001 0°C -40°C 0.0001 0 1 2 3 4 5 6 VP-P (V) 7 8 9 10 FIGURE 41. UNITY-GAIN THD+N vs OUTPUT VOLTAGE vs TEMPERATURE AT VS = ±5V FOR 600Ω LOAD 15 FN6639.0 September 13, 2010 ISL28110, ISL28210 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 9/13/10 REVISION FN6639.0 Initial Release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28110, ISL28210 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6639.0 September 13, 2010 ISL28110, ISL28210 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 A B ( 1.95) ( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 ) SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 ±0.10 1 SIDE VIEW 0.75 ±0.05 0.10 C C 0.08 C 8 8X 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 8X 0.30 ±0.05 0.10 M C A B 4 C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. 17 FN6639.0 September 13, 2010 ISL28110, ISL28210 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0.05 A 8 D 1.10 MAX 5 DETAIL "X" SIDE VIEW 2 3.0±0.05 5 4.9±0.15 0.09 - 0.20 PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW 0.95 REF GAUGE PLANE 0.25 0.55 ± 0.15 H 0.85±010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 ± 0.05 0.10 C 3°±3° (5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 18 FN6639.0 September 13, 2010 ISL28110, ISL28210 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 1.27 0.43 ± 0.076 0.25 M C A B 4° ± 4° TOP VIEW SIDE VIEW “B” 1.75 MAX 1.45 ± 0.1 0.25 0.175 ± 0.075 GAUGE PLANE C SEATING PLANE 0.10 C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012. 2. (5.40) 3. 4. TYPICAL RECOMMENDED LAND PATTERN 19 FN6639.0 September 13, 2010