ISL28118MUZ-T7A

DATASHEET ISL28118M FN7858 Rev 1.00 March 7, 2014 40V Extended Temperature Range, Precision Single-Supply, Rail-to-Rail Output, Operational Amplifier The ISL28118M is a single, low-power precision amplifier optimized for single-supply applications over the extended temperature range of -55°C to +125°C. This device features a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which makes it ideal for single-supply applications where input operation at ground is important. Features The ISL28118M features low power, low offset voltage, and low temperature drift, making it the ideal choice for applications requiring both high DC accuracy and AC performance. The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Low noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/Hz • Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300kΩ. The output stage is internally current limited. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 45 and 46). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28118M is immune to output phase reversal for input voltage to 0.5V beyond the rail (VABS MAX) limit (Figure 38). Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX +  JA xPD MAXTOTAL (EQ. 1) where • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package Page 15 of 23 ISL28118M PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------R (EQ. 2) L where: • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of one amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance ISL28118M SPICE Model Figure 50 shows the SPICE model schematic and Figure 51 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, CMRR, and gain and phase. The DC parameters are IOS, total supply current, and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 4. The AVOL is adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for an ambient temperature of +25°C. Figures 52 through 66 show the characterization vs simulation results for the noise voltage, open loop gain phase, closed loop gain vs frequency, gain vs frequency vs RL, CMRR, large signal 10V step response, small signal 0.1V step, and output voltage swing ±15V supplies. LICENSE STATEMENT The information in the SPICE model is protected under United States copyright laws. Intersil Corporation hereby grants users of this macro-model, hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model, as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. FN7858 Rev 1.00 March 7, 2014 Page 16 of 23 DX D3 G1 + - I2 54E-6 I3 9 R2 5e11 4 V8 DN D13 750 2 R17 + ++ - - 0 D14 0 3 750 En Q8 CinDif 1.33E-12 5 R1 5e11 Cin2 4.02e-12 DX D5 + - C1 R7 6.6667E-11 3.7304227e9 GAIN = 1.69138e-3 -0.91 V3 6 Input Stage V+ R6 1 GAIN = 0.65897 D4 1st Gain Stage V++ V++ L3 3.18319E-09 V++ G9 + - R13 795.7981 D10 GAIN = 1.2566e-3 D7 D11 V5 DX 24 C3 10e-12 Vc Vg G2 V-- G5 + + 18 21 GAIN = 1 R9 GAIN = 1 R11 1e-3 1e-3 19 15 R4 1k DX 16 V2 -0.96 DX 3.18319E-09 GAIN = 1 V-- GAIN = 1 L1 Q9 14 EOS + + - - 12 11 Cin1 4.02e-12 E2 ++ - 0 PNP_LATERAL 10 PNP_input PNP_input D2 DBREAK R3 1k Vin+ GAIN = 0.3 Q6 8 IOS 4e-9 Vcm R18 Q7 7 DX DN PNP_LATERAL +- V7 -0.91 - 1 1 GAIN = 0.65897 V1 D1 DBREAK 0.1 0.1 R5 13 54E-6 Vin- ISL28118M FN7858 Rev 1.00 March 7, 2014 I1 80e-6 G13 GAIN = 12.5e-3 -0.4 23 26 R15 80 Vout VOUT 27 Vmid ISY D8 DX Page 17 of 23 D6 22 L4 3.18319E-09 GAIN = 1.2566e-3 R14 795.7981 V-- Mid Supply ref V D9 G11 G12 D12 + + GAIN = 12.5e-3 GAIN = 12.5e-3 V-V- 2nd Gain Stage -0.4 C4 10e-12 DY G8 L2 3.18319E-09 GAIN = 1 GAIN = 1 G10 DY + - GAIN = 1.69138e-3 3.7304227e9 20 G6 + - C2 6.6667E-11 17 R12 1e-3 + - G4 R10 1e-3 + - ++ - GAIN = 0.5 -0.96 V6 25 DX V4 Common Mode Gain Stage with Zero E3 + -+ GAIN = 1 V-- 0 FIGURE 50. SPICE SCHEMATIC Output Stage Correction Current Sources R16 + - 2.5E-3 G14 GAIN = 12.5e-3 80 ISL28118M *ISL28118_218 Macromodel - covers following *products *ISL28118 *ISL28218 * *Revision History: * Revision B, LaFontaine January 22 2014 * Model for Noise, supply currents, CMRR *120dB f = 40kHz, AVOL 136dB f = 0.5Hz * SR = 1.2V/us, GBWP 4MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model: *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages, * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging, *Load current reflected into the power supply *current. * source ISL28118_218 SPICEmodel * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output .subckt ISL28118_218 Vin+ Vin-V+ V- VOUT * source ISL28118_218_presubckt_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 V_V8 4 0 0.1 R_R17 2 0 750 *R_R18 3 0 750 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 80e-6 I_I2 V++ 7 DC 54E-6 I_I3 V++ 10 DC 54E-6 I_IOS 6 VIN- DC 4e-9 D_D1 7 10 DBREAK D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 1000 R_R4 V-- 11 1000 C_Cin1 V-- VIN- 4.02e-12 C_Cin2 V-- 6 4.02e-12 C_CinDif 6 VIN- 1.33E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.65897 G_G2 V-- 14 8 11 0.65897 V_V1 13 14 -0.91 V_V2 14 15 -0.96 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 1.69138e-3 G_G4 V-- VG 14 VMID 1.69138e-3 V_V3 16 VG -0.91 V_V4 VG 17 -0.96 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 3.7304227e9 R_R8 V-- VG 3.7304227e9 C_C1 VG V++ 6.6667E-11 C_C2 V-- VG 6.6667E-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 0.85E-3 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 1 G_G6 V-- 19 5 VMID 1 G_G7 V++ VC 19 VMID 1 G_G8 V-- VC 19 VMID 1 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 3.18319E-09 L_L2 20 V-- 3.18319E-09 L_L3 21 V++ 3.18319E-09 L_L4 22 V-- 3.18319E-09 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G9 V++ 23 VG VMID 1.2566e-3 G_G10 V-- 23 VG VMID 1.2566e-3 R_R13 23 V++ 795.7981 R_R14 V-- 23 795.7981 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28118_218 FIGURE 51. SPICE NET LIST FN7858 Rev 1.00 March 7, 2014 Page 18 of 23 ISL28118M Characterization vs Simulation Results INPUT NOISE VOLTAGE 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k 10k 1 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE CURRENT (fA/√Hz) 100 100 0.1 100k 10 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) FREQUENCY (Hz) 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PHASE GAIN 1 10 100 1k 10k 100k 1M 10M100M 1G 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 FIGURE 54. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY GAIN (dB) 40 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 30 20 ACL = 10 RF = 10kΩ, RG = 1kΩ 10 0 60 RF = 10kΩ, RG = 100Ω 50 40 30 20 0 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 56. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY FN7858 Rev 1.00 March 7, 2014 10 100 1k 10k 100k 1M 10M100M 1G RF = 10kΩ, RG = 10Ω ACL = 1000 RF = 10kΩ, RG = 100Ω 50 10 ACL = 1 -10 100 1 70 GAIN (dB) 60 GAIN FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY RF = 10kΩ, RG = 10Ω ACL = 1000 PHASE FREQUENCY (Hz) FREQUENCY (Hz) 70 100k FIGURE 53. SIMULATED INPUT NOISE VOLTAGE GAIN (dB) GAIN (dB) FIGURE 52. CHARACTERIZED INPUT NOISE VOLTAGE 10k -10 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 ACL = 10 RF = 10kΩ, RG = 1kΩ ACL = 1 RF = 0, RG = ∞ 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 57. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY Page 19 of 23 ISL28118M Characterization vs Simulation Results (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 RL = OPEN, 100k, 10k -4 -5 RL = 1k RL = 499k RL = 100k VS = ±15V -6 CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 1k 100 RL = 49.9k 10k 100k 1M -2 -3 -4 RL = OPEN, 100k, 10k -5 -6 CL = 4pF AV = +1 -8 VOUT = 100mVp-p -7 -9 100 10M 1k CMRR (dB) CMRR (dB) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 VOUT (V) VOUT (V) VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 0 0 -2 -2 -4 -4 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 62. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE FN7858 Rev 1.00 March 7, 2014 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 6 VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 20 10M FIGURE 61. SIMULATED CMRR vs FREQUENCY 6 10 1M FIGURE 59. SIMULATED GAIN vs FREQUENCY vs RL FIGURE 60. CHARACTERIZED CMRR vs FREQUENCY 0 100k FREQUENCY (Hz) FIGURE 58. CHARACTERIZED GAIN vs FREQUENCY vs RL -6 RL = 49.9k 10k FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 RL = 1k RL = 499k RL = 100k VS = ±15V -6 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 63. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE Page 20 of 23 ISL28118M Characterization vs Simulation Results (Continued) 100 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (V) 60 VOUT (V) 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 2.0 0 0.2 0.4 0.6 FIGURE 64. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE 20V OUTPUT VOLTAGE SWING (V) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (µs) TIME (µs) FIGURE 65. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE VOH = 14.88V 10V 0V -10V VS = ±15V RL = 10k -20V 0 VOL = -14.93V 0.5 1.0 TIME (ms) 1.5 2.0 FIGURE 66. SIMULATED OUTPUT VOLTAGE SWING FN7858 Rev 1.00 March 7, 2014 Page 21 of 23 ISL28118M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE March 7, 2014 FN7858.1 Updated Spice model netlist on page 18. Changed POD: FROM M8.118: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36" To M8.118B: Correct lead dimension in side view 2 from 0.15 - 0.05mm to 0.15+/-0.05mm May 11, 2011 FN7858.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2011-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7858 Rev 1.00 March 7, 2014 Page 22 of 23 ISL28118M Package Outline Drawing M8.118B 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 3/12 3.0±0.10mm 5 A D 8 4.9±0.20mm DETAIL "X" 3.0±0.10mm 5 1.10 MAX 0.15±0.05mm PIN# 1 ID SIDE VIEW 2 1 2 B 0.65mm BSC TOP VIEW 0.95 REF 0.86±0.05mm H GAUGE PLANE C 0.25 SEATING PLANE 0.23 - 0.36mm 0.08 M C A-B D 0.10 ± 0.05mm 3°±3° 0.10 C 0.53 ± 0.10mm SIDE VIEW 1 DETAIL "X" (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN7858 Rev 1.00 March 7, 2014 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 23 of 23