ISL28146

® ISL28146, ISL28246 Data Sheet June 23, 2008 FN6321.3 5MHz, Single and Dual Rail-to-Rail Input-Output (RRIO) Op Amps The ISL28146 and ISL28246 are low-power single and dual operational amplifiers optimized for single supply operation from 2.4V to 5.5V, allowing operation from one lithium cell or two Ni-Cd batteries. They feature a gain-bandwidth product of 5MHz and are unity-gain stable with a -3dB bandwidth of 13MHz. These devices feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging 0.25V above a 5.0V supply and to within 10mV from ground. The output operation is rail-to-rail. The parts draw minimal supply current while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28146 features an enable pin that can be used to turn the device off and reduce the supply current to only 16µA. Operation is guaranteed over -40°C to +125°C temperature range. Features • 5MHz gain bandwidth product @ AV = 100 • 13MHz -3db unity gain bandwidth • 1mA typical supply current (per amplifier) • 650µV maximum offset voltage • 16nA typical input bias current • Down to 2.4V single supply voltage range • Rail-to-rail input and output • Enable pin (ISL28146 only) • -40°C to +125°C operation • Pb-free (RoHS compliant) Applications • Low-end audio • 4mA to 20mA current loops • Medical devices Ordering Information PART NUMBER (Note) ISL28146FHZ-T7* ISL28146FHZ-T7A* ISL28246FBZ ISL28246FBZ-T7* ISL28246FUZ ISL28246FUZ-T7* ISL28146EVAL1Z ISL28246SOICEVAL1Z ISL28246MSOPEVAL1Z PART MARKING GABS GABS 28246 FBZ 28246 FBZ 8246Z 8246Z PACKAGE (Pb-Free) 6 Ld SOT-23 6 Ld SOT-23 8 Ld SOIC 8 Ld SOIC 8 Ld MSOP 8 Ld MSOP PKG. DWG. # MDP0038 MDP0038 MDP0027 MDP0027 MDP0043 MDP0043 • Sensor amplifiers • ADC buffers • DAC output amplifiers Pinouts ISL28146 (6 LD SOT-23) TOP VIEW OUT 1 V- 2 IN+ 3 6 V+ 5 EN 4 INOUT_A 1 IN-_A 2 IN+_A 3 V- 4 -+ +- ISL28246 (8 LD MSOP) TOP VIEW 8 V+ 7 OUT_B 6 IN-_B 5 IN+_B +- Evaluation Board - 6 Ld SOT-23 Evaluation Board - 8 Ld SOIC Evaluation Board - 8 Ld MSOP *Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ISL28246 (8 LD SOIC) TOP VIEW OUT_A 1 IN-_A 2 IN+_A 3 V- 4 -+ +8 V+ 7 OUT_B 6 IN-_B 5 IN+_B 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL28146, ISL28246 Absolute Maximum Ratings (TA = +25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500V Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 120 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 160 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT PARAMETER DC SPECIFICATIONS VOS Δ V OS --------------ΔT IOS IB CMIR CMRR PSRR AVOL DESCRIPTION Input Offset Voltage Input Offset Voltage vs Temperature Input Offset Current Input Bias Current Common-Mode Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Guaranteed by CMRR VCM = 0V to 5V V+ = 2.4V to 5.5V VO = 0.5V to 4V, RL = 100kΩ to VCM VO = 0.5V to 4V, RL = 1kΩ to VCM -650 -750 30 0.3 650 750 µV µV/°C -10 -15 -35 -40 0 90 85 90 85 600 500 0 16 10 15 35 40 5 nA nA V dB dB V/mV V/mV 114 99 1770 140 3 70 6 10 90 110 VOUT Maximum Output Voltage Swing Output low, RL = 100kΩ to VCM Output low, RL = 1kΩ to VCM Output high, RL = 100kΩ to VCM Output high, RL = 1kΩ to VCM 4.99 4.98 4.92 4.89 mV mV mV V 4.994 4.94 1 10 1.25 1.4 14 16 IS,ON IS,OFF Supply Current, Enabled Supply Current, Disabled Per Amplifier mA µA 2 FN6321.3 June 23, 2008 ISL28146, ISL28246 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) CONDITIONS RL = 10Ω to VCM RL = 10Ω to VCM V+ to V2.4 2 0.8 VEN = V+ VEN = V1 16 1.5 1.6 25 30 MIN (Note 2) 48 45 TYP 56 -54 -48 -45 5.5 MAX (Note 2) UNIT mA mA V V V µA nA PARAMETER IO+ IOVSUPPLY VENH VENL IENH IENL DESCRIPTION Short-Circuit Output Source Current Short-Circuit Output Sink Current Supply Operating Range EN Pin High Level, ISL28146 Only EN Pin Low Level, ISL28146 Only EN Pin Input High Current, ISL28146 Only EN Pin Input Low Current, ISL28146 Only AC SPECIFICATIONS GBW Unity Gain Bandwidth eN Gain Bandwidth Product -3dB Bandwidth Input Noise Voltage Peak-to-Peak Input Noise Voltage Density iN CMRR PSRRto 120Hz PSRR+ to 120Hz Input Noise Current Density Input Common Mode Rejection Ratio Power Supply Rejection Ratio (V-) Power Supply Rejection Ratio (V+) AV = 100, RF = 100kΩ, RG = 1kΩ AV =1, RF = 0Ω, RL = 10kΩ, VOUT = 10mVP-P f = 0.1Hz to 10Hz fO = 1kHz fO = 10kHz fO = to 120Hz; VCM = 1VP-P, RL = 1kΩ V+, V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 1kΩ V+, V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 1kΩ 5 13 0.4 12 0.35 -90 -88 -105 MHz MHz µVP-P nV/√Hz pA/√Hz dB dB dB TRANSIENT RESPONSE SR tr, tf, Large Signal Slew Rate Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT tEN Enable to Output Turn-on Delay Time, 10% EN to 10% VOUT Enable to Output Turn-off Delay Time, 10% EN to 10% VOUT NOTE: 2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. VOUT = ±1.5V, Rf = 50kΩ, RG = 50kΩ to VCM ±1.9 0.6 0.5 65 62 5 0.3 V/µs µs µs nS nS µs µs AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 1kΩ to VCM AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 1kΩ to VCM AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 1kΩ to VCM AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 1kΩ to VCM VEN = 5V to 0V, AV = +2, Rg = Rf = RL = 1kΩ to VCM VEN = 0V to 5V, AV = +2, Rg = Rf = RL = 1kΩ to VCM tr, tf, Small Signal 3 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 15 NORMALIZED GAIN (dB) 10 5 0 V + = 5V R L = 1k CL = 16.3pF -10 AV = +2 VOUT = 10mVP-P -15 100 1k 10k -5 Rf = Rg = 1 k Rf = Rg = 100k Rf = Rg = 10k NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 100k 1M 10M 100M VOUT = 1V VOUT = 100mV VOUT = 50mV VOUT = 10mV V+ = 5V RL = 1k CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M -9 10k FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k 1 NORMALIZED GAIN (dB) 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 VOUT = 1V VOUT = 100mV VOUT = 50mV VOUT = 10mV V + = 5V RL = 10k CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M 1 0 -1 -2 -3 -4 -5 -6 -7 -8 VOUT = 1V VOUT = 100mV VOUT = 50mV VOUT = 10mV V+ = 5V RL = 100k CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M -9 10k -9 10k FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k 1 NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 V+ = 5V CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M RL =1k RL =10k GAIN (dB) RL =100k 70 60 AV = 1001, Rg = 1k, Rf = 1M V + = 5V CL = 16.3pF RL = 10k VOUT = 10mVP-P 50 AV = 101, Rg = 1k, Rf = 100k 40 30 20 10 0 -10 100 AV = 1, Rg = INF, Rf = 0 AV = 10, Rg = 1k, Rf = 9.09k -9 10k 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 5. GAIN vs FREQUENCY vs RL FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 4 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 RL = 10k CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M V+ = 2.4V V+ = 5V (Continued) -9 10k 8 7 6 5 4 3 2 1 0 -1 -2 -3 V+ = 5V -4 RL = 1k -5 A = +1 V -6 VOUT = 10mVP-P -7 -8 10k 100k CL = 51.7pF CL = 43.7pF CL = 37.7pF CL = 26.7pF CL = 16.7pF CL = 4.7pF 1M FREQUENCY (Hz) 10M 100M FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 8. GAIN vs FREQUENCY vs CL 20 0 CMRR (dB) -20 PSRR (dB) -40 -60 -80 -100 10 V+ = 2.4V, 5V RL = 1 k CL = 16.3pF AV = +1 VCM = 1VP-P 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 20 0 -20 -40 -60 -80 -100 -120 10 V+, V- = ±1.2V R L = 1k CL = 16.3pF AV = +1 VSOURCE = 1VP-P PSRR- PSRR+ 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 9. CMRR vs FREQUENCY, V+ = 2.4V and 5V FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V 20 INPUT VOLTAGE NOISE (nV/√Hz) 0 -20 PSRR (dB) -40 -60 -80 -100 -120 10 V+, V- = ±2.5V RL = 1 k CL = 16.3pF AV = +1 VSOURCE = 1VP-P 100 V+ = 5V RL = 1k CL = 16.3pF AV = +1 PSRRPSRR+ 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 11. PSRR vs FREQUENCY, V, V+, V- = ±2.5V FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 5 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 10 INPUT CURRENT NOISE (pA/√Hz) V + = 5V RL = 1 k CL = 16.3pF AV = +1 1 0.5 0.4 0.3 INPUT NOISE (µV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0.1 1 10 100 1k 10k 100k -0.5 0 1 2 3 4 5 6 7 8 9 10 V+ = 5V RL = 10k CL = 16.3pF Rg = 10, Rf = 100k AV = 10000 (Continued) FREQUENCY (Hz) TIME (s) FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz to 10Hz 1.5 1.0 SMALL SIGNAL (V) LARGE SIGNAL (V) 0.026 0.024 0.022 0.020 0.018 0.016 0.014 0.012 0 1 2 3 4 5 6 TIME (µs) 7 8 9 10 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg = Rf = 10k AV = 2 VOUT = 10mVP-P 0.5 0 -0.5 -1.0 -1.5 V+, V- = ±2.5V RL = 1 k CL = 16.3pF Rg = Rf = 10k AV = 2 VOUT = 1.5VP-P FIGURE 15. LARGE SIGNAL STEP RESPONSE FIGURE 16. SMALL SIGNAL STEP RESPONSE 6 V-ENABLE 5 V-ENABLE (V) 4 3 2 1 0 -1 0 10 20 30 40 50 60 TIME (µs) 70 80 90 V + = 5V Rg = Rf = RL = 1k CL = 16.3pF AV = +2 VOUT = 1VP-P V-OUT 1.3 1.1 0.9 OUTPUT (V) 100 80 V+ = 5V RL = OPEN 60 R = 100k, R = 100 f g 40 AV = +1000 VOS (µV) 20 0 -20 -40 -60 -80 -100 -1 0 1 2 3 VCM (V) 4 5 6 0.7 0.5 0.3 0.1 -0.1 100 FIGURE 17. ENABLE TO OUTPUT RESPONSE FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 6 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 100 80 60 40 I-BIAS (nA) 20 0 -20 -40 -60 -80 -100 -1 V + = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1000 0 1 2 3 VCM (V) 4 5 6 (Continued) FIGURE 19. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE 1200 1100 MAX CURRENT (µA) 1000 MEDIAN 900 MIN 800 700 N = 1150 600 -40 -20 0 20 40 60 80 100 120 CURRENT (µA) 11 MAX 10 9 8 7 6 MIN 5 N = 1150 4 -40 -20 0 20 40 60 80 100 120 MEDIAN TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE, V+, V- = ±2.5V FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE, V+, V- = ±2.5V 750 550 350 VOS (µV) VOS (µV) 150 -50 -250 -450 -650 N = 1150 -850 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN MAX 750 550 350 150 -50 -250 MIN -450 N = 1150 -650 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 22. VOS (SOT PKG) vs TEMPERATURE, V+, V- = ±2.5V FIGURE 23. VOS (SOT PKG) vs TEMPERATURE, V+, V- = ±1.2V 7 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 30 25 MAX 20 IBIAS- (nA) IBIAS+ (nA) 15 10 5 0 -5 -10 -40 -20 0 20 MIN 40 60 80 MEDIAN 20 15 10 5 0 -5 N = 1150 100 120 -10 -40 -20 0 20 40 60 80 TEMPERATURE (°C) N = 1150 100 120 MIN MEDIAN 30 25 MAX (Continued) TEMPERATURE (°C) FIGURE 24. IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V FIGURE 25. IBIAS- vs TEMPERATURE, V+, V- = ±2.5V 15 10 MAX 5 IBIAS+ (nA) 0 MEDIAN -5 -10 -15 -20 -25 -40 -20 0 20 MIN 40 60 80 N = 1150 100 120 IBIAS- (nA) 20 15 10 5 0 MEDIAN -5 -10 -15 -20 N = 1150 -25 -40 -20 0 20 40 60 80 100 120 MIN MAX TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 26. IBIAS+ vs TEMPERATURE, V+, V- = ±1.2V FIGURE 27. IBIAS- vs TEMPERATURE, V+, V- = ±1.2V 10 8 MAX 6 4 IOS (nA) 2 0 -2 -4 -6 -8 -40 -20 0 20 40 60 MIN N = 1150 80 100 120 MEDIAN IOS (nA) 12 10 8 6 4 2 0 -2 -4 -6 -8 -40 -20 0 20 40 60 80 MIN N = 1150 100 120 MEDIAN MAX TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 28. IOS vs TEMPERATURE V+, V- = ±2.5V FIGURE 29. IOS vs TEMPERATURE V+, V- = ±1.2V 8 FN6321.3 June 23, 2008 ISL28146, ISL28246 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 140 135 130 125 CMRR (dB) 120 115 110 105 100 95 90 -40 -20 0 20 40 60 80 TEMPERATURE (°C) MIN N = 1150 100 120 MEDIAN PSRR (dB) MAX 120 115 MAX 110 105 MEDIAN 100 95 MIN 90 -40 -20 0 20 40 60 80 N = 1150 100 120 (Continued) TEMPERATURE (°C) FIGURE 30. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V, V+, V- = ±2.5V FIGURE 31. PSRR vs TEMPERATURE V+, V- = ±1.2V TO ±2.75V 4500 4000 3500 AVOL (V/mV) AVOL (V/mV) 3000 2500 2000 MEDIAN 1500 1000 MIN 500 0 -40 -20 0 20 40 60 80 N = 1150 100 120 MAX 200 180 MAX 160 MEDIAN 140 120 100 MIN 80 N = 1150 60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 TEMPERATURE (°C) FIGURE 32. AVOL vs TEMPERATURE V+, V- = ±2.5V, VO = +2V, RL= 100k FIGURE 33. AVOL vs TEMPERATURE V+, V- = ±2.5V, VO = +2V, RL = 1k 4.960 MAX 4.955 4.950 VOUT (V) MEDIAN 4.945 4.940 MIN 4.935 N = 1150 4.930 -40 -20 0 20 40 60 80 100 120 75 70 MAX VOUT (mV) 65 60 55 MIN 50 N = 1150 45 -40 -20 0 20 40 60 80 100 120 MEDIAN TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 34. VOUT HIGH vs TEMPERATURE V+, V- = ±2.5V, RL = 1k FIGURE 35. VOUT LOW vs TEMPERATURE V+, V- = ±2.5V, RL = 1k 9 FN6321.3 June 23, 2008 ISL28146, ISL28246 Pin Descriptions ISL28146 (6 Ld SOT-23) 4 2 (A) 6 (B) ISL28246 (8 Ld SOIC) (8 Ld MSOP) PIN NAME ININ-_A IN-_B FUNCTION Inverting input EQUIVALENT CIRCUIT V+ IN- IN+ VCircuit 1 3 3 (A) 5 (B) 2 4 IN+ IN+_A IN-+_B V- Non-inverting input See Circuit 1 Negative supply V+ CAPACITIVELY COUPLED ESD CLAMP VCircuit 2 1 1 (A) 7 (B) OUT OUT_A OUT_B Output V+ OUT VCircuit 3 6 5 8 V+ EN Positive supply Chip enable See Circuit 2 V+ LOGIC PIN VCircuit 3 10 FN6321.3 June 23, 2008 ISL28146, ISL28246 Applications Information Introduction The ISL28146 and ISL28246 are single and dual channel rail-to-rail input, output (RRIO) micropower precision operational amplifiers. The parts are designed to operate from single supply (2.4V to 5.0V) or dual supply (±1.2V to ±2.75V). The parts have an input common mode range that extends 0.25V above the positive rail and down to the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load. external series resistor must be used to ensure the input currents never exceed 5mA (Figure 36). VIN RIN + RL VOUT FIGURE 36. INPUT CURRENT LIMITING Enable/Disable Feature The ISL28146 offers an EN pin that disables the device when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 10µA at room temperature. The EN pin has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default. When not used, the EN pin should either be left floating or connected directly to the -V pin. By disabling the part, multiple ISL28146 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or a large value RF, to keep the feed through current low enough to minimize the impact on the active channel. See “Limitations of the Differential Input Protection” on page 11. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28146 and ISL28246 achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives an undistorted behavior from typically down to the negative rail and up to 0.25V higher than the V+ rail. Rail-to-Rail Output A pair of complementary MOS devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The ISL28146 and ISL28246 with a 100kΩ load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail. Limitations of the Differential Input Protection If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications, the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1. During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise. 2. When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3. When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep FN6321.3 June 23, 2008 Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. The output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr. of exposure under these conditions. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (“Pin Descriptions” on page 10 - Circuit 1). For applications where the input differential voltage is expected to exceed 0.5V, an 11 ISL28146, ISL28246 up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 1.9V/µs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application RL = Load resistance Using Only One Channel The ISL28246 is a dual op amp. If the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (Figure 37). + ECG/EEG AMPLIFIER APPLICATION CIRCUIT ECG and EEG amplifiers must extract millivolt low frequency AC signals from the skin of the patient while rejecting AC common mode interference and static DC potentials created at the electrode-to-skin interface. In Figure 38, the EL8171 Instrumentation amplifier (U1) and the ISL28146 (U2) form a differential input, high impedance high pass patient lead amplifier. U2, RF1 and CF1 form a low pass active feedback amplifier. Inserting this amplifier in the feedback loop results in a high pass frequency response in the forward direction. The corner frequency is given by Equation 3: f – HPF – 3dB = 1/[2* π *RF1*CF1 (EQ. 3) FIGURE 37. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Current Limiting These devices have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation It is possible to exceed the +125°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) (EQ. 1) Voltage dividers R1 through R2 and R3 through R4 set the overall amplifier pass-band gain. Unwanted DC offsets appearing at the patient leads are cancelled by U2 at U1A’s inverting input. Resistor divider pair, R3 through R4 define the maximum input DC level that is cancelled, and is given by Equation 4: V IN DC = V + [R 4 ⁄ ( R 3 + R 4 ) ] (EQ. 4) In the passband range, U1B’s gain is +1 and the total signal gain is defined by the divider ratios according to Equation 5: V OUT U1 Gain = V OUT ⁄ V IN = [ ( R 1 + R 2 ) ⁄ R 2 ]∗ [ ( R 3 + R 4 ) ⁄ R 4 ] (EQ. 5) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × --------------------------R L The gain bandwidth product of the differential amplifier U1 determines the frequency response limit. Reference amplifiers U3A and U3B form a DC feedback loop that supplies a reference voltage drive to the patient to establish a common mode DC reference for the differential amplifiers. The voltage at the VCM sense electrode is maintained at the reference voltage set by RF1-RF2. With the values shown in Figure 38, the performance parameters are: 1. Supply Voltage range = +2.4V to +5.5V 2. Total supply current draw @ +5V = 1.3mA (typ) 3. Common-mode reference voltage (VCM) = V+/2 4. Max DC Input Offset Voltage = VCM ±0.18V to ±0.41V 5. Passband Gain = 425V/V 6. Lower -3dB Frequency = 0.05Hz (EQ. 2) 12 FN6321.3 June 23, 2008 ISL28146, ISL28246 PATIENT LEAD CONNECTOR V+ R VIN+ 10k VDC Offset V+ + U1 FB+ EL8171 R 1k C 0.01µF V+ RFA 10k RFB 10k 0.47µF VOUT+ VOUT+2.4 TO 5.5V SUPPLY 4.7µF V+ Signal VIN- R 10k FB0.082µF C3 V+ U2 + ISL28146 - R1 10k VDC Offset PATIENT ELECTRODE PADS V+ VCM SENSE R 10k R3 12.4k R4 2.21k R2 158Ω Signal CF1 4.7µF RF1 680k SUPPLY COMMON V+ + U3A 1/2 ISL28288 R 5k VCM REFERENCE TO OTHER CHANNELS VCM VCM DRIVE V+ R 10k PROTECTION CIRCUIT CA 1nF R 500k CB V+ 1nF U3B 1/2 ISL28288 + FIGURE 38. ECG/EEG AMPLIFIER 13 FN6321.3 June 23, 2008 ISL28146, ISL28246 SOT-23 Package Family e1 A N 6 4 MDP0038 D SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX ±0.05 ±0.15 ±0.05 ±0.06 Basic Basic Basic Basic Basic ±0.10 Reference Reference Rev. F 2/07 NOTES: E1 2 3 E A2 b c 0.20 C 0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D D E E1 e e1 L L1 N 0.15 C A-B 2X C D 1 3 A2 SEATING PLANE 0.10 C NX A1 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) H 6. SOT23-5 version has no center lead (shown as a dashed line). A GAUGE PLANE c L 0° +3° -0° 0.25 14 FN6321.3 June 23, 2008 ISL28146, ISL28246 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07 15 FN6321.3 June 23, 2008 ISL28146, ISL28246 Mini SO Package Family (MSOP) 0.25 M C A B D N A (N/2)+1 MDP0043 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. ±0.05 ±0.09 +0.07/-0.08 ±0.05 ±0.10 ±0.15 ±0.10 Basic ±0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. E E1 PIN #1 I.D. A2 b c B 1 (N/2) D E E1 e C SEATING PLANE 0.10 C N LEADS b H e L L1 N 0.08 M C A B L1 A c SEE DETAIL "X" 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. A2 GAUGE PLANE L DETAIL X 0.25 A1 3° ±3° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6321.3 June 23, 2008