ISL32175E

QUAD, ±16.5kV ESD Protected, 3.0V to 5.5V, RS-485/RS-422 Receivers ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E These Intersil devices are ±16.5kV IEC61000-4-2 ESD protected, 3.0V to 5.5V powered, QUAD receivers for balanced communication using the RS-485 and RS-422 standards. Each receiver has low input currents (±200μA), so it presents a 1/4 unit load to the RS-485 bus, and allows up to 128 receivers on the bus. The ISL32173E, ISL32175E, ISL32177E are high data rate receivers that operate at data rates up to 80Mbps. Their 8ns maximum propagation delay skew (tolerance) guarantees excellent part-to-part matching. The ISL32273E, ISL32275E, ISL32277E are reduced supply current versions that operate at data rates up to 20Mbps. Receiver outputs are tri-statable, and incorporate a hot plug feature to keep them disabled during power up and down. Versions are available with a common EN/EN (‘173 pinout), a two channel EN12/EN34 (‘175 pinout), or a versatile individual channel enable (see Table 1) A 26% smaller footprint is available with the ISL32177E and ISL32277E QFN packages, and these two devices also feature a logic supply pin (VL). The VL supply sets the switching points of the enable inputs, and the receiver outputs’ VOH, to levels compatible with a lower supply voltage in mixed voltage systems. Individual channel and group enable pins increase the ISL32177E and ISL32277E’s flexibility. ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Features • IEC61000 ESD Protection (RS-485 Inputs) ±16.5kV - Class 3 ESD on all Other Pins . . . . . .>8kV HBM • Wide Supply Range. . . . . . . . . . . . . 3.0V to 5.5V • Wide Common Mode Range . . . . . . . -7V to +12V • Low Part-to-Part Propagation Delay Tolerance . . . . . . . . . . . . . . . . . . . ±4ns (max) • Specified for +125°C Operation • Fail-Safe Open Rx Inputs • 1/4 Unit Load Allows 128 Devices on the Bus • Available in Industry Standard Pinouts (‘173/’175) and a 4x4 QFN (ISL32X77E) with Added Features • Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL32X77E) • High Data Rates . . . . . . . . . up to 80M or 20Mbps • Low Shutdown Supply Current . . . . . . . . . . 60μA • Tri-statable Rx Outputs • 5V Tolerant Logic Inputs When VCC = 3.3V Applications*(see page 19) • • • • Telecom Equipment Motor Controllers/Encoders Programmable Logic Controllers Industrial/Process Control Networks ISL32177E Part-to-Part Prop Delay Variability VCC = 3.3V, +25°C # of DEVICES = 270 ISL3217XE Data Rate and VL Performance RECEIVER OUTPUT (V) RECEIVER INPUT (V) 80Mbps 1 0 -1 A-B VCC = 3.3V FREQUENCY 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 VL = 2.5V VL = 1.8V VL = 1.6V 10.04 10.17 10.29 10.41 10.54 10.66 10.78 10.91 11.03 11.15 11.28 11.40 11.52 9.67 9.80 9.92 RECEIVER PROPAGATION DELAY (ns) TIME (4ns/DIV) November 19, 2009 FN7529.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E TABLE 1. SUMMARY OF FEATURES DATA VL RATE HOT SUPPLY FUNCTION (Mbps) PLUG? PIN? 4 Rx 4 Rx 4 Rx 4 Rx 4 Rx 4 Rx 80 80 80 20 20 20 YES YES YES YES YES YES NO NO YES NO NO YES MAX. TOTAL SUPPLY CURRENT (mA) 15 15 15 5.5 5.5 5.5 PART NUMBER ISL32173E ISL32175E ISL32177E ISL32273E ISL32275E ISL32277E Rx ENABLE TYPE EN, EN EN12, EN34 INDIVIDUAL AND GROUP ENABLES EN, EN EN12, EN34 INDIVIDUAL AND GROUP ENABLES LOW POWER SHUTDOWN? YES YES YES YES YES YES PIN COUNT 16 16 24 16 16 24 Pin Configurations ISL32173E, ISL32273E (16 LD N-SOIC, 16 LD TSSOP) TOP VIEWS B1 1 A1 2 RO1 3 EN 4 RO2 5 A2 6 B2 7 GND 8 R R R R 16 VCC 15 B4 14 A4 13 RO4 12 EN 11 RO3 10 A3 9 B3 ISL32175E, ISL32275E (16 LD N-SOIC, 16 LD TSSOP) TOP VIEWS B1 1 A1 2 RO1 3 EN12 4 RO2 5 A2 6 B2 7 GND 8 R R R R 16 VCC 15 B4 14 A4 13 RO4 12 EN34 11 RO3 10 A3 9 B3 ISL32177E, ISL32277E (24 LD QFN) TOP VIEW VCC A1 A4 19 18 RO4 R R 17 EN4 16 EN3 15 EN R 14 NC 13 RO3 7 A2 8 B2 9 SHDNEN 10 GND 11 B3 12 A3 B1 B4 20 VL 21 24 RO1 EN1 EN2 EN NC RO2 1 2 3 4 5 6 23 22 PAD (GND) R 2 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Pin Descriptions ISL32173E, ISL32175E, ISL32177E, ISL32273E ISL32275E ISL32277E PIN NUMBER PIN NUMBER PIN NUMBER 4, 12 4, 15 PIN EN, EN FUNCTION Group driver output enables, that are internally pulled high to VCC. All receiver outputs are enabled by driving EN high OR EN low, and the outputs are all high impedance when EN is low AND EN is high (i.e., if using only the active high EN, connect EN to VCC or VL through a 1kΩ resistor; if using only the active low EN, connect EN directly to GND). If the group enable function isn’t required, connect EN to VCC (or VL) through a 1kΩ or greater resistor, or connect EN directly to GND. (ISL32X73E and ISL32X77E only) Paired driver output enables, that are internally pulled high to VCC. Driving EN12 (EN34) high enables the channel 1 and 2 (3 and 4) RO outputs. Driving EN12 (EN34) low disables the channel 1 and 2 (3 and 4) outputs. If the enable function isn’t required, connect EN12 and EN34 to VCC (or VL) through a 1kΩ or greater resistor. (ISL32X75E only). Individual receiver output enables that are internally pulled high to VCC. Forcing ENX high (along with EN high OR EN low) enables the channel X output (ROX). Driving ENX low disables the channel X output, regardless of the states of EN and EN. If the individual channel enable function isn’t required, connect ENX to VCC (or VL) through a 1kΩ or greater resistor. (ISL32X77E only) Low power SHDN mode enable that is internally pulled high to VCC. A high level allows the ISL32X77E to enter a low power mode when all channels are disabled. A low level prevents the device from entering the low power mode. (ISL32X77E only) Channel X receiver output: If A - B ≥ 200mV, RO is high; If A - B ≤ -200mV, RO is low. RO = High if A and B are unconnected (floating). Ground connection. This is also the potential of the QFN thermal pad. ±16.5kV IEC61000-4-2 ESD Protected RS-485/422 level, channel X noninverting receiver input. ±16.5kV IEC61000-4-2 ESD Protected RS-485/422 level, channel X inverting receiver input. System power supply input (3.0V to 5.5V). On devices with a VL pin, power up VCC first. Logic power supply input (1.4V to VCC) that powers all the TTL/CMOS inputs and outputs (logic pins). VL sets the VIH and VIL levels of the enable and SHDNEN pins, and sets the VOH level of the RO pins. Connect the VL pin to the lower voltage power supply of a logic device (e.g., UART or μcontroller) interfacing with the ISL32X77E logic pins. Power up this supply after VCC, and keep VL ≤ VCC. To minimize input current and SHDN supply current, logic pins that are strapped high externally (preferably through a 1kΩ resistor) should connect to VCC, but they may also connect to VL. (ISL32X77E only) No Connection. - 4, 12 - EN12, EN34 - - 2, 3, 16, 17 EN1, EN2, EN3, EN4 - - 9 SHDNEN 3, 5, 11, 13 8 2, 6, 10, 14 1, 7, 9, 15 16 - 3, 5, 11, 13 8 2, 6, 10, 14 1, 7, 9, 15 16 - 1, 6, 13, 18 10, PD 24, 7, 12, 19 23, 8, 11, 20 22 21 RO1, RO2, RO3, RO4 GND A1, A2, A3, A4 B1, B2, B3, B4 VCC VL - - 5, 14 NC 3 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Ordering Information PART NUMBER (Notes 1, 2, 3) ISL32173EIBZ ISL32173EFBZ ISL32173EIVZ ISL32173EFVZ ISL32175EIBZ ISL32175EFBZ ISL32175EIVZ ISL32175EFVZ ISL32177EIRZ ISL32177EFRZ ISL32273EIBZ ISL32273EFBZ ISL32273EIVZ ISL32273EFVZ ISL32275EIBZ ISL32275EFBZ ISL32275EIVZ ISL32275EFVZ ISL32277EIRZ ISL32277EFRZ NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL32173E,ISL32175E,ISL32177E,ISL32273E, ISL32275E, ISL32277E. For more information on MSL please see techbrief TB363. PART MARKING ISL32173 EIBZ ISL32173 EFBZ 32173 EIVZ 32173 EFVZ ISL32175 EIBZ ISL32175 EFBZ 32175 EIVZ 32175 EFVZ 321 77EIRZ 321 77EFRZ ISL32273 EIBZ ISL32273 EFBZ 32273 EIVZ 32273 EFVZ ISL32275 EIBZ ISL32275 EFBZ 32275 EIVZ 32275 EFVZ 322 77EIRZ 322 77EFRZ TEMP. RANGE (°C) -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 PACKAGE (Pb-Free) 16 Ld SOIC 16 Ld SOIC 16 Ld TSSOP 16 Ld TSSOP 16 Ld SOIC 16 Ld SOIC 16 Ld TSSOP 16 Ld TSSOP 24 Ld QFN 24 Ld QFN 16 Ld SOIC 16 Ld SOIC 16 Ld TSSOP 16 Ld TSSOP 16 Ld SOIC 16 Ld SOIC 16 Ld TSSOP 16 Ld TSSOP 24 Ld QFN 24 Ld QFN PKG. DWG. # M16.15 M16.15 MDP0044 MDP0044 M16.15 M16.15 MDP0044 MDP0044 L24.4x4C L24.4x4C M16.15 M16.15 MDP0044 MDP0044 M16.15 M16.15 MDP0044 MDP0044 L24.4x4C L24.4x4C Truth Tables RECEIVER OUTPUT (ROX ENABLED, ALL VERSIONS) INPUTS (A-B) ≥0.2V ≤-0.2V Inputs Open (Floating) OUTPUT (RO) 1 0 1 RECEIVER ENABLE (ISL32173E, ISL32273E) INPUTS EN X 1 0 EN 0 X 1 OUTPUTS ROX ENABLED ENABLED DISABLED* NOTE: *Low Power SHDN Mode When Disabled 4 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Truth Tables INPUTS EN12 0 0 1 1 EN34 0 1 0 1 (Continued) RECEIVER ENABLE (ISL32177E, ISL32277E) INPUTS ENX RO4 Z* EN Z EN 0 EN1-4 = 0 X X 1 1 EN EN SHDNEN ROX X X 0 0 X 1 X X 1 1 0 X 0 1 0 1 X X Z Z* Z Z* EN EN OUTPUTS COMMENTS Chan X output disabled All outputs disabled All outputs disabled All outputs disabled Individual ENX controls chan RECEIVER ENABLE (ISL32175E, ISL32275E) OUTPUTS RO1 Z* Z EN EN RO2 Z* Z EN EN RO3 Z* EN Z EN NOTE: *Low Power SHDN Mode When All Outputs Disabled; Z = Tri-state NOTE: * Low Power SHDN Mode; Z = Tri-state Typical Operating Circuits (1 of 4 Channels Shown) NETWORK USING GROUP ENABLES +3.3V TO 5V 16 VCC ISL32X73E 3 RO 12 EN A R B 2 1 RT 2Y 3Z D + 0.1μF + 0.1μF +3.3V TO 5V 16 VCC ISL32X72E DI 1 EN 4 EN 12 GND 8 EN 4 GND 8 ≥1kΩ NETWORK USING PAIRED ENABLES +3.3V TO 5V 16 VCC ISL32X75E 3 RO1 4 EN12 A1 2 R B1 1 RT + 0.1μF + 0.1μF +3.3V TO 5V 16 VCC ISL32X74E EN12 4 2 Y1 3 Z1 D DI1 1 GND 8 GND 8 5 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Operating Circuits (1 of 4 Channels Shown) (Continued) NETWORK WITH VL PIN FOR INTERFACING TO LOWER VOLTAGE LOGIC DEVICES +1.8V +3.3V TO 5V 21 VCC LOGIC DEVICE (μP, ASIC, UART) VL 22 ≥1kΩ + 0.1μF ≥1kΩ + +3.3V TO 5V +2.5V 21 20 VCC VL 22 SHDNEN 14 EN ISL32179E 2, 3, 15, 16 EN1-EN4 24 Y 1Z GND 9 USING ACTIVE HIGH GROUP ENABLE AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER UP VCC BEFORE VL D DI EN 0.1μF VCC 9 SHDNEN 15 ISL32X77E EN 4 EN A1 24 1 RO1 R B1 23 2 EN1 GND 10 VCC LOGIC DEVICE (μP, ASIC, UART) RT 23 4 USING INDIVIDUAL CHANNEL ENABLES AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER UP VCC BEFORE VL 6 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Absolute Maximum Ratings VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V VL to GND (Note 4) . . . . . . . . . . . . . . -0.3V to (VCC +0.3V) Input Voltages EN (All varieties) . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V to +13V Output Voltages RO (Note 5). . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.3V) RO (Note 4). . . . . . . . . . . . . . . . . . . -0.5V to (VL + 0.3V) Short Circuit Duration RO (One output at a time) . . . . . . . . . . . . . . . Indefinite ESD Rating . . . . . . . . . See “Electrical Specifications” Table Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 16 Ld SOIC Package (Notes 6, 9). . 78 30 16 Ld TSSOP Package (Notes 6, 9) 104 25 24 Ld QFN Package (Notes 7, 8) . . 42 5 Maximum Junction Temperature (Plastic Package) . . +150°C Maximum Storage Temperature Range . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . VL (Note 4) . . . . . . . . . . . . . . . . . . Temperature Range ISL32X7XEI . . . . . . . . . . . . . . . . . ISL32X7XEF . . . . . . . . . . . . . . . . . Bus Pin Common Mode Voltage Range RO Output Current . . . . . . . . . . . . . . RO Load Capacitance . . . . . . . . . . . . . . . . . . . . 3V to 5.5V . . . . . . . 1.6V to VCC . . . . . . . . . . . . . . . . .-40°C to +85°C . -40°C to +125°C . . . -7V to +12V . . -9mA to +9mA . . . . . . . . . ≤6pF CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. ISL32177E and ISL32277E only. 5. Excluding the ISL32177E and ISL32277E. 6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 9. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL32177E and ISL32277E only); Typicals are at the worst case of VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Notes 10, 14) TEST CONDITIONS TEMP (°C) Full Full Full Full Full 25 Full Full Full Full 25 MIN (Note 13) 2 2.2 2 1.6 0.72*VL TYP 0.4*VL 0.35* VL MAX (Note 13) 0.8 0.6 0.6 0.22*VL UNITS V V V V V V V V V V V PARAMETER Input High Voltage (Logic Pins, Note 17) SYMBOL VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 DC CHARACTERISTICS VL = VCC if ISL32177E or ISL32277E VCC ≤3.6V VCC ≤ 5.5V 2.7V ≤ VL < 3.0V (ISL32177E and ISL32277E Only) 2.3V ≤ VL < 2.7V (ISL32177E and ISL32277E Only) 1.6V ≤ VL < 2.3V (ISL32177E and ISL32277E Only) 1.4V ≤ VL < 1.6V (ISL32177E and ISL32277E Only) VL = VCC if ISL32177E and ISL32277E VL ≥ 2.7V (ISL32177E and ISL32277E Only) 2.3V ≤ VL < 2.7V (ISL32177E and ISL32277E Only) 1.6V ≤ VL < 2.3V (ISL32177E and ISL32277E Only) 1.4V ≤ VL < 1.6V (ISL32177E and ISL32277E Only) Input Low Voltage (Logic Pins, Note 17) VIL1 VIL2 VIL3 VIL4 VIL5 7 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL32177E and ISL32277E only); Typicals are at the worst case of VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Notes 10, 14) (Continued) TEST CONDITIONS EN, EN, ENX, SHDNEN = 0V or VCC EN12, EN34 = 0V or VCC (ISL32X75E Only) -7V ≤ VCM ≤ 12V TEMP (°C) Full Full Full MIN (Note 13) -15 -30 -200 TYP MAX (Note 13) 15 30 200 UNITS μA μA mV PARAMETER Logic Input Current Receiver Differential Threshold Voltage Receiver Input Hysteresis Input Current (A, B) Receiver Input Resistance Receiver Output Leakage Current Receiver ShortCircuit Current, VO = High or Low Receiver Output High Voltage SYMBOL IIN1 IIN2 VTH ΔVTH IIN3 RIN IOZ IOS VCM = 0V VCC = 0V or 5.5V -7V ≤ VCM ≤ 12V EN = 0V, 0 ≤ VO ≤ VCC (0 to VL if ISL32177E or ISL32277E) EN = 1, 0V ≤ VO ≤ VCC (0 to VL if ISL32177E or ISL32277E) 20Mbps Versions 80Mbps Versions VIN = 12V VIN = -7V 25 Full Full Full Full Full Full Full -0.2 48 -10 VCC - 1 30 - 0.2 10 ±100 ±155 - mV mA mA kΩ μA mA mA V VOH1 IO = -8mA, VID = 200mV VCC ≥ 4.5V (VL = VCC if ISL32177E or ISL32277E) IO = -6mA, VID = 200mV VCC ≥ 3.0V (VL = VCC if ISL32177E or ISL32277E) Full 2.4 - - V VOH2 VOH3 VOH4 Receiver Output Low Voltage VOL1 VOL2 VOL3 SUPPLY CURRENT No-Load Supply Current, 80Mbps Versions 80ICC IO = -2mA, VL ≥ 2.3V IO = -1.5mA, VL = 1.8V IO = -200μA, VL ≥ 1.4V ISL32177E and ISL32277E Only Full Full Full Full Full Full VL - 0.3 VL - 0.3 VL - 0.2 - - 0.4 0.4 0.4 V V V V V V IO = 8mA, VID = -200mV, VL = VCC if ISL32177E, ISL32277E IO = 5mA, VL ≥ 1.8V IO = 2mA, VL ≥ 1.4V ISL32177E and ISL32277E Only ISL32177E and ISL32277E Only EN = 1, or EN = 0 (ISL32173E and ISL32177E), or EN12 = EN34 = 1 (ISL32175E), or EN1 = EN2 = EN3 = EN4 = 1 (ISL32177E) EN12 = 1 and EN34 = 0, or vice versa (ISL32175E only), or if only two channels are enabled on the ISL32177E SHDNEN = 0, EN1 = EN2 = EN3 = EN4 = 0 or EN = 0 and EN = 1 (ISL32177E only) Full - - 15 mA 80ICC1/2 Full - - 8.5 mA 80ICCD Full - - 2.5 mA 8 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL32177E and ISL32277E only); Typicals are at the worst case of VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Notes 10, 14) (Continued) TEST CONDITIONS EN = 1, or EN = 0 (ISL32273E and ISL32277E), or EN12 = EN34 = 1 (ISL32275E), or EN1 = EN2 = EN3 = EN4 = 1 (ISL32277E) EN12 = 1 and EN34 = 0, or vice versa (ISL32275E only), or if only two channels are enabled on the ISL32277E SHDNEN = 0, EN1 = EN2 = EN3 = EN4 = 0 or EN = 0 and EN = 1 (ISL32277E only) All outputs disabled (Note 18) (all except ISL32X75E) All outputs disabled (Note 19) (all except ISL32X73E) ESD PERFORMANCE RS-485 Pins (A, B) IEC61000-4-2, From Bus Pins to GND Air Gap Contact 25 25 25 25 25 Full Full Full Full Full Full Full Full Full Full 20 ±16.5 ±8 ±15 ±8 500 37 2.7 3 4 150 155 19 19 55 6 8 20 190 190 30 30 850 kV kV kV kV V Mbps ns ns ns ns ns ns ns ns ns TEMP (°C) Full MIN (Note 13) TYP MAX (Note 13) 5.5 UNITS mA PARAMETER No-Load Supply Current, 20Mbps Versions SYMBOL 20ICC 20ICC1/2 Full - - 3.5 mA 20ICCD Shutdown Supply Current ISHDN Full Full Full - - 1.2 15 60 mA μA μA Human Body Model, From Bus Pins to GND All Pins HBM Machine Model Maximum Data Rate Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | Prop Delay Skew Chan-to-Chan Prop Delay Skew Part-to-Part Receiver Enable to Output High Receiver Enable to Output Low Receiver Disable from Output High Receiver Disable from Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low Maximum Data Rate fMAX VID = ±1.5V, CL=15pF RECEIVER SWITCHING CHARACTERISTICS (ISL32273E, ISL32275E, ISL32277E, 20Mbps) tPLH, tPHL (Figure 1) tSKD tSKC-C tSKP-P tZH tZL tHZ tLZ (Figure 1) (Figure 1), (Note 11) (Figure 1), (Note 12) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 15, 21) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 15, 21) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 16, 20) tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 16, 20) Full - - 850 ns RECEIVER SWITCHING CHARACTERISTICS (ISL32173E, ISL32175E, ISL32177E, 80Mbps) fMAX VID = ±1.5V, CL≤ 15pF VCC≤ 3.6V VCC > 3.6V VID = ±1.5V, CL≤ 6pF, 3.6V ≤ VCC ≤ 5.5V Full Full Full 80 20 80 Mbps Mbps Mbps 9 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL32177E and ISL32277E only); Typicals are at the worst case of VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Notes 10, 14) (Continued) TEST CONDITIONS TEMP (°C) Full Full Full Full Full Full Full Full Full MIN (Note 13) 7 TYP 11 0.4 0.7 1.2 57 59 18 19 MAX (Note 13) 16 2 4 8 75 75 30 30 850 UNITS ns ns ns ns ns ns ns ns ns PARAMETER Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | Prop Delay Skew Chan-to-Chan Prop Delay Skew Part-to-Part Receiver Enable to Output High Receiver Enable to Output Low Receiver Disable from Output High Receiver Disable from Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low NOTES: SYMBOL tPLH, tPHL (Figure 1) tSKD tSKC-C tSKP-P tZH tZL tHZ tLZ (Figure 1) (Figure 1), (Note 11) (Figure 1), (Note 12) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 15, 21) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 15, 21) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 16, 20) tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 16, 20) Full - - 850 ns 10. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at the same test conditions. 12. tSKP-P is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to enable the output(s) under test. 15. For ISL32177E and ISL32277E, keep SHDNEN low to avoid entering SHDN. For ISL32175E and ISL32275E ensure that at least one channel remains enabled to prevent SHDN. 16. For ISL32177E and ISL32277E, keep SHDNEN high to enter SHDN when all drivers are disabled. 17. Logic Pins are the enable variants and SHDNEN. 18. EN low and EN high on the ISL32X73E. SHDNEN, EN, EN1-EN4 all high and EN low on the ISL32X77E. 19. EN12 and EN34 low on ISL32X75E. SHDNEN high, with EN1-EN4 low plus EN and EN high on the ISL32X77E. 20. Shutdown is entered by simultaneously disabling all four outputs for at least 600ns. 21. Does not apply to the ISL32173E nor the ISL32273E; only the EN from SHDN parameters apply to these two parts. 10 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Test Circuits and Waveforms EN +1.5V B A R RO 15pF A 1.5V 1.5V 0V tPLH SIGNAL GENERATOR RO 50% tPHL VCC OR VL 50% 0V 3V FIGURE 1A. TEST CIRCUIT FIGURE 1B. MEASUREMENT POINTS FIGURE 1. RECEIVER PROPAGATION DELAY EN GND SIGNAL GENERATOR B A R RO 1kΩ SW 15pF VCC OR VL GND 3V OR VL EN 1.5V 1.5V 0V tZH, tZH(SHDN) tHZ OUTPUT HIGH LOWER OF 1.5V OR VL/2 tLZ LOWER OF 1.5V OR VL/2 OUTPUT LOW PARAMETER tHZ tLZ tZH (Notes 15, 21) tZL (Notes 15, 21) tZH(SHDN) (Notes 16, 20) tZL(SHDN) (Notes 16, 20) A +1.5V -1.5V +1.5V -1.5V +1.5V -1.5V SW GND VCC GND VCC GND VCC RO V VOH - 0.5V OH 0V tZL, tZL(SHDN) RO VCC OR VL VOL + 0.5VV OL FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. RECEIVER ENABLE AND DISABLE TIMES Application Information RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. Load (UL)” requirement of 12kΩ minimum. Thus, these products are known as “one-quarter UL” receivers and there can be up to 128 of these devices on a network while still complying with the RS-485 loading specification. Receiver inputs function with common mode voltages as great as +9V/-7V outside the power supplies (i.e., +12V and -7V with VCC = 3.0V), making them ideal for long networks where induced voltages, and ground potential differences are realistic concerns. All the receivers include a “fail-safe open” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). All receivers easily support a 20Mbps data rate, and the ISL32173E, ISL32175E, and ISL32177E support data rates up to 80Mbps. All receiver outputs are tri-statable, with the enable scheme varying by part type (see next section). Receiver Features These devices utilize differential receivers for maximum noise immunity and common mode rejection. Input sensitivity is better than ±200mV, as required by the RS-422 and RS-485 specifications. Receiver input resistance of 48kΩ surpasses the RS-422 specification of 4kΩ and is four times the RS-485 “Unit 11 Receiver Enable Functions All product types include functionality to allow disabling of the Rx outputs. The ISL32X73E types feature group (all four Rx) enable functions that are active high (EN) or active low (EN). Receivers enable when EN = 1, or when EN = 0, and they disable only when EN = 0 and EN = 1. ISL32X75E versions use active high paired enable FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E functions (EN12 and EN34) that enable (when high) or disable (when low) the corresponding pairs of Rx. All four of these enable pins have internal pull-up resistors to VCC, but unused enable pins that need to be high (e.g., EN when using the EN input for enable control, or EN12 and EN34 when using always enabled receivers) should always be connected externally to VCC. If VCC transients might exceed 7V, then inserting a series resistor between the input(s) and VCC limits the current that flows if the input’s ESD protection starts conducting. 1 OF 4 CHANNELS ENX EN EN VCC VCC VCC CHX EN The ISL32177E and ISL32277E include a VL pin that powers the logic inputs (enables, SHDNEN) and the RO outputs. These pins interface with “logic” devices such as UARTs, ASICs, and μcontrollers, and today most of these devices use power supplies significantly lower than 3.3V. Thus, a 5V or 3.3V RO output level from an ISL32X77E IC might seriously overdrive and damage the logic device input (Figure 4). Similarly, the logic device’s low VOH might not exceed the VIH of the ISL32X77E’s 3.3V or 5V powered enable input. Connecting the ISL32X77E’s VL pin to the power supply of the logic device - as shown in Figure 4 - limits the ISL32X77E’s VOH to VL, and reduces its logic input switching points to values compatible with the logic device’s output levels. Tailoring the logic pin input switching points and RO output levels to the supply voltage of the UART, ASIC, or μcontroller eliminates the need for a level shifter/translator between the two ICs. VCC = +3.3V VCC = +2V FIGURE 3. ISL32X77E ENABLE LOGIC The ISL32177E and ISL32277E have the most flexible enable scheme. Their six enable pins allow for group, paired, or individual channel enable control. Figure 3 details the ISL32X77E’s internal enable logic. To utilize a group enable function, connect all the ENX pins high, and handle the EN and EN pins as described in the previous paragraph. For paired enables, connect EN and EN high (for the lowest current in SHDN mode, if SHDN is used) and tie EN1 and EN2 together, and EN3 and EN4 together. For individual channel enables, again connect EN and EN high, and drive the appropriate ENX (active high) for the particular channel. All six enable pins incorporate pull-up resistors to VCC, but unused enable pins of any type should be externally connected high, rather than being left floating. Connecting to VCC is the best choice, but VL may be utilized as long as SHDN power isn’t a primary concern (for each VL connected input, ICC increases by (VCC - VL)/600kΩ). If VCC or VL transients might exceed 7V, then inserting a series resistor between the input(s) and the supply limits the current that will flow if the input’s ESD protection starts conducting. RO VOH = 3.3V RXD ESD DIODE EN GND VIH ≥ 2V VOH ≤ 2V RXEN GND ISL32X7XE VCC = +3.3V TO 5V UART/PROCESSOR VCC = +2V VL RO VOH = 2V RXD ESD DIODE EN GND VIH = 0.9V VOH ≤ 2V RXEN GND ISL32X77E UART/PROCESSOR Wide Supply Range The ISL32X7XE design operates with a wide range of supply voltages from 3.0V to 5.5V, and the receivers meet the RS-485 specs for that full supply voltage range. 5.5V TOLERANT LOGIC PINS Logic input pins (enables, SHDNEN) contain no ESD nor parasitic diodes to VCC (nor to VL), so they withstand input voltages exceeding 5.5V regardless of the VCC and VL voltages (see Figure 6). FIGURE 4. USING VL PIN TO ADJUST LOGIC LEVELS Logic Supply (VL Pin, ISL32177E and ISL32277E) Note: Power up VCC before powering up the VL supply. VL can be anywhere from VCC down to 1.4V, but the data rate drops off dramatically below VL = 1.6V. Table 2 indicates typical VIH and VIL values (applicable to both speed grades) for various VL settings, and also lists the ISL32177E’s typical data rate versus VL. The ISL32277E typically runs at 20Mbps for VL ≥ 1.6V, and drops to 10Mbps to 15Mbps at VL=1.4V. Prop delays, skews, and transition times increase at lower VL, as shown in Figures 17 through 29. 12 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E TABLE 2. TYPICAL VIH, VIL AND DATA RATE vs. VL FOR VCC = 3.3V OR 5V VL (V) 1.4 1.6 1.8 2.3 2.7 3.3 VIH (V) 0.55 0.6 0.8 1 1.1 1.3 VIL (V) 0.5 0.55 0.7 0.9 1 1.2 ISL32177E DATA RATE (Mbps) 25 50 65 70 75 80 configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device’s RS-485 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-485 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The A and B RS-485 pins withstand ±16.5kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. These Quad receivers survive ±8kV contact discharges on the RS-485 pins. Neglecting the RO IOH currents, the quiescent VL supply current (IL) is typically less than 1μA for enable input voltages at ground or VL, as shown in Figure 6. Enable pin pull-up resistors connect to VCC, so the current due to a low enable input adds to ICC rather than to IL. Hot Plug Function When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-485 control lines (EN, EN, ENX) is unable to ensure that the RS-485 Rx outputs are kept disabled. If the equipment is connected to the bus, a receiver activating prematurely during power up may generate RO transitions that could cause interrupts. To avoid this scenario, this family incorporates a “Hot Plug” function. During power up, circuitry monitoring VCC ensures that the Rx outputs remain disabled for a period of time, regardless of the state of the enables. This gives the processor/ASIC a chance to stabilize and drive the RS-485 control lines to the proper states. Data Rate, Cables, and Terminations RS-485 and RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Networks operating at 80Mbps are limited to lengths much less than 100’ (30m), while a 20Mbps version can operate at full data rates with lengths up to 200’ (60m). Any of these ICs may be used at slower data rates over longer cables, but there are some limitations for the 80Mbps versions. The 80Mbps Rx is optimized for high speed operation, so its output may glitch if the Rx input differential transition times are too slow. Keeping the transition times below 500ns, which equates to a Tx driving a 1000’ (305m) CAT 5 cable, yields excellent performance over the full operating temperature range. Twisted pair is the cable of choice for RS-485 and RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. When using these receivers, proper termination is imperative to minimize reflections. Short networks using slew rate limited transmitters need not be terminated, but terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on a bus with multiple receivers) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at ESD Protection All pins on these devices include class 3 (>8kV) Human Body Model (HBM) ESD protection structures, but the RS-485 pins (receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of ±15kV HBM, and ±16.5kV IEC 61000-4-2. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. IEC 61000-4-2 Testing The IEC 61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-485 pins in this case), and the IC is tested in its typical application 13 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E both ends. Stubs connecting a transmitter or receiver to the main cable should be kept as short as possible. The ISL32X77E enter the low power SHDN mode if SHDNEN is high, and if all four Rx are disabled for at least 600ns. This is accomplished by driving EN low and EN high, or by driving all four ENX inputs low. Enable times increase if the IC was in SHDN, so if enable time is more important than SHDN supply current, tying the SHDNEN pin low defeats the low power SHDN feature. In this mode, the supply current drops to 1mA to 2mA when all four Rx are disabled, but the enable time of any Rx remains below 200ns. Remember that all enable pins have pull-up resistors on them, so each pin that is low during SHDN adds up to 15μA to the SHDN supply current. The SHDN supply current entries in the “Electrical Specifications” table on page 9 include the resistor currents of the pins indicated to be in the low state. Low Power Shutdown Mode These BiCMOS receivers all use a fraction of the power required by their bipolar counterparts, but they also include a shutdown (SHDN) feature that reduces the already low quiescent ICC to a microamp trickle. These devices enter shutdown only when all four receivers disable (see “Truth Tables” on page 4) for at least 600ns. The ISL32X73E types enter SHDN whenever EN is low and EN is high. ISL32X75E types enter SHDN only if both EN12 and EN34 are low. Note that the ISL32X75E enable times increase significantly when enabling from the SHDN condition. 14 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Performance Curves 11 10 9 8 ICC (mA) 7 6 5 4 3 ISL3227XE VCC = VL = 3.3V -15 EN = VCC, EN = 0V VCC = VL = 5V ISL3217XE VCC = VL = 3.3V VCC = VL = 5V CL= 15pF, VCC = VL = 3.3V or 5V, TA = +25°C; Unless Otherwise Specified. VL Notes Apply To The ISL32177E And ISL32277E Only. 180 160 140 120 IL (μA) 100 80 60 40 20 0 0 1 VL ≤ 2V VL = 3.3V VL = 2.5V 2 3 4 EN VOLTAGE (V) 5 6 7 VCC = 5V OR 3.3V DATA FOR ANY 1 ENABLE PIN VL = 5V (VCC = 5V ONLY) 2 -40 10 35 60 85 TEMPERATURE (°C) 110 125 FIGURE 5. SUPPLY CURRENT vs TEMPERATURE FIGURE 6. VL SUPPLY CURRENT vs ENABLE PIN VOLTAGE (ISL32X77E ONLY) RECEIVER OUTPUT CURRENT (mA) RECEIVER OUTPUT CURRENT (mA) 120 100 80 60 40 20 0 VOH, +25°C VCC = VL = 5V 60 50 40 30 VOH, +125°C 20 10 0 VCC = 5V OR 3.3V, VL = 3.3V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 RECEIVER OUTPUT VOLTAGE (V) VOH, +25°C VOL, +25°C VOL, +85°C VOL, +125°C VOH, +85°C VOL, +25°C VOL, +85°C VOL, +125°C VOH, +85°C VOH, +125°C 0 1 2 3 4 5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 7. ISL3217XE RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 8. ISL3217XE RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE RECEIVER OUTPUT CURRENT (mA) 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 VOH, +125°C VOH, +25°C VOL, +25°C VOL, +85°C VOL, +125°C VOH, +85°C RECEIVER OUTPUT CURRENT (mA) 40 VCC = 5V OR 3.3V, VL = 2.5V 18 16 14 12 10 8 6 4 2 0 0 VCC = 5V OR 3.3V, VL = 1.8V VOL, +25°C VOL, +85°C VOL, +125°C VOH, +25°C VOH, +85°C VOH, +125°C 2.0 2.5 0.5 1.0 1.5 1.8 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) FIGURE 9. ISL32177E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 10. ISL32177E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 15 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Performance Curves 10 RECEIVER OUTPUT CURRENT (mA) 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 VOH, +125°C VOH, -40°C VOH, +25°C VOH, +85°C VCC = 5V or 3.3V, VL = 1.5V VOL, +85°C VOL, +25°C CL= 15pF, VCC = VL = 3.3V or 5V, TA = +25°C; Unless Otherwise Specified. VL Notes Apply To The ISL32177E And ISL32277E Only. 70 RECEIVER OUTPUT CURRENT (mA) 60 50 40 30 20 10 0 VOH, +85°C VOH, +125°C VCC = VL = 5V VOH, +25°C VOL, +25°C VOL, +85°C VOL, +125°C VOL, +125°C 0.6 0.8 1.0 1.2 1.41.5 0 1 2 3 4 5 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) FIGURE 11. ISL32177E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 12. ISL3227XE RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE RECEIVER OUTPUT CURRENT (mA) 35 30 25 20 15 10 5 0 VOH, +125°C VOH, +25°C VOL, +25°C VOL, +85°C VOL, +125°C VOH, +85°C RECEIVER OUTPUT CURRENT (mA) 40 25 VCC = 5V OR 3.3V, VL = 2.5V VOL, +25°C VOL, +85°C VOL, +125°C 20 15 VOH, +25°C 10 VOH, +125°C VOH, +85°C 5 VCC = 5V OR 3.3V, VL = 3.3V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 RECEIVER OUTPUT VOLTAGE (V) 0 0 0.5 1.0 1.5 2.0 2.5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 13. ISL3227XE RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 11 RECEIVER OUTPUT CURRENT (mA) 10 FIGURE 14. ISL32277E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 6 RECEIVER OUTPUT CURRENT (mA) 5 4 3 2 1 0 0 VOH, +125°C VOH, -40°C VOH, +25°C 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5 VOH, +85°C VCC = 5V OR 3.3V, VL = 1.8V VOL, +25°C VOL, +85°C VCC = 5V or 3.3V, VL = 1.5V VOL, +85°C VOL, +25°C VOL, +125°C 8 VOL, +125°C 6 VOH, +25°C VOH, +125°C 2 VOH, +85°C 4 0 0 0.5 1.0 1.5 1.8 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) FIGURE 15. ISL32277E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 16. ISL32277E RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 16 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Performance Curves 20 18 16 14 VL = 1.8V 12 VL = 2.5V 10 VL = 5V 8 -40 -15 10 35 60 85 VL = 1.5V VCC = 5V CL= 15pF, VCC = VL = 3.3V or 5V, TA = +25°C; Unless Otherwise Specified. VL Notes Apply To The ISL32177E And ISL32277E Only. 3.5 3.0 2.5 SKEW (ns) 2.0 1.5 1.0 VL = 1.8V VL = 1.5V |tPLH - tPHL| VCC = 5V PROPAGATION DELAY (ns) VL = 3.3V VL = 2.5V VL = 3.3V VL = 5V -15 10 35 60 85 110 125 0.5 0 -40 110 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 17. ISL3217XE RECEIVER PROPAGATION DELAY vs TEMPERATURE 20 18 VL = 1.5V 16 14 VL = 1.8V 12 10 8 -40 VL = 2.5V VL = 3.3V VCC = 3.3V FIGURE 18. ISL3217XE RECEIVER SKEW vs TEMPERATURE 3.0 2.5 2.0 |tPLH - tPHL| VL = 1.5V VCC = 3.3V PROPAGATION DELAY (ns) SKEW (ns) 1.5 1.0 0.5 0 -40 VL = 3.3V VL = 2.5V -15 10 35 60 85 110 125 TEMPERATURE (°C) VL = 1.8V -15 10 35 60 85 110 125 TEMPERATURE (°C) FIGURE 19. ISL3217XE RECEIVER PROPAGATION DELAY vs TEMPERATURE 54 52 PROPAGATION DELAY (ns) 50 48 46 44 42 40 38 36 34 -40 -15 10 VL = 1.8V VL = 3.3V VL = 2.5V VL = 5V VL = 1.5V VCC = 5V FIGURE 20. ISL3217XE RECEIVER SKEW vs TEMPERATURE 8 7 6 SKEW (ns) 5 4 3 2.5V ≤ VL ≤ VCC 2 1 VL = 1.8V |tPLH - tPHL| VL = 1.5V VCC = 5V 35 60 85 110 125 0 -40 -15 10 35 60 85 110 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 21. ISL3227XE RECEIVER PROPAGATION DELAY vs TEMPERATURE FIGURE 22. ISL3227XE RECEIVER SKEW vs TEMPERATURE 17 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Performance Curves 57 VCC = 3.3V CL= 15pF, VCC = VL = 3.3V or 5V, TA = +25°C; Unless Otherwise Specified. VL Notes Apply To The ISL32177E And ISL32277E Only. 7 6 VL = 1.5V SKEW (ns) 5 4 3 2 1 0 -40 VL = 1.8V VL = 2.5V VL = 3.3V |tPLH - tPHL| VCC = 3.3V PROPAGATION DELAY (ns) 52 VL = 1.5V 47 42 VL = 1.8V VL = 3.3V VL = 2.5V 37 32 -40 -15 10 35 60 85 110 125 -15 10 35 60 85 110 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 23. ISL3227XE RECEIVER PROPAGATION DELAY vs TEMPERATURE RECEIVER OUTPUT (V) RECEIVER INPUT (V) FIGURE 24. ISL3227XE RECEIVER SKEW vs TEMPERATURE RECEIVER OUTPUT (V) RECEIVER INPUT (V) 80Mbps 1 0 -1 A-B 20Mbps 1 0 -1 A-B 5 4 3 2 1 0 VCC = 5V, CL = 6pF 5 4 3 2 1 0 VCC = 5V VCC = 3.3V VCC = 3.3V, CL = 15pF TIME (4ns/DIV) TIME (20ns/DIV) FIGURE 25. ISL3217XE RECEIVER WAVEFORMS RECEIVER OUTPUT (V) RECEIVER INPUT (V) RECEIVER OUTPUT (V) RECEIVER INPUT (V) FIGURE 26. ISL3227XE RECEIVER WAVEFORMS 80Mbps 1 0 -1 A-B CL = 6pF VCC = 5V 80Mbps 1 0 -1 A-B VCC = 3.3V 4 3 2 1 0 VL = 3.3V VL = 2.5V VL = 1.8V VL = 1.6V 2.5 2.0 1.5 1.0 0.5 0 VL = 2.5V VL = 1.8V VL = 1.6V TIME (4ns/DIV) TIME (4ns/DIV) FIGURE 27. ISL32177E RECEIVER WAVEFORMS FIGURE 28. ISL32177E RECEIVER WAVEFORMS 18 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Typical Performance Curves RECEIVER OUTPUT (V) RECEIVER INPUT (V) 20Mbps 1 0 -1 A-B CL= 15pF, VCC = VL = 3.3V or 5V, TA = +25°C; Unless Otherwise Specified. VL Notes Apply To The ISL32177E And ISL32277E Only. VCC = 5V OR 3.3V Die Characteristics SUBSTRATE AND QFN THERMAL PAD POTENTIAL (POWERED UP): GND VL = 2.5V VL = 1.8V VL = 1.6V 2.5 2.0 1.5 1.0 0.5 0 PROCESS: Si Gate BiCMOS VL = 1.4V TIME (20ns/DIV) FIGURE 29. ISL32277E RECEIVER WAVEFORMS Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/19/09 REVISION FN7529.0 Initial release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL32173E,ISL32175E,ISL32177E,ISL32273E, ISL32275E, ISL32277E To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 19 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 16 0° 8° 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0° 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 20 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Package Outline Drawing L24.4x4C 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06 4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25) PIN 1 INDEX AREA 18 1 4.00 2 . 50 ± 0 . 15 13 (4X) 0.15 12 7 24X 0 . 4 ± 0 . 1 0.10 M C A B 24X 0 . 23 + 0 . 07 4 - 0 . 05 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 ( 3 . 8 TYP ) C BASE PLANE SIDE VIEW SEATING PLANE 0.08 C ( 2 . 50 ) ( 20X 0 . 5 ) C ( 24X 0 . 25 ) ( 24X 0 . 6 ) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 21 FN7529.0 November 19, 2009 ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. A A1 A2 b c D E E1 e H 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max ±0.05 ±0.05 +0.05/-0.06 +0.05/-0.06 ±0.10 Basic ±0.10 Basic ±0.15 Reference E E1 1 B TOP VIEW (N/2) 0.20 C B A 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 L L1 b 0.10 C N LEADS SIDE VIEW 0.10 M C A B SEE DETAIL “X” Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0° - 8° For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN7529.0 November 19, 2009