ISL54065

® ISL54065 Data Sheet December 19, 2008 FN6583.0 +1.8V to +6.5V, Sub-ohm, Click and Pop Elimination, Dual SPDT w/ Enable, Analog Switch with Negative Signal Capability The Intersil ISL54065 device is a low ON-resistance, low voltage, bi-directional, dual single-pole/double-throw (SPDT) analog switch. It is designed to operate from a single +1.8V to +6.5V supply and pass signals that swing up to 6.5V below the positive supply rail. Targeted applications include battery powered equipment that benefit from low rON (0.56Ω), low power consumption (8nA) and fast switching speeds (tON = 55ns, tOFF = 18ns). The digital inputs are1.8V logic-compatible up to a +3V supply. The ISL54065 also features integrated circuitry to eliminate click and pop noise to an audio speaker. The ISL54065 is offered in a small form factor package, alleviating board space limitations. It is available in a tiny 12 Ld 2.2x1.4mm µTQFN. The ISL54065 is a committed dual single-pole/double-throw (SPDT) that consist of two normally open (NO) and two normally closed (NC) switches with independent logic control. This configuration can be used as a dual 2-to-1 multiplexer. TABLE 1. FEATURES AT A GLANCE ISL54065 Number of Switches SW 4.3V rON 4.3V tON/tOFF 2.7V rON 2.7V tON/tOFF 1.8V rON 1.8V tON/tOFF Packages 2 SPDT or 2-1 MUX 0.65Ω 43ns/23ns 0.9Ω 55ns/18ns 1.8Ω 145ns/28ns 12 Ld µTQFN Features • Pb-free (RoHS Compliant) • Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V • Negative Signal Capability (up to V+ - 6.5V) • Enable Pin to Disable All Switches • Integrated Click and Pop Elimination Circuitry • Click and Pop Circuitry Disable Pin • ON-Resistance (rON) - V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52Ω - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω - V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9Ω - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8Ω • rON Matching Between Channels . . . . . . . . . . . . . . . . . 10mΩ • rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.33Ω • Low THD+N @ 32Ω Load . . . . . . . . . . . . . . . . . . . . . . .0.02% • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . 8nA • Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns • ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV • Guaranteed Break-Before-Make • 1.8V Logic Compatible (+3V supply) • Low I+ Current when VINH is not at the V+ Rail • Available in 12 Ld 2.2mm x 1.4mm µTQFN Package Applications • Audio and Video Switching • Battery powered, Handheld, and Portable Equipment - MP3 and Multimedia Players - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement • Medical Equipment Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54065 Pinout (Note 1) ISL54065 (12 LD µTQFN) TOP VIEW NC1 12 COM1 11 NO1 10 Pin Descriptions PIN V+ FUNCTION Supply Voltage(+1.8V to +6.5V). Decouple V+ to ground by placing a 0.1µF capacitor at the V+ and GND supply lines as near as the IC as possible. Ground Connection Input Select Pin Switch Enable Pin Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Click and Pop Circuitry Enable Pin GND INx GND 1 9 IN1 EN COMx CP 2 CLICK AND POP CIRCUITRY 8 EN NOx NCx V+ 3 7 IN2 CP 4 NC2 5 COM2 6 NO2 NOTE: 1. Switches Shown for EN = Logic “1” and INx = Logic “0”. Truth Table EN 0 1 1 1 1 IN1 X 0 0 1 1 IN2 X 0 1 0 1 NC1 OFF ON ON OFF OFF NC2 OFF ON OFF ON OFF NO1 OFF OFF OFF ON ON NO2 OFF OFF ON OFF ON NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply. Ordering Information PART NUMBER (Note) ISL54065IRUZ-T* PART MARKING GG TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-Free) 12 Ld Thin µTQFN (Tape and Reel) PKG. DWG. # L12.2.2x1.4A *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6583.0 December 19, 2008 ISL54065 Absolute Maximum Ratings V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltages NOx, NCx (Note 2) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) INx, EN (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) Continuous Current NOx, NCx, or COMx . . . . . . . . . . . . . . ±300mA Peak Current NOx, NCx, or COMx (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV Thermal Information Thermal Resistance (Typical) θJA (°C/W) 12 Ld µTQFN Package (Note 3) . . . . . . . . . . . . . . . 155 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . (V+ - 6.5)V to V+ CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on NCx, NOx, INx, EN, CP, or COMx exceeding V+ or GND by the specified amount are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, VEN = VINH, VCP = VINL (Note 4), unless otherwise specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS Ω Ω mΩ mΩ Ω Ω nA µA nA µA PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON rON Matching Between Channels, ΔrON rON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion -3dB Bandwidth NOx or NCx OFF Capacitance, COFF V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ -6.5) to V+ (see Figure 5 ) V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ -6.5) to V+ (Note 7) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = 5V, -1.5V V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float 25 Full 25 Full 25 Full 25 Full 25 Full - 0.52 0.68 10 13.1 0.11 0.14 -8.13 -0.4 -4.42 -0.33 - V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) RL = 50Ω, CL = 5pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz, VNO or VNC = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω VCOM = 1VRMS, RL = 50Ω, CL = 5pF f = 1MHz (see Figure 7) 25 Full 25 Full Full 25 25 25 25 25 25 25 - 35 50 16 22 18 170 60 -75 0.02 35 36 100 - ns ns ns ns ns pC dB dB % MHz pF pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 3 FN6583.0 December 19, 2008 ISL54065 Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, VEN = VINH, VCP = VINL (Note 4), unless otherwise specified. (Continued) TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, VINx = 0V or V+ 25 Full - 0.008 1.41 0.1 - µA µA DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VINx = 0V or V+ Full Full 25 Full 2.4 -0.1 0.3 0.8 0.1 V V µA µA Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VEN = V+, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (see Figure 5 ) V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (Note 7) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = 4.3V, -1.2V V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float 25 Full 25 Full 25 Full 25 Full 25 Full -0.1 -1 -0.1 -1 0.65 0.72 10 15 0.1 0.14 -0.33 -0.33 0.1 1 0.1 1 Ω Ω mΩ mΩ Ω Ω µA µA µA µA rON Matching Between Channels, ΔrON rON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) RL = 50Ω, CL = 5pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz, VNO or VNC = 1VRMS (see Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω f = 1MHz (see Figure 7) 25 Full 25 Full Full 25 25 25 25 25 25 - 43 50 23.1 23.2 22 200 60 -75 0.025 36 100 - ns ns ns ns ns pC dB dB % pF pF Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 4.5V, VIN = 0V or V+ 25 Full - 0.003 0.9 0.1 - µA µA 4 FN6583.0 December 19, 2008 ISL54065 Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VEN = V+, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS V+ = 4.2V, VIN = 2.85V TEMP (°C) 25 MIN (Notes 5, 6) TYP 0.78 MAX (Notes 5, 6) UNITS 12 µA PARAMETER Positive Supply Current, I+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Full Full 25 Full 1.6 -0.5 0.2 0.5 0.5 V V µA µA Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VEN = V+, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 8) V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (Notes 7, 9) 25 Full 25 Full 25 Full - 0.9 0.96 10 17 0.33 0.35 0.5 0.55 Ω Ω mΩ mΩ Ω Ω rON Matching Between Channels, ΔrON rON Flatness, RFLAT(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω , CL = 35pF (see Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω , CL = 35pF, (See Figure 1) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω , CL = 35pF (see Figure 3) CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) RL = 50Ω, CL = 35pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) RL = 50Ω, CL = 35pF, f = 1MHz, VNO or VNC = 1VRMS (see Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω f = 1MHz (see Figure 7) 25 Full 25 Full Full 25 25 25 25 25 25 55 82 18 24 30 150 60 -75 0.04 36 100 ns ns ns ns ns pC dB dB % pF pF Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 25 25 25 Full 1.4 -0.5 - 0.2 0.5 0.5 - V V µA µA 5 FN6583.0 December 19, 2008 ISL54065 Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VEN = V+, VINH = 1.0V, VINL = 0.4V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (see Figure 5) V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (Note 7) 25 Full 25 Full 25 Full - 1.87 1.97 16 30 1.34 1.43 - Ω Ω mΩ mΩ Ω Ω rON Matching Between Channels, ΔrON rON Flatness, RFLAT(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 3) CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) f = 1MHz (see Figure 7) 25 Full 25 Full Full 25 25 25 145 150 20 22 130 40 36 100 ns ns ns ns ns pC pF pF Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ 25 25 25 Full 1.0 -0.5 - 0.19 0.4 0.5 - V V µA µA NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2 or between NO1 and NO2. 9. Limits established by characterization and are not production tested. 6 FN6583.0 December 19, 2008 ISL54065 Test Circuits and Waveforms V+ V+ LOGIC INPUT 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT SWITCH INPUT NO OR NC COM IN GND RL 50Ω CL 35pF VOUT 50% tr < 5ns tf < 5ns C Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) ----------------------R L + r ON FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ C SWITCH OUTPUT VOUT RG ΔVOUT NO OR NC COM VOUT V+ LOGIC INPUT ON OFF 0V Q = ΔVOUT x CL ON VG GND IN CL LOGIC INPUT Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION FIGURE 2B. TEST CIRCUIT V+ C V+ LOGIC INPUT 0V VNX NO COM NC IN RL 50Ω GND CL 35pF VOUT SWITCH OUTPUT VOUT 90% 0V tBBM LOGIC INPUT FIGURE 3A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 7 FN6583.0 December 19, 2008 ISL54065 Test Circuits and Waveforms (Continued) V+ *50Ω SOURCE C V+ C SIGNAL GENERATOR NO OR NC rON = V1/100mA NO OR NC IN 0V OR V+ VNX 100mA ANALYZER RL COM GND COM GND V1 IN 0V OR V+ Signal direction through switch is reversed, worst case values are recorded. FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT V+ *50Ω SOURCE C V+ C SIGNAL GENERATOR RL NO1 OR NC1 COM1 NO OR NC INX 0V OR V+ IMPEDANCE ANALYZER COM2 NC2 OR NO2 NC GND 50Ω COM GND IN 0V OR V+ ANALYZER Signal direction through switch is reversed, worst case values are recorded. FIGURE 6. CROSSTALK TEST CIRCUIT COM is connected to NO or NC during ON capacitance measurement. FIGURE 7. CAPACITANCE TEST CIRCUIT INx VDC 0V VINx* 0V tD tD 220µF NOx VDC tD = 200ms measured at 50% points. VDC CLICK AND POP CIRCUITRY COMx 220µF NCx *VINx waveform for Click and Pop Elimination on NOx terminal. For Click and Pop Elimination on NCx terminal invert INx. RL FIGURE 8A. CLICK AND POP WAVEFORM FIGURE 8B. CLICK AND POP TEST CIRCUIT FIGURE 8. CLICK AND POP ELIMINATION 8 FN6583.0 December 19, 2008 ISL54065 Detailed Description The ISL54065 is a bidirectional, dual single pole-double throw (SPDT) analog switch that offers precise switching from a single 1.8V to 6.5V supply with low ON-resistance (0.83Ω) and high speed operation (tON = 55ns, tOFF = 18ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (8nA), and a tiny 2.2x1.4mm µTQFN package. The low ON-resistance and RON flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. V+ +RING VCOMx VNCx VNOx CLAMP 1kΩ LOGIC INPUTS GND -RING Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. The ISL54065 contains ESD protection diodes on each pin of the IC (see Figure 9). These diodes connect to either a +Ring or -Ring for ESD protection. To prevent forward biasing the ESD diodes to the +Ring, V+ must be applied before any input signals, and the input signal voltages must remain between recommended operating range. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the V+ rail. Logic inputs can be protected by adding a 1kΩ resistor in series with the logic input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting external Schottky diodes to the signal pins will shunt the fault current to the V+ supply instead of through the internal ESD diodes thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current. FIGURE 9. OVERVOLTAGE PROTECTION Power-Supply and By-Pass Considerations The ISL54065 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 5.5V maximum supply voltage, the ISL54065’s 6.5V maximum supply voltage provides plenty of head room for the 10% tolerance of 5.5V supplies due to overshoot and noise spikes. The minimum recommended supply voltage is 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to “Electrical Specifications” tables, beginning on page 3, and “Typical Performance Curves”, beginning on page 11, for details. V+ and GND also power the internal logic and level shiftiers. The level shiftiers convert the input logic levels to V+ and GND signals levels to drive the analog switch gate terminals. A high frequency decoupling capacitor placed as close to the V+ and GND pin as possible is recommended for proper operation of the switch. A value of 0.1µF is highly recommended. Negative Signal Capability The ISL54065 contains circuitry that allows the analog input signal to swing below ground. The device has an analog signal range of 6.5V below V+ up to the V+ rail (see Figure 16) while maintaining low rON performance. For example, if V+ = 5V, then the analog input signal range is from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V to +2.7V. Click and Pop Operation The ISL54065 contains circuitry that prevents audible click and pop noises that may occur when audio sources are powered on or off. Single supply audio sources are biased at a DC offset that can generate transients during power on/off. A DC blocking capacitor is needed to remove the DC bias at the speaker load. For 32Ω headphones, a 220µF capacitor is 9 FN6583.0 December 19, 2008 ISL54065 typically used to preserve the audio bandwidth. The power on/off transients are AC coupled by the 220µF capacitor to the speaker load causing a click and pop noise. The ISL54065 has shunt switches on the NO and NC pins to eliminate click and pop transients (see Figure 10). These switches are driven complimentary to the main switch. When NC is connected to COM, the shunt switch is active on the NO pin (and vice versa). The shunt switches connect an impedance (140Ω typical, see Figure 25) from the NO/NC pin to ground to discharge any transients that may appear on the NO or NC pins. When the DC bias becomes active at the source, the NO and NC terminals will also have a DC offset due to capacitor dv/dt principle. The DC offset will be discharged through the shunt impedance on the NO and NC terminals instead of the speaker, eliminating click and pop noise. On the ISL54065, the Click and Pop Circuitry is enabled when the CP pin is logic high (>1.4V). The Click and Pop Circuitry may be disabled by tying the CP pin low (